JP2001272655A - Method and device for driving liquid crystal device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driver IC capable of driving a liquid crystal panel with a low current drain even if the liquid crystal panel is increased in size and load. SOLUTION: For a period until a D-A converter 210 selects the next gradation voltages VPx, VNx with the next change-over polarity after output terminals S1-S384 are connected with a common voltage Vcom, an input to the D-A converter 210 is once changed over from an 8-bit digital data signals serially supplied from the outside of a horizontal driver IC and parallel-converted by 8-bit fixed digital data signal to 8-bit fixed digital data signals D1-D8 equal all '1', for displaying the liquid crystal panel with a desired gradation, and thereby the input to an operational amplifier 220 is changed over from the gradation voltage VPx to a gradation voltage VN256 or from the gradation voltage VNx to a gradation voltage VP256 for that period, therefore, a current flowing through a differential amplifying stage included in the operational amplifier 220 can be reduced for the period, and a current drain can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a driving method and a driving device for an active matrix type liquid crystal display device, and more particularly to a driving method and a driving device suitable for driving a liquid crystal display device with low power consumption.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device has, as a liquid crystal panel, a pixel electrode and switching elements constituting pixels, for example, a rear glass substrate on which TFTs (thin film transistors) are formed in a matrix, a common electrode and a common electrode. A glass substrate on the front side on which a color filter is formed is arranged to face each other via a liquid crystal, and a scanning line extending in the horizontal direction and juxtaposed in the vertical direction is provided on the TFT and the pixel electrode. The data lines are arranged in parallel in the horizontal direction. In the liquid crystal panel, a vertical driver IC is connected to a scanning line and a horizontal driver IC is connected to a data line, and a scanning signal is supplied line-sequentially to each scanning line from the vertical driver IC.
Each TFT connected to the scanning line supplied with the scanning signal
Is turned on, the driving voltage simultaneously supplied to each data line from the horizontal driver IC is supplied to the corresponding pixel electrode via the turned-on TFT, and the voltage supplied to the common electrode (hereinafter referred to as the common voltage Vcom). Drives the liquid crystal.

The drive voltage supplied to each pixel electrode must alternately supply a positive voltage and a negative voltage with respect to the common voltage due to the characteristic of the liquid crystal. As positive polarity gradation voltages VP1 to VP256
(One gradation voltage VPx of Vcom <VP1 <VP256> and negative gradation voltages VN1 to VN as negative voltages
One of the gray scale voltages VNx among 256 (Vcom>VN1> VN256) is alternately supplied. Driving methods for alternately supplying the positive voltage and the negative voltage include frame inversion driving for switching every screen (frame), line inversion driving for switching every scanning line (one horizontal line), and one pixel electrode unit. An AC driving method such as switching dot inversion driving has been proposed. In the case of line inversion driving or dot inversion driving, every time one horizontal line is scanned,
In the case of frame inversion driving, a positive voltage and a negative voltage are alternately supplied to the data lines as a driving voltage of the liquid crystal panel every time one frame is scanned, so that the driving voltage has a rising waveform from a negative voltage to a positive voltage. And a falling waveform of a negative voltage from a positive voltage. As the liquid crystal panel becomes larger and the load on each data line increases, the rising waveform and the falling waveform show examples of rising waveforms in FIG. 6 and examples of falling waveforms are not shown, but have gentle slopes. Rise and fall times for obtaining a desired drive voltage are prolonged, which may increase current consumption and cause a problem that writing to a liquid crystal panel is not performed normally. In order to solve this problem, when a positive voltage and a negative voltage are alternately supplied to the data line, there is a proposal to switch the supply of the positive voltage and the negative voltage once after setting the potential of the data line to the common voltage, for example. It is disclosed in Japanese Unexamined Patent Publication No. Hei 11-30975, Japanese Unexamined Patent Publication No. Hei 11-272237, and the like.

Hereinafter, an embodiment of the above proposal will be described with reference to FIGS. 3 and 4. FIG. In FIG. 3, reference numeral 100 denotes a horizontal driver IC, which is assumed to have a capability of performing dot inversion driving on 384 data lines of a liquid crystal panel and displaying 256 gradations. The horizontal driver IC 100 has 384 output terminals S1-S that output a drive voltage to each data line.
384 and the gradation voltages VPx, VN corresponding to each data line.
a D / A converter 110 for alternately supplying x.
A 384 voltage-follower-connected operational amplifier for both rising and falling, which alternately outputs a driving voltage to each data line as a driving voltage by raising the driving capability of the gradation voltages VPx and VNx from the converter 110 120, and 384 A-switches 130 and B-switches 140 for disconnecting the output of each operational amplifier 120 from the data line and connecting to the common voltage Vcom.
From the D / A converter 110 to each operational amplifier 120,
A γ-correction power supply which is supplied serially from the outside of the horizontal driver IC and is supplied from the outside based on 8-bit digital data signals D1 to D8 supplied in parallel from an internal circuit (not shown) corresponding to each data line. Voltage V1 to V
10 and 256 gradation voltages VP1 to V
P256, one of the gray scale voltages VPx and VNx among VN1 to VN256 is 2n-1 (odd) (n = 1 to 192) data lines and 2n (even) for each horizontal line.
The grayscale voltage VPx and the grayscale voltage VNx are alternately selected and supplied to the second data line. Each of the switches 130 and 140 is formed of, for example, a transfer gate formed of a MOS transistor.

The operation of the horizontal driver IC 100 having the above configuration will be described with reference to FIG. An 8-bit digital data signal D1 to D
8, gate enable signal OE, latch signal STB, γ
Corrected power supply voltages V1 to V10 are supplied. When a gate enable signal OE is supplied to a vertical driver IC (not shown) as shown in FIG.
As shown in FIG. 4A, a pulse of the scanning signal Gm is supplied to a certain scanning line in synchronization with the falling and rising of the gate enable signal OE from C, and the next scanning line is scanned after a blanking period. A pulse of the signal Gm + 1 is supplied.

When the gate enable signal OE changes from "H" level to "L" level (a certain scanning signal Gm is at "H" level), while the scanning signal Gm is at "H" level (the gate enable signal OE is at "L" level). 4B), when the latch signal STB becomes “H” level as shown in FIG. 4B, an 8-bit digital signal converted into parallel by an internal circuit (not shown) at the rising edge of the latch signal STB. The data signal is supplied to the D / A converter 110 corresponding to each data line, and the D / A converter 110 supplies 256 gradation voltages VP1 to VP25 to the operational amplifier 120 corresponding to the (2n−1) th data line.
6 is selected and supplied, and is output from the operational amplifier 120 as an output A2n-1 as shown in FIG. 4 (d) and corresponds to the 2n-th data line. One of the 256 gradation voltages VN1 to VN256 to the operational amplifier 120
Nx is selected and supplied, and is output from the operational amplifier 120 as an output A2n (not shown). When the latch signal STB becomes “L” level, the latch signal STB
4C, the A switch 130 is turned on and the B switch 140 is turned off, as shown in FIG. 4C, and the output terminal S2n is output as shown in FIG.
The selected gradation voltage VPx is output to −1, and although not shown, the selected gradation voltage VNx is output to the output terminal S2n.

When the gate enable signal OE goes high (the scanning signal Gm goes low), the A switch 130 is turned off at the rising edge of the gate enable signal OE, as shown in FIG. , And the B switch 140 are turned on, and the common voltage Vcom is output to the output terminal S2n-1 as shown in FIG. 4E, and the common voltage Vcom is also output to the output terminal S2n (not shown). .

Next, the gate enable signal OE becomes "L".
When the level (the next scanning signal Gm + 1 is at the “H” level), the scanning signal Gm + 1 is at the “H” level (the period during which the gate enable signal OE is at the “L” level). As shown in the figure, when the latch signal STB becomes “H” level, the rising edge of the latch signal STB causes
An 8-bit digital data signal converted in parallel by an internal circuit (not shown) is supplied to the D / A converter 110 corresponding to each data line, and the D / A converter 110 corresponds to the 2n-1st data line. Operational amplifier 12
0, one of the 256 grayscale voltages VN1 to VN256 is selected and supplied, and the operational amplifier 120 outputs an output A as shown in FIG.
2n−1, and the operational amplifier 120 corresponding to the 2n-th data line supplies the 256 gray-scale voltage VP
One of the gradation voltages VPx among 1 to VP256 is selected and supplied, and is output from the operational amplifier 120 as an output A2n (not shown). When the latch signal STB becomes “L” level, the A switch 130 is turned on at the falling edge of the latch signal STB as shown in FIG.
Is turned on, and the B switch 140 is turned off. As shown in FIG. 4 (e), the selected gradation voltage VNx is output to the output terminal S2n-1. The output gradation voltage VPx is output.

When the gate enable signal OE goes to "H" level (the scanning signal Gm + 1 goes to "L" level), the rising edge of the gate enable signal OE causes the rising edge of FIG.
As shown in FIG.
The switch 140 is turned on, and the common voltage Vcom is output to the output terminal S2n-1 as shown in FIG.
Although not shown, the common voltage Vcom is also output to the output terminal S2n. As described above, the grayscale voltages VPx and VNx as the drive voltages for the respective data lines are not switched immediately, but are once switched to the potential of the common voltage. As shown, current consumption at the time of switching can be reduced.

[0010]

By the way, as shown in FIG. 4D, even during a period when the output terminal is at the potential of the common voltage Vcom (a period during which the output terminals do not output the gradation voltages VPx and VNx). Meanwhile, the operational amplifier 120 continues to output the selected gradation voltages VPx and VNx,
Also at this time, the operational amplifier is consuming current. As the size of the liquid crystal panel is increased and the number of data lines is increased, the number of operational amplifiers is correspondingly increased and the current consumption cannot be ignored. Therefore, the present invention has been made in order to solve the above-mentioned problems, and it has been noticed that the current flowing through the differential amplifier stage included in the operational amplifier is not constant depending on the gradation voltage value. It is another object of the present invention to provide a driving method and a driving apparatus for a liquid crystal display device in which current consumption is reduced by inputting a grayscale voltage value which requires a small current value flowing through the differential amplifier stage.

[0011]

(1) A method of driving a liquid crystal display device according to the present invention is characterized in that a driving voltage of a data line of a liquid crystal panel to be driven is set to a common voltage based on an n-bit digital data signal. On the other hand, one gray scale voltage of the 2 n gray scales of the positive polarity and the negative polarity is set to D /
When the driving capability is increased by a voltage follower-connected operational amplifier that outputs both a rising waveform and a falling waveform and selected from the A converter, and is output from the output terminal. Output terminal
A method of driving a liquid crystal display device connected to a common voltage, wherein the output terminal is connected to a common voltage and then the D / A
Until the converter selects the next gradation voltage with the next switching polarity, the input of the operational amplifier is a gradation voltage with the next switching polarity that minimizes the current flowing through the operational amplifier. And (2) In the driving method of the liquid crystal display device according to the present invention, in the above item (1), the gradation voltage at which the current flowing through the operational amplifier is the minimum is the gradation voltage at which the maximum potential difference with respect to the common voltage is obtained. There is a feature. (3) The driving method of a liquid crystal display device according to the present invention is characterized in that, in the above item (2), a gradation voltage at which a current flowing through the operational amplifier is minimized is output from the D / A converter. . (4) In the driving method of the liquid crystal display device according to the present invention, in the above item (3), the period from the time when the output terminal is connected to the common voltage to the time when the D / A converter selects the next gradation voltage is used. The digital data signal input to the D / A converter is characterized in that all n bits are at the same level. (5) The driving device for a liquid crystal display device according to the present invention, based on an n-bit digital data signal, has one of two positive-polarity and negative-polarity n-th gradation voltages with respect to a common voltage. A D / A converter for selecting one of the gradation voltages, a voltage follower-connected operational amplifier for outputting both a rising waveform and a falling waveform for increasing the driving capability of the selected gradation voltage and outputting the selected gradation voltage; An output terminal for outputting the output of the amplifier to the data line of the liquid crystal panel to be driven, and when the polarity of the output from the output terminal is switched every predetermined period, the output terminal is once connected to a common voltage. A driving device for the liquid crystal display device, wherein the input terminal of the operational amplifier is connected to the D / A converter during a period from when the output terminal is connected to a common voltage to when the D / A converter selects the next gradation voltage at the next switching polarity. And a current flowing through the operational amplifier has a gray scale voltage in the next switched polarity becomes minimum. (6) In the driving device for a liquid crystal display device according to the present invention, in the above item (5), the gradation voltage at which the current flowing through the operational amplifier is the minimum is the gradation voltage at which the maximum potential difference with respect to the common voltage is obtained. There is a feature. (7) In the driving device for a liquid crystal display device according to the present invention, in the above item (6), a gradation voltage at which a current flowing through the operational amplifier is minimized is output from the D / A converter. . (8) In the liquid crystal display device driving device according to the present invention, in the above item (7), the period from when the output terminal is connected to a common voltage to when the D / A converter selects the next gradation voltage is the same. The digital data signal input to the D / A converter is characterized in that all n bits are at the same level.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to FIGS. In FIG. 1, a horizontal driver IC 200 is described as having a capability of performing dot inversion driving on 384 data lines of a liquid crystal panel and displaying 256 gradations. Horizontal driver IC
Reference numeral 200 denotes 384 output terminals S1 to S384 for outputting a drive voltage to each data line, a D / A converter 210 for alternately supplying grayscale voltages VPx and VNx corresponding to each data line, and a D / A Gradation voltage VP from converter 210
x and VNx are increased in drive capability and alternately output as drive voltages to respective data lines. 384 one-amp type voltage follower-connected operational amplifiers 220 for both rising and falling, and each operational amplifier 220 384 A-switches 230 and B-switches 240 for disconnecting the output of the data line from the data line and connecting to the common voltage Vcom
The input of the D / A converter 210 is serially supplied from the outside of the horizontal driver IC to display a desired gradation on the liquid crystal panel, and is supplied in parallel from an internal circuit (not shown) corresponding to each data line. 384 C-switches 250 and D-switches 260 that switch between 8-bit digital data signals D1 to D8 and fixed 8-bit data signals D1 to D8 = all “1”.
From the D / A converter 210 to each operational amplifier 220,
When the C switch 250 is turned on and the D switch 260 is turned off, a circuit (not shown) inside the horizontal driver IC supplies the data in parallel corresponding to each data line.
Based on the bit digital data signals D1 to D8, the 256 grayscale voltages VP1 to VP256 and V generated by the externally supplied γ correction power supply voltages V1 to V10.
One of the grayscale voltages VPx, V among N1 to VN256
Nx indicates the grayscale voltage VPx and the grayscale voltage V for the 2n-1st data line and the 2nth data line for each horizontal line.
Nx are alternately selected, and when the C switch 250 is off and the D switch 260 is on, an 8-bit fixed digital data signal D1 supplied in parallel from a circuit (not shown) inside the horizontal driver IC is provided. ~
Based on D8 = all “1”, the gradation voltage VP256,
VN256 is supplied by alternately selecting the grayscale voltage VP256 and the grayscale voltage VN256 by the (2n-1) th data line and the 2nth data line for each horizontal line.
The operational amplifier 220 is a one-amplifier system that serves both for rising and falling in order to alternately output the gradation voltages VPx and VNx, and internally has a differential amplification stage for rising and a differential amplifying stage for falling. In the steady state, the differential amplifier stage includes a differential amplifier stage, and when the grayscale voltage VP256 is input, the current flowing through the differential amplifier stage for falling is minimized, and when the grayscale voltage VN256 is input, the differential current for rising is reduced. Since the current flowing through the dynamic amplification stage is minimized, as shown in FIG. 5, in the operational amplifier 220 as a whole, VP256 is used as the positive gradation voltage and VN is used as the negative gradation voltage.
When 256 is input, the current flowing through the operational amplifier 220 is minimized. Switches 230, 240, 250
And 260 are constituted by, for example, transfer gates composed of MOS transistors.

The operation of the horizontal driver IC 200 having the above configuration will be described with reference to FIG. The horizontal driver IC 200 externally receives 8-bit digital data signals D1 to D
8, gate enable signal OE, latch signal STB, γ
Corrected power supply voltages V1 to V10 are supplied. When a gate enable signal OE is supplied to a vertical driver IC (not shown) as shown in FIG. 2B, the vertical driver IC synchronizes with the fall and rise of the gate enable signal OE from FIG. As shown in (1), a pulse of the scanning signal Gm is supplied to a certain scanning line, and a pulse of the scanning signal Gm + 1 is supplied to the next scanning line after a blanking period.

When the gate enable signal OE changes from "H" level to "L" level (a certain scanning signal Gm is at "H" level), the period when the scanning signal Gm is at "H" level (the gate enable signal OE is at "L" level) 2B), when the latch signal STB becomes the “H” level as shown in FIG. 2B, the C switch 250 as shown in FIG. 2C at the rising edge of the latch signal STB.
Is turned on, and the D switch 260 is turned off. In order to display a desired gradation on the liquid crystal panel, an 8-bit signal which is serially supplied from outside the horizontal driver IC and converted into parallel by an internal circuit (not shown) is provided. A digital data signal is applied to the D / A converter 210 corresponding to each data line.
, And one of the 256 grayscale voltages VP1 to VP256 is selected and supplied from the D / A converter 210 to the operational amplifier 220 corresponding to the (2n−1) th data line. , This operational amplifier 220
As shown in FIG. 2D, the data is output as an output A2n-1 and is supplied to the operational amplifier 220 corresponding to the 2n-th data line with 256 grayscale voltages VN1 to VN256.
Is selected and supplied, and the operational amplifier 220 outputs an output A (not shown).
Output as 2n. When the latch signal STB goes to "L" level, the A switch 230 is turned on at the falling edge of the latch signal STB, as shown in FIG.
And the B switch 240 is turned off, and FIG.
As shown in the figure, the selected gradation voltage V is applied to the output terminal S2n-1.
Px is output, and although not shown, the selected gradation voltage VNx is output to the output terminal S2n.

When the gate enable signal OE becomes "H" level (the scanning signal Gm becomes "L" level), the rising edge of the gate enable signal OE causes the A switch 230 and the C switch as shown in FIG. 250 is off, B switch 240 and D switch 260
Are turned on, and the D / A converter 210 supplies fixed digital data signals D1 to D8 of 8 bits = all
When "1" is supplied, the grayscale voltage VN256 is output as the output A2n-1 of the operational amplifier 220 as shown in FIG. 2D, and the output terminal S2n- is output as shown in FIG. 1, a common voltage Vcom is output. Although not shown, the gray scale voltage VP256 is output as an output A2n-1 of the operational amplifier 220, and the common voltage Vcom is output to an output terminal S2n.

Next, the gate enable signal OE goes low.
When the level (the next scanning signal Gm + 1 is at the "H" level), the scanning signal Gm + 1 is at the "H" level (the period when the gate enable signal OE is at the "L" level). As shown in the figure, when the latch signal STB becomes “H” level, the rising edge of the latch signal STB causes
As shown in FIG. 2C, the C switch 250 is turned on, and the D switch 260 is turned off. The liquid crystal panel is serially supplied from the outside of the horizontal driver IC to display a desired gradation on the liquid crystal panel. Is supplied to the D / A converter 210 corresponding to each data line, and the D / A converter 210 corresponds to the 2n-1st data line. One of the 256 gradation voltages VN1 to VN256 is supplied to the operational amplifier 220.
Is selected and supplied. As shown in FIG. 2D, the operational amplifier 220 outputs an output A2n-1 and outputs the output A2n-1.
One of the gradation voltages VP1 to VP256 of 256 gradations is selected and supplied to 0, and is output from the operational amplifier 220 as an output A2n (not shown). When the latch signal STB becomes “L” level,
At the falling edge of the latch signal STB, the A switch 230 is turned on and the B switch 240 is turned off as shown in FIG. 2C, and the output terminal S2n- is turned on as shown in FIG. The selected gradation voltage VNx is output to 1 and the selected gradation voltage VPx is output to an output terminal S2n (not shown).

When the gate enable signal OE goes to the "H" level (the scanning signal Gm goes to the "L" level), the rising edge of the gate enable signal OE causes the A switch 230 and the C switch as shown in FIG. 250 is off, B switch 240 and D switch 260
Are turned on, and the D / A converter 210 supplies fixed digital data signals D1 to D8 of 8 bits = all
When "1" is supplied, the grayscale voltage VP256 is output as the output A2n-1 of the operational amplifier 220 as shown in FIG. 2D, and the output terminal S2n- is output as shown in FIG. 1, a common voltage Vcom is output. Although not shown, the grayscale voltage VN256 is output as an output A2n-1 of the operational amplifier 220, and the common voltage Vcom is output to an output terminal S2n.

As described above, the output terminals S1 to S
After the 384 is connected to the common voltage Vcom, the D / A converter 210 switches the next grayscale voltage VPx, V
During the period until Nx is selected, once the D / A converter 2
The input to the input 10 is converted from an 8-bit digital data signal, which is serially supplied from the outside of the horizontal driver IC and converted into parallel by an internal circuit (not shown) in order to display a desired gradation on the liquid crystal panel, from an 8-bit digital data signal. By switching to the fixed digital data signals D1 to D8 = all "1", during that period, the input to the operational amplifier 220 is changed from the grayscale voltage VPx to the grayscale voltage VN256 or from the grayscale voltage VNx to the grayscale voltage. Since VP256 is used, FIG.
As shown in FIG. 2, the current value flowing through the internal circuit of the operational amplifier 220 becomes minimum, and as shown in FIG. 2 (f), after the output terminals S1 to S384 are connected to the common voltage Vcom, the D / A
The converter 210 switches the next grayscale voltage V at the next switching polarity.
Operational amplifier 220 until Px and VNx are selected
Current consumption can be reduced. In the above embodiment,
The gray scale voltages VP256, VN2 of the input of the operational amplifier 220
The switching to 56 is performed by switching the input of the D / A converter to 8-bit fixed digital data signals D1 to D8 = all "1". Can be switched using voltage,
Therefore, a large layout area is not required. still,
The gray scale voltages VP256, VN2 of the input of the operational amplifier 220
It is also possible to switch to 56 immediately before the input of the operational amplifier 220. However, in this case, it is necessary to switch the output stage at a high voltage. In the above-described embodiment, the dot inversion drive has been described. However, the present invention can be applied to frame inversion drive and line inversion drive.

[0019]

According to the method and apparatus for driving a liquid crystal display device according to the present invention, after the output terminal is connected to the common voltage, the D / A converter selects the next gradation voltage with the next switching polarity. During this period, the current consumption of the operational amplifier can be reduced by driving the input of the operational amplifier to a gradation voltage at the next switching polarity that minimizes the current flowing through the operational amplifier. It can respond to the increase in size. Further, the gray scale voltage at which the current flowing through the operational amplifier is the minimum is the gray scale voltage having the maximum potential difference with respect to the common voltage. By outputting this gray scale voltage from the D / A converter, The switching can be performed by using a low voltage of the logic processing stage instead of a high voltage, so that a large layout area is not required and an element area is not increased.
Further, the n bits of the digital data signal input to the D / A converter to output the gray scale voltage are all the same level, for example, 8-bit fixed digital data signals D1 to D8 = all "1". By doing so, this signal can be easily generated by the internal circuit of the horizontal driver IC.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram of a horizontal driver IC according to one embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the horizontal driver IC of FIG.

FIG. 3 is a main part circuit diagram of a conventional horizontal driver IC.

FIG. 4 is a time chart for explaining the operation of the horizontal driver IC shown in FIG. 3;

FIG. 5 is a characteristic diagram showing a relationship between a current value in an output high impedance state of the operational amplifier used in FIGS. 1 and 3 and a supplied gradation voltage value.

FIG. 6 is a diagram showing a rising waveform of a driving voltage depending on the magnitude of a load on a liquid crystal panel.

[Description of Signs] 200 Horizontal driver IC 210 D / A converter 220 Operational amplifier 230 A switch 240 B switch 250 C switch 260 D switch

Claims (8)

[Claims] 1. A driving voltage for a data line of a liquid crystal panel to be driven based on an n-bit digital data signal.
A voltage that selects one of the 2n-th gradation voltages of a positive polarity and a negative polarity with respect to a common voltage by a D / A converter and outputs both a rising waveform and a falling waveform. A driving method for a liquid crystal display device in which a driving capability is increased by a follower-connected operational amplifier and output from an output terminal, and when the polarity of this output is switched every predetermined period, the output terminal is once connected to a common voltage. During a period from the time when the output terminal is connected to the common voltage to the time when the D / A converter selects the next gradation voltage with the next switching polarity, the current flowing through the input of the operational amplifier to the operational amplifier is minimized. A driving method for a liquid crystal display device, wherein a gradation voltage at a next switching polarity is used. 2. The liquid crystal display device according to claim 1, wherein the gradation voltage at which the current flowing through the operational amplifier is minimum is a gradation voltage having a maximum potential difference with respect to a common voltage. Method. 3. A driving method for a liquid crystal display device according to claim 2, wherein a gradation voltage at which a current flowing through said operational amplifier is minimized is output from said D / A converter. 4. A period from when the output terminal is connected to a common voltage to when the D / A converter selects the next gradation voltage, all n bits of the digital data signal input to the D / A converter are set. 4. The driving method for a liquid crystal display device according to claim 3, wherein the levels are the same. 5. A D / D converter for selecting one of two (n) th gradation voltages of a positive polarity and a negative polarity with respect to a common voltage based on an n-bit digital data signal.
An A-converter, a voltage follower-connected operational amplifier that outputs both a rising waveform and a falling waveform that outputs the selected gradation voltage with increased driving capability, and a liquid crystal panel to drive the output of the operational amplifier An output terminal for outputting to the data line of the liquid crystal display device, when the polarity of the output from the output terminal is switched every predetermined period, the output terminal is once connected to a common voltage, the driving device of the liquid crystal display device, During a period from the time when the output terminal is connected to the common voltage to the time when the D / A converter selects the next gradation voltage with the next switching polarity, the current flowing through the input of the operational amplifier to the operational amplifier is minimized. A driving device for a liquid crystal display device, wherein a gradation voltage at a next switching polarity is used. 6. A driving method for a liquid crystal display device according to claim 5, wherein the gray scale voltage at which the current flowing through said operational amplifier is minimum is a gray scale voltage having a maximum potential difference with respect to a common voltage. apparatus. 7. A driving device for a liquid crystal display device according to claim 6, wherein a gradation voltage at which a current flowing through said operational amplifier is minimized is output from said D / A converter. 8. A period from when the output terminal is connected to a common voltage to when the D / A converter selects the next gradation voltage, all n bits of the digital data signal input to the D / A converter are set. The driving device for a liquid crystal display device according to claim 7, wherein the driving levels are at the same level.