JP5098619B2 - Display driving device and display device including the same - Google Patents

Description

  The present invention relates to a display driving device for driving a display panel corresponding to, for example, an active matrix driving method, and a display device including such a display driving device.

  In recent years, information devices such as computers, mobile phones, and portable information terminals, and image processing related devices such as digital video cameras, digital still cameras, and scanners have been widely used. In such devices, a liquid crystal display (LCD) is frequently used as a display means.

  For example, in an active matrix liquid crystal display device, display pixels (liquid crystal pixels) each having a pixel transistor such as a thin film transistor are arranged in a matrix, and scanning lines that connect the display pixels in the row direction and signal lines that connect the display pixels in the column direction. For a liquid crystal display panel equipped with a display driver, each scanning line is sequentially selected by a gate driver, a predetermined signal voltage is applied to each signal line by a source driver, and image information is displayed on the display pixels in the selected state. By writing a signal voltage according to the above, the liquid crystal orientation state in each display pixel is controlled to display desired image information with a predetermined contrast.

As a liquid crystal driving method of such an active matrix liquid crystal display device, for example, as disclosed in Patent Document 1, a signal line is precharged to the highest voltage for writing to a display pixel for a certain time of one horizontal period, There is a driving method in which the target voltage is written in the remaining time.
JP-A-7-121139

  In recent years, liquid crystal display devices have become higher in definition, and accordingly, the time for one horizontal period has become shorter.

  In the driving method disclosed in Patent Document 1, the target voltage is always high because it is always precharged to the maximum voltage, but when the target voltage is low, the target voltage is determined from the precharged maximum voltage. There is a risk that the writing time for writing to the voltage will be insufficient.

  The present invention has been made in view of the above points, and provides a display driving device and a display device including the display driving device that can reduce the writing time and achieve high definition in each gradation of display data. With the goal.

To achieve the above object, one aspect of the display driving apparatus of the present invention, a pixel electrode, a counter electrode opposed to the pixel electrode, and liquid crystal filled between the counter electrode and the pixel electrode, In a display driving device for driving a display pixel having a predetermined number of selection periods based on display data, a gradation voltage generation for generating a plurality of gradation voltages according to the number of gradations of the display data And selecting and outputting one of the plurality of gradation voltages generated by the gradation voltage generation circuit in accordance with a gradation value of the display data within the selection period, and applying to the pixel electrode And a writing circuit that writes a display signal voltage due to a potential difference between the pixel electrode and the counter electrode to the display pixel, and the writing is performed in a correction period including an initial period of the selection period. Output from the circuit The gray voltages, the direction in which the absolute value increases of the display signal voltage, have a correction means for the correction gradation voltage shifted by a shift amount corresponding to the gradation value of the display data that, the gradation The voltage generation circuit divides a potential difference between the upper limit voltage and the lower limit voltage by a plurality of voltage dividing resistors connected in series between the upper limit voltage and the lower limit voltage, and generates the plurality of gradation voltages. A voltage dividing circuit; and means for switching, in the correction period, one of the upper limit voltage and the lower limit voltage to a shift voltage having a voltage value shifted in a direction in which the absolute value of the display signal voltage increases. It is characterized by having .

In order to achieve the above-described object, one aspect of the display device of the present invention is arranged in a matrix corresponding to each intersection of a plurality of scanning lines and a plurality of signal lines, and the scanning lines and the signal lines are electrically connected. A display panel having a plurality of display pixels each having a pixel electrode connected to the pixel electrode, a counter electrode facing the pixel electrode, and a liquid crystal filled between the pixel electrode and the counter electrode; A scanning line driving circuit that sequentially selects the plurality of scanning lines for each predetermined selection period, a gradation voltage generating circuit that generates a plurality of gradation voltages according to the number of gradations of display data, and the scanning line driving circuit The plurality of signal lines by selecting any of the plurality of gradation voltages generated by the gradation voltage generation circuit in accordance with the gradation value of the display data within the selection period of each scanning line by Output to A signal line driving circuit having a writing circuit for writing a display signal voltage due to a potential difference between the pixel electrode and the counter electrode to each display pixel of the selected scanning line, and the signal line driving circuit includes: In the correction period including the initial period of the selection period, the gradation voltage output from the writing circuit is set to the gradation value of the display data in the direction in which the absolute value of the display signal voltage increases. A correction unit configured to correct the gradation voltage shifted by a corresponding shift amount, and the gradation voltage generation circuit includes the upper limit voltage by a plurality of voltage dividing resistors connected in series between the upper limit voltage and the lower limit voltage. A voltage dividing circuit that divides a potential difference between the upper limit voltage and the lower limit voltage to generate the plurality of gradation voltages, and in the correction period, either the upper limit voltage or the lower limit voltage is set to the display signal. It has a means for switching the shift voltage having a voltage value shifted in the direction in which the absolute value of the voltage increases, and wherein the.

  According to the present invention, during the initial correction period of the selection period, the level of the display data is shifted to the side where the absolute value of the liquid crystal applied voltage becomes larger than the normal gradation voltage corresponding to the gradation value of the display data. The corrected gradation voltage shifted by the shift amount according to the tone value is applied to the display pixel, and the regular gradation voltage according to the gradation value of the display data is applied to the display pixel during the remaining period of the selection period. Therefore, the writing to the display pixel can be satisfactorily performed at each gradation of the display data. Therefore, it is possible to provide a display driving device that can shorten the writing time and achieve high definition and a display device including the display driving device.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic configuration diagram showing an overall configuration of a liquid crystal display device according to a first embodiment of the present invention. Here, a liquid crystal display device using an active matrix liquid crystal display panel will be described as the liquid crystal display device.

  The liquid crystal display device according to the present embodiment is roughly classified into a liquid crystal display panel 10, a source driver (display drive device: signal line drive circuit) 20, a gate driver (scanning line drive circuit) 30, and an LCD controller (control circuit). ) 40 and a system control circuit (control circuit) 50.

  Each configuration will be described below. The liquid crystal display panel 10 includes pixel electrodes arranged in a matrix, a common electrode (common electrode; common voltage Vcom) arranged opposite to the pixel electrodes, and liquid crystal filled between the pixel electrodes and the common electrode. A liquid crystal capacitor Clc, a TFT having a source connected to the pixel electrode (hereinafter referred to as “pixel transistor ITFT”), and a plurality of scans extending in the row direction of the matrix and connected to the gates of the plurality of pixel transistors ITFT. A source driver 20 and a gate driver 30 to be described later are configured to include a line Lg and a plurality (n) of signal lines Ld extending in the column direction of the matrix and connected to the drains of the plurality of pixel transistors ITFT. By applying a display signal voltage to the pixel electrode selected by the above, an electric field between the pixel electrode and the common electrode (liquid crystal applied voltage VLC ) Displays and outputs the predetermined image information by controlling the orientation of liquid crystal by. Here, Cs is a storage capacitor, and the liquid crystal capacitor Clc, the storage capacitor Cs, and the pixel transistor ITFT constitute a display pixel (liquid crystal pixel) 11.

  The source driver 20 generates a display signal voltage corresponding to display data (image signals R, G, B) supplied from the system control circuit 50 on the signal line Ld based on a horizontal control signal supplied from the LCD controller 40 described later. Is supplied to each pixel electrode.

  On the other hand, the gate driver 30 sequentially applies a scanning signal to each scanning line Lg every horizontal scanning period (1H) based on the vertical control signal supplied from the LCD controller 40, and selects the signal line Ld. The pixel electrodes (display pixels) arranged at the intersecting positions are subjected to line sequential driving in which the display signal voltage supplied (written) to the signal line Ld by the source driver 20 is applied. That is, by applying a scanning signal to one scanning line Lg of the liquid crystal display panel 10, each pixel transistor ITFT of the scanning line Lg is driven and controlled, and the display signal voltage applied to each signal line Ld by the source driver 20. Is applied to each pixel electrode via the pixel transistor ITFT.

  The LCD controller 40 generates a horizontal control signal and a vertical control signal based on the horizontal synchronization signal HD, the vertical synchronization signal VD, and the system clock SYSCK supplied from the system control circuit 50, and supplies them to the source driver 20 and the gate driver 30, respectively. Thus, a display signal voltage is applied to the pixel electrode at a predetermined timing, and control is performed to display desired image information on the liquid crystal display panel 10.

  The system control circuit 50 supplies the system clock SYSCK to the source driver 20, the LCD controller 40, and the like, and supplies the horizontal synchronization signal HD and the vertical synchronization signal VD synchronized with the system clock SYSCK to the LCD controller 40. In addition, display data composed of digital RGB signals is output to the source driver 20.

  That is, the LCD controller 40 and the system control circuit 50 perform various controls for displaying desired image information on the liquid crystal display panel 10 based on a video signal supplied from the outside via an interface (not shown). A signal is generated and output to the source driver 20 and the gate driver 30.

In general, in a liquid crystal display device, inversion driving is performed to invert the polarity of an electric field (liquid crystal applied voltage VLCD) between a pixel electrode and a common electrode filled with liquid crystal at a predetermined period. In the liquid crystal display panel 10, as described above, the pixel electrodes - but the arrangement of the liquid crystal is determined depending on the electric field between the common electrode, such pixel electrodes - the application of a direct current between the common electrode, but if image sticking occurs Or cause deterioration or destruction of the liquid crystal. For this reason, this is prevented by periodically inverting the polarity of the electric field between the pixel electrode and the common electrode.

  As the inversion driving method, line inversion driving and frame inversion driving are generally used. The line inversion driving is a method of inverting the polarity of the liquid crystal applied voltage VLCD for each scanning line and also for each frame period. The frame inversion drive is a method for inverting the polarity of each display pixel for each frame period. Here, “frame” refers to a unit of a period in which a display signal voltage is supplied to all the display pixels 11 of each liquid crystal display panel to display one image.

FIG. 2 is a block diagram showing the configuration of the source driver 20. Here, it is assumed that the display data in the present embodiment is an 8-bit digital RGB signal. As shown in the figure, the source driver 20 includes an n-stage shift register 21, a level shifter 22, an n × 8-bit data register 23, an n × 8-bit data latch 24, and n DACs 25 (25 _{1 to} 25 _n ). , A gamma circuit (gradation voltage generation circuit) 26, and n output AMPs 27 (27 _{1 to} 27 _n ). Here, the DAC 25 and the output AMP 27 constitute a writing circuit.

  The shift register 21 has n output terminals, starts with a shift register start signal supplied as a horizontal control signal from the LCD controller 40, and sequentially performs a shift operation with a clock supplied as a horizontal control signal. Output signals are sequentially output from each output terminal.

  The level shifter 22 shifts the signal level of the output signal from the shift register 21 from the logic voltage level to the power supply voltage level of the source driver. The data register 23 captures display data supplied from the system control circuit 50 at the timing of each output signal output from the shift register 21. The data latch 24 fetches and holds the display data fetched into the data register 23 all at once.

The DAC 25 (25 _{1 to} 25 _n ) is composed of digital RGB signals held in the data latch 24 based on a polarity control signal POL (described later) and a correction control signal CNT supplied as horizontal control signals from the LCD controller 40. This is a digital / analog (D / A) converter for converting display data into analog RGB signals (image signals R, G, B) and outputting them. Details will be described later.

The gamma circuit 26 generates a plurality of gradation voltages to be supplied to the DAC 25 and supplies it to the DAC 25. Conventionally, when the display data is 8 bits, the gradation corresponding to 8-bit data (0 to 255). Although the voltages V0 to V255 (V255 is higher than V0) are generated, the gamma circuit 26 in this embodiment further uses the minimum gradation voltage V0 in addition to the gradation voltages V0 to V255. The shift gradation voltages V0-α2, V0-α1, and the highest gradation voltage V255, shifted to a lower potential, are shifted to a higher potential. In the present embodiment, two-stage shift gradation voltages V255 + α1 and V255 + α2 are also generated. The DAC 25 selects the shift gradation voltage and gradation voltage of V0−α2 to V255 + α2 generated by the gamma circuit 26 according to the display data held in the data latch 24, thereby performing D / A conversion. I do. As described above, in the present embodiment, the voltage generated by the gamma circuit 26 is originally expanded from 256 levels of V0 to V255 when the display data is 8 bits, for example, 260 of V0−α2 to V255 + α2. By adopting the steps, the output voltage range of the DAC 25 can be made wider than in the conventional configuration. The output AMP27 (27 _{1 to} 27 _n ) amplifies the output of the corresponding DAC 25 (25 _{1 to} 25 _n ) and outputs the amplified signal to the n signal lines Ld as display signal voltages Y1 to Yn.

FIG. 3 is a diagram showing a configuration of the DAC 25 (25 _{1 to} 25 _n ), and FIG. 4 is a timing chart of the polarity control signal POL and the correction control signal CNT.

  Each DAC 25 is supplied with the gradation voltages V0−α2 to V255 + α2 generated by the gamma circuit 26, and decodes the corresponding 8-bit data among the display data held in the data latch 24, and displays the display data. A decoder (not shown) that outputs a V0 select signal to V255 select signal corresponding to the gradation values 0 to 255, and a V0 select signal to V255 select signal from the decoder, the polarity control signal POL, and the correction control signal CNT are provided. And a selection circuit that selects any one of the shift gradation voltage and the gradation voltages V0−α2 to V255 + α2 depending on the state of these signals, and outputs corresponding to the gradation voltage selected by the selection circuit It is configured to output to the AMP 27.

  That is, as shown in FIG. 3, the V0 select signal from the decoder is input to the AND gate 2501 and the AND gate 2502. The AND gate 2501 further receives the polarity control signal POL and the correction control signal CNT. The correction control signal CNT is input to the AND gate 2502 via an inverter 2503. The output of the AND gate 2501 is given as a switching control signal to a switch 2504 for switching and supplying the shift gradation voltage V0-α2 generated by the gamma circuit 26 to the output AMP27. The output of the AND gate 2502 is given as a switching control signal to a switch 2506 for switching and supplying the gradation voltage V0 generated by the gamma circuit 26 to the output AMP 27 via an OR gate 2505. It is configured.

Here, in the present liquid crystal display device, line inversion driving is performed in which the polarities of the display signal voltages Y1 to Yn and the common voltage VCOM are inverted for each scanning line. In the inversion driving in the present embodiment, the display data is inverted every time the inversion is performed, and the frame on the side where the absolute value of the liquid crystal applied voltage VLCD increases is the V0 side and the frame on the V255 side are alternately provided. . The polarity control signal POL indicates whether the voltage at which the absolute value of the liquid crystal applied voltage VLCD increases is the V0 side or the V255 side, and is high every horizontal scanning period (1H) as shown in FIG. The level / low level is inverted. The correction control signal CNT is a signal that is at a high level during the correction period (T _CNT ) set in the initial period of the 1H period. In the present embodiment, the voltage at which the absolute value of the liquid crystal application voltage VLCD increases when the polarity control signal POL is high is on the V0 side, and the absolute value of the liquid crystal application voltage VLCD when the polarity control signal POL is low. Assume that the voltage at which the voltage increases is on the V255 side.

  In the operation of this embodiment, when the polarity control signal POL is at a high level, that is, when the voltage at which the absolute value of the liquid crystal applied voltage VLCD increases is on the V0 side, the gradation value of the display data is the maximum gradation 255. When the V0 select signal is supplied to the DAC 25, while the correction control signal CNT is at a high level, the V0 select signal is output only from the AND gate 2501 side, the switch 2504 is turned on, and the switch 2506 is turned on. As a result, the output AMP 27 is lower than V0 which is a normal gradation voltage corresponding to the gradation value of the display data (larger by α2 than when the absolute value of the liquid crystal applied voltage VLCD is V0). The shift gradation voltage of V0-α2 is selected and output to the output AMP27 as the corrected gradation voltage. When the correction control signal CNT becomes low level, the V0 select signal is output only from the AND gate 2502 side, the switch 2504 is turned off, and the switch 2506 is turned on. As a result, the output AMP27 , V0 which is a normal gradation voltage is selected and output.

  As described above, the selection circuit including the AND gates 2501 and 2502 and the switches 2504 and 2506 allows the correction control signal CNT to be supplied from the normal gradation voltage V0 during the high level period, that is, the initial correction period for writing to the liquid crystal of the display pixel. Also, the shift gradation voltage V0-α2 whose absolute value of the liquid crystal application voltage VLCD is larger by α2 is output, and the normal gradation voltage V0 can be output with the correction control signal CNT at the low level in the subsequent writing period.

  Note that when the V0 select signal is supplied to the DAC 25 in accordance with the gradation value of the display data, when the polarity control signal POL is inverted to a low level, that is, the voltage at which the absolute value of the liquid crystal applied voltage VLCD increases is V255. The V0 select signal is not output from the AND gate 2501 regardless of the state of the correction control signal CNT, and the V0 select signal is output from the AND gate 2502 while the correction control signal CNT is at the low level. When the switch 2506 is turned on, the normal gradation voltage V0 is selected and output to the output AMP27. At this time, since the normal gradation voltage V0 is a low voltage, it is not necessary to perform precharging, and the period during which the output from the output AMP27 is shorter than 1H is only during the period when the correction control signal CNT is at a low level. Even if not, it is possible to write a normal display signal voltage corresponding to the gradation value of the display data.

  Next, when the gradation value of the display data is 254, which is one gradation lower than the highest gradation, and the V1 select signal is supplied to the DAC 25, the V1 select signal is input to the AND gate 2507 and the AND gate 2508. The AND gate 2507 further receives the polarity control signal POL and the correction control signal CNT, and the AND gate 2508 receives the correction control signal CNT via an inverter 2509. The output of the AND gate 2507 is given as a switching control signal to a switch 2510 for switching and supplying the shift gradation voltage V0-α1 generated by the gamma circuit 26 to the output AMP27. The output is configured to be supplied as a switching control signal to a switch 2512 for switching and supplying the gradation voltage V1 generated by the gamma circuit 26 to the output AMP 27 via an OR gate 2511.

Accordingly, when the polarity control signal POL is at a high level, that is, when the voltage at which the absolute value of the liquid crystal applied voltage VLCD increases is on the V0 side, the V1 select is performed while the correction control signal CNT is at a high level. The signal is output only from the AND gate 2507 side, the switch 2510 is turned on and the switch 2512 is turned off. As a result, the output AMP 27 is supplied with a normal gradation voltage corresponding to the gradation value of the display data. A shift gradation voltage of V0−α1 lower than a certain V1 (larger by α 1 +1 gradation difference (difference between 255 gradation and 254 gradation) than when the absolute value of the liquid crystal applied voltage VLCD is V1) is selected. Thus, the corrected gradation voltage is output to the output AMP27. When the correction control signal CNT becomes low level, the V1 select signal is output only from the AND gate 2508 side, the switch 2510 is turned off and the switch 2512 is turned on. As a result, the output AMP 27 V1, which is a normal gradation voltage, is selected and output.

  As described above, the selection circuit including the AND gates 2507 and 2508 and the switches 2510 and 2512 allows the absolute value of the liquid crystal application voltage VLCD to be higher than the normal gradation voltage V1 during the correction period when the correction control signal CNT is at the high level. The shift gradation voltage V0-α1 that is larger by the distribution is output, and the normal gradation voltage V1 can be output with the correction control signal CNT at the low level in the subsequent writing period.

  Note that when the V1 select signal is supplied to the DAC 25 according to the gradation value of the display data, when the polarity control signal POL is inverted to a low level, that is, the voltage at which the absolute value of the liquid crystal applied voltage VLCD increases is V255. The V1 select signal is not output from the AND gate 2507 regardless of the state of the correction control signal CNT, and the V1 select signal is AND gate while the correction control signal CNT is at the low level. Output from the 2508 side, the switch 2512 is turned on, and the normal gradation voltage V1 is selected and output to the output AMP27. At this time, since the normal gradation voltage V1 is a low voltage, it is not necessary to perform precharging, and the period during which the output from the output AMP27 is shorter than 1H is only during the period when the correction control signal CNT is at a low level. Even if not, it is possible to write a normal display signal voltage corresponding to the gradation value of the display data.

  In addition, when the gradation value of the display data is 253, which is two gradations lower than the highest gradation, and the V2 select signal is supplied to the DAC 25, the V2 select signal is output from the AND gate 2513 and the output through the OR gate. The regulated voltage V2 is inputted to an AND gate (V2 AND gate: not shown) given as a switching control signal to a switch (V2 switch: not shown) for switching and supplying to the output AMP27. The AND gate 2513 further receives the polarity control signal POL and the correction control signal CNT, and the V2 AND gate receives the correction control signal CNT via an inverter (not shown). The output of the AND gate 2513 is given as a switching control signal to the switch 2506 for switching and supplying the gradation voltage V0 generated by the gamma circuit 26 to the output AMP 27 via the OR gate 2505.

  Accordingly, when the polarity control signal POL is at a high level, that is, when the voltage at which the absolute value of the liquid crystal applied voltage VLCD increases is on the V0 side, the V2 select is performed while the correction control signal CNT is at a high level. The signal is output only from the AND gate 2513 side, the switch 2506 is turned on and the V2 switch is turned off. As a result, the output AMP 27 is supplied with a normal gradation voltage corresponding to the gradation value of the display data. A gradation voltage of V0 lower than a certain V2 (a difference of two gradations (the difference between 255 gradations and 253 gradations) lower than that when the absolute value of the liquid crystal applied voltage VLCD is V2) is selected and corrected gradation The voltage is output to the output AMP27. When the correction control signal CNT becomes low level, the V2 select signal is output only from the V2 AND gate side, the switch 2506 is turned off and the V2 switch is turned on. As a result, the output AMP27 V2 which is a normal display signal voltage is selected and output.

  As described above, the selection circuit composed of the AND gate 2513, the AND gate (not shown), the switch 2506, and the V2 switch allows the absolute value of the liquid crystal applied voltage VLCD to be higher than the normal gradation voltage V2 during the correction period in which the correction control signal CNT is at the high level. The shift gradation voltage V0 having a value larger by two gradations is output, and the normal gradation voltage V2 can be output with the correction control signal CNT at the low level in the subsequent writing period.

  Note that when the V2 select signal is supplied to the DAC 25 in accordance with the gradation value of the display data, when the polarity control signal POL is inverted to a low level, that is, the voltage at which the absolute value of the liquid crystal applied voltage VLCD increases is V255. The V2 select signal is not output from the AND gate 2513 regardless of the state of the correction control signal CNT, and the V2 select signal is displayed during the period when the correction control signal CNT is at the low level. Is output from the AND gate side, and the switch (not shown) is turned on, and the normal display signal voltage V2 is selected and output to the output AMP27. At this time, since the normal gradation voltage V2 is a relatively low voltage, it is not necessary to perform precharging, and the correction control signal CNT whose output period from the output AMP27 is shorter than 1H is low. Even if there is only a period, it is possible to write a normal display signal voltage corresponding to the gradation value of the display data.

  Thereafter, the intermediate V127 select signal from V3 is configured in the same manner as described above, and the correction control signal CNT is written in accordance with each select signal from the decoder, the polarity control signal POL and the correction control signal CNT during the high level period. Only during the initial correction period, the absolute value of the liquid crystal applied voltage VLCD is 2 gradation differences (2 gradations higher than its own gradation and itself) than the normal gradation voltage corresponding to the gradation value of the display data. The gradation voltage which is increased by the difference between the first and second gradations) is output to the output AMP 27 as the corrected gradation voltage.

  On the other hand, regarding the V128 select signal side intermediate from V255, the configuration on the V0 to V127 select signal side described above is symmetric with respect to the V127 select signal, and the polarity control signal POL is inverted by an inverter and input to the AND gate. It has the structure which was made.

  That is, the V255 select signal from the decoder is input to the AND gate 2515 and the AND gate 2516. Further, the correction control signal CNT and the polarity control signal POL are input to the AND gate 2515 via an inverter 2517. The correction control signal CNT is input to the AND gate 2516 via an inverter 2518. The output of the AND gate 2515 is given as a switching correction control signal to a switch 2519 for switching and supplying the shift gradation voltage V255 + α2 generated by the gamma circuit 26 to the output AMP27. The output of the AND gate 2516 is given as a switching control signal to a switch 2521 for switching and supplying the gradation voltage V255 generated by the gamma circuit 26 to the output AMP 27 via an OR gate 2520. It is configured.

  Therefore, when the polarity control signal POL is at a low level, that is, when the voltage at which the absolute value of the liquid crystal applied voltage VLCD increases is on the V255 side, the gradation value of the display data is the maximum gradation 255 and the V255 select signal is When supplied to the DAC 25, while the correction control signal CNT is at a high level, the V255 select signal is output only from the AND gate 2515 side, the switch 2519 is turned on, and the switch 2521 is turned off. As for the output AMP27, the shift gradation of V255 + α2 is higher than V255, which is a normal gradation voltage corresponding to the gradation value of the display data (the absolute value of the liquid crystal applied voltage VLCD is larger by α2 than when V255). A voltage is selected and output to the output AMP 27 as a corrected gradation voltage. When the correction control signal CNT becomes low level, the 2550 select signal is output only from the AND gate 2516 side, the switch 2519 is turned off, the switch 2521 is turned on, and as a result, the output AMP 27 V255, which is a normal gradation voltage, is selected and output.

  As described above, the selection circuit including the AND gates 2515 and 2516 and the switches 2519 and 2521 allows the absolute value of the liquid crystal applied voltage VLCD to be α2 more than the normal gradation voltage V255 during the correction period in which the correction control signal CNT is at the high level. A large shift gradation voltage V255 + α2 is output, and the normal gradation voltage V255 can be output with the correction control signal CNT at a low level in the subsequent writing period.

  Note that when the V255 select signal is supplied to the DAC 25 according to the gradation value of the display data, when the polarity control signal POL is inverted to a high level, that is, the voltage at which the absolute value of the liquid crystal applied voltage VLCD increases becomes V0. The V255 select signal is not output from the AND gate 2515 regardless of the state of the correction control signal CNT, and the V255 select signal is AND gate while the correction control signal CNT is at the low level. Output from the side 2516, the switch 2521 is turned on, and V255, which is a normal gradation voltage, is selected and output to the output AMP27. At this time, since the normal gradation voltage V255 is a low voltage, it is not necessary to perform precharging, and the period during which the output from the output AMP27 is shorter than 1H is only during the period when the correction control signal CNT is at a low level. Even if not, it is possible to write a normal display signal voltage corresponding to the gradation value of the display data.

  Next, when the gradation value of the display data is 254, which is one gradation lower than the highest gradation, and the V254 select signal is supplied to the DAC 25, the V254 select signal is input to the AND gate 2522 and the AND gate 2523. The AND gate 2522 further receives the correction control signal CNT and the polarity control signal POL via an inverter 2524. The AND gate 2523 receives the correction control signal CNT via an inverter 2525. Is entered. The output of the AND gate 2522 is given as a switching correction control signal to a switch 2526 for switching and supplying the shift gradation voltage V255 + α1 generated by the gamma circuit 26 to the output AMP 27, and the output of the AND gate 2523 Is configured to be supplied as a switching control signal to a switch 2528 for switching and supplying the gradation voltage V254 generated by the gamma circuit 26 to the output AMP 27 via an OR gate 2527.

  Therefore, when the polarity control signal POL is at a low level, that is, when the voltage at which the absolute value of the liquid crystal applied voltage VLCD increases is on the V255 side, the V254 select is performed while the correction control signal CNT is at a high level. The signal is output only from the AND gate 2522 side, the switch 2526 is turned on, the switch 2528 is turned off, and as a result, the output AMP 27 is supplied with a normal gradation voltage corresponding to the gradation value of the display data. A shift gradation voltage of V255 + α1 that is higher than a certain V254 (larger by α1 + 1 gradation difference (difference between 255 gradation and 254 gradation) than when the liquid crystal applied voltage VLCD is V254) is selected and corrected. It is output to the output AMP 27 as a regulated voltage. When the correction control signal CNT becomes low level, the V254 select signal is output only from the AND gate 2523 side, the switch 2526 is turned off, and the switch 2528 is turned on. As a result, the output AMP27 V254, which is a normal gradation voltage, is selected and output.

  As described above, the selection circuit including the AND gates 2522 and 2523 and the switches 2526 and 2528 allows the absolute value of the liquid crystal application voltage VLCD to be higher than the normal gradation voltage V254 during the correction period in which the correction control signal CNT is at the high level. The shift gradation voltage V255 + α1 that is larger by the distribution is output, and the normal gradation voltage V254 can be output with the correction control signal CNT at the low level in the subsequent writing period.

  Note that when the V254 select signal is supplied to the DAC 25 according to the gradation value of the display data, when the polarity control signal POL is inverted to a high level, that is, the voltage at which the liquid crystal application voltage VLCD becomes higher is on the V0 side. In this case, the V254 select signal is not output from the AND gate 2522 regardless of the state of the correction control signal CNT, and the V254 select signal is on the AND gate 2523 side while the correction control signal CNT is at the low level. , The switch 2528 is turned on, and a normal gradation voltage V254 is selected and output to the output AMP27. At this time, since V254, which is a normal gradation voltage, is a low voltage, it is not necessary to perform precharge, and the period during which the output from the output AMP27 is shorter than 1H is only during the period when the correction control signal CNT is at a low level. Even if not, it is possible to write a normal display signal voltage corresponding to the gradation value of the display data.

  Further, when the gradation value of the display data is 253, which is two gradations lower than the highest gradation, and the V253 select signal is supplied to the DAC 25, the V253 select signal is output from the AND gate 2529 and the output through the OR gate. The regulated voltage V253 is input to an AND gate (V253 AND gate: not shown) given as a switching control signal to a switch (V253 switch: not shown) for switching and supplying the output voltage AMP27. The AND gate 2529 further receives the correction control signal CNT and the polarity control signal POL via an inverter 2530. The V253 AND gate receives the correction control signal via an inverter (not shown). CNT is input. The output of the AND gate 2529 is given as a switching control signal to the switch 2521 for switching and supplying the gradation voltage V255 generated by the gamma circuit 26 to the output AMP 27 through the OR gate 2520.

  Therefore, when the polarity control signal POL is at a low level, that is, when the voltage at which the absolute value of the liquid crystal applied voltage VLCD increases is on the V255 side, the V253 select is performed while the correction control signal CNT is at a high level. The signal is output only from the AND gate 2529 side, the switch 2521 is turned on, and the switch (not shown) is turned off. As a result, the output AMP 27 has a normal gradation voltage corresponding to the gradation value of the display data. Is higher than V253 (the difference between the two gradations (the difference between 255 gradations and 253 gradations) is larger than when the absolute value of the liquid crystal applied voltage VLCD is V253). It is output to the output AMP 27 as a regulated voltage. When the correction control signal CNT becomes low level, the V253 select signal is output only from the V253 AND gate side, the switch 2521 is turned off, and the V253 switch is turned on. As a result, the output AMP27 V253, which is a normal gradation voltage, is selected and output.

As described above, the selection circuit composed of the AND gate 2529, the AND gate (not shown), and the switch 2521 and the V253 switch allows the liquid crystal applied voltage VLCD to be more absolute than the normal gradation voltage V253 during the high-level correction period. The gradation voltage V255 having a value that is two gradation differences larger is output, and the normal gradation voltage V253 can be output with the correction control signal CNT at the low level in the subsequent writing period .

  When the gradation value of the display data is 253 and the V253 select signal is supplied to the DAC 25, when the polarity control signal POL is inverted to a high level, that is, the voltage at which the liquid crystal application voltage VLCD becomes high is on the V0 side. In some cases, the V253 select signal is not output from the AND gate 2529 regardless of the state of the correction control signal CNT, and the V253 select signal is not shown while the correction control signal CNT is at a low level. Output from the AND gate side, the switch (not shown) is turned on, and V253, which is a normal gradation voltage, is selected and output to the output AMP27. At this time, since the normal gradation voltage V253 is a relatively low voltage, it is not necessary to perform precharge, and the correction control signal CNT whose period outputted from the output AMP27 is shorter than 1H is low. The target voltage can be written even if there is only a period.

  Hereinafter, the intermediate V128 select signal from V252 is configured in the same manner as described above, and the correction control signal CNT is in a high level period according to each select signal from the decoder, the polarity control signal POL, and the correction control signal CNT. Only during the initial correction period of writing, the absolute value of the liquid crystal applied voltage VLCD is higher than the normal gradation voltage corresponding to the gradation value of the display data, and the absolute value of the liquid crystal applied voltage VLCD is a level higher by 2 gradations than its own gradation. A gradation voltage that is larger by the difference between the tone and its own gradation is output to the output AMP 27 as a corrected gradation voltage.

  As described above, according to the first embodiment, the liquid crystal application voltage VLCD is higher than the normal gradation voltage corresponding to the gradation value of the display data during the initial correction period of writing when the correction control signal CNT is at the high level. Is output to the output AMP 27, and the normal gradation voltage is output during the period when the subsequent correction control signal CNT is at the low level, so that the liquid crystal of the display pixel is set to the normal display signal voltage. It can be reached quickly. Here, the absolute value (shift amount) of the difference between the correction gradation voltage output during the initial correction period of writing and the normal gradation voltage is α2 when the gradation value of the display data is the highest gradation, When the gradation value is one gradation lower than the highest gradation, α1 + 1 gradation difference (difference between the highest gradation and the highest gradation minus one gradation), and when the gradation value is two gradations lower than the highest gradation It is set to a difference between two gradations (difference between a gradation that is two gradations higher than its own gradation and its own gradation). That is, in the present embodiment, the correction gradation voltage is not always precharged to the maximum voltage as in the prior art so that the writing to the display pixel can be satisfactorily performed at each gradation of the display data. The value of is different depending on the gradation value of the display data, and the magnitude of the shift amount is appropriately changed according to the gradation value of the display data. Here, when the absolute value of the liquid crystal applied voltage VLCD is the highest at the highest gradation, the load on the output AMP 27 is the highest at the highest gradation, so the shift amount is maximized and lower than the highest gradation. Therefore, it is preferable to set the difference between the correction voltage and the target voltage to be smaller as the gradation becomes lower than the maximum gradation, so that α2> α1 + 1 gradation difference> 2 gradation difference. Further, when the gradation value is two gradations or more lower than the maximum gradation, the difference of the correction voltage with respect to the target voltage is set to the two gradation difference, but the present invention is not limited to this.

  When the correction gradation voltage is output to the output AMP 27 during the initial correction period of writing, the output AMP 27 is driven during this period so that writing to the display pixel via the signal line Ld can be performed in a short time. It is preferable to increase the capacity. Therefore, the bias current of the output AMP 27 is controlled according to the correction control signal CNT, and the bias control signal CNT is supplied to the output AMP 27 during the period when the correction control signal CNT is at the high level. It may be controlled to be several times that of

  Further, the period during which the correction control signal CNT is set to the high level and the correction voltage is output may be less than half of 1H, and preferably about 1/3.

According to the first embodiment as described above, and set wider than the voltage range corresponding to the number of bits of the display data voltage range of a plurality of gradation voltages supplied to the DAC 25, in the writing period of the 1H, write initial During this correction period, the corrected gradation voltage shifted to the side where the absolute value of the liquid crystal applied voltage becomes larger than the normal gradation voltage corresponding to the gradation value of the display data is output, and then the normal gradation voltage is changed. By providing a writing circuit for outputting, the writing time of the liquid crystal can be shortened in each gradation. As a result, for example, even if the period of 1H is shortened due to high definition, it is possible to satisfactorily write the normal display signal voltage to the liquid crystal of the display pixel by suppressing the shortage of writing due to insufficient writing time. It becomes possible.

[Second Embodiment]
Next, a liquid crystal display device according to a second embodiment of the present invention will be described.

  Since the overall configuration is the same as that of the liquid crystal display device according to the first embodiment described above, the description thereof is omitted.

As shown in FIG. 2 in the first embodiment, the source driver 20 includes a shift register 21, a level shifter 22, a data register 23, a data latch 24, n DACs 25 (25 _{1 to} 25 _n ), and a gamma circuit. 26 and n output AMPs 27 (27 _{1 to} 27 _n ), in the source driver 20 in the second embodiment, the gamma circuit 26 is V0-α2 as in the first embodiment. It is assumed that 256 levels of gradation voltages of V0 to V255 are generated in the same manner as in the past, instead of 260 levels of ~ V255 + α2. Further, the DAC 25 (25 _{1 to} 25 _n ) has a configuration that includes only a switch that selects and outputs a gradation voltage according to each select signal.

  However, in the present embodiment, the 256-level gradation voltage generated by the gamma circuit 26 is not always constant, and the absolute value of the liquid crystal application voltage VLCD of the gradation voltage is not changed during the initial correction period of writing. By switching the voltage on the increasing side to a shift voltage shifted in the direction in which the absolute value of the liquid crystal application voltage VLCD increases, the value of each gradation voltage is applied to the liquid crystal from the normal gradation voltage corresponding to the gradation value of the display data. The corrected gradation voltage is generated so that the absolute value of the voltage VLCD is shifted to the larger side.

FIG. 5 is a diagram showing a configuration of the gamma circuit 26 in the second embodiment, and FIG. 6 is a timing chart of the polarity control signal POL, the correction control signal CNT, and the delay control signal CNTD. Here, the correction control signal CNT and the delay control signal CNTD are supplied from the LCD controller 40 as horizontal control signals. As shown in FIG. 6, the correction control signal CNT is a signal that is at a high level for a predetermined period (T _CNT ) in the initial correction period of the 1H period, as in the first embodiment, and the delay control signal CNTD is After the correction control signal CNT becomes low level, the correction control signal CNT becomes high level, for example, until a period (T _CNTD ) having a delay period Delay of several _microseconds , Is a signal.

As shown in FIG. 5, the gamma circuit 26 normally has a voltage divider (divided voltage) composed of a plurality of resistors (voltage dividing resistors) R1, R2,..., R254 corresponding to the number of gradations (256 gradations) of display data. Circuit) 2601 and amplifiers 2602 and 2603 for applying voltages (upper limit voltage) VH and voltage (lower limit voltage) VL from a voltage generation circuit (not shown) to both ends of the voltage divider 2601, A voltage obtained by dividing the voltage difference between the upper limit voltage VH and the lower limit voltage VL by the resistors R1, R2,..., R254 is applied to both ends of the voltage divider 2601 by applying the voltage from the amplifiers 2602 and 2603 to the gradation voltage V0, V1,..., V255 are applied to the DAC 25 (25 _{1 to} 25 _n ).

In this embodiment, a switch that switches the series connection of resistors (auxiliary resistors) Rs, Rt, Ru, and Rv in parallel with the resistors R1 to R254 of the voltage divider 2601 according to the delay control signal CNTD. The connection is made via 2604 and 2605. Further, a connection point between the resistors Rs and Rt is connected to a connection point between the resistors R62 and R63 of the voltage divider 2601 through a switch 2606 that is switched according to the delay control signal CNTD, and the resistors Rt and Ru Is connected to a connection point between the resistors R126 and R127 of the voltage divider 2601 through a switch 2607 that is switched according to the delay control signal CNTD, and a connection point between the resistor Ru and the resistor Rv is connected to the delay control signal. through the switch 2608 is switched in accordance with the CNTD is to be connected to a connection point between the resistor R190 and R 1 91 of the divider 2601.

  The resistor Rs is (R0 + R1 + ... + R62) / 10, the resistor Rt is (R63 + R64 + ... + R126) / 10, the resistor Ru is (R127 + R128 + ... + R190) / 10, and the resistor Rv is (R191 + R192 + ... + R254) / 10. Resistance value.

  The input terminal of the amplifier 2602 is connected to a switch 2609 that switches between the S1 terminal and the S2 terminal according to the polarity signal POL. Here, the S1 terminal of the switch 2609 is an S3 terminal to which a low level voltage (lower limit voltage) VL is applied from a voltage generation circuit (not shown) according to the correction control signal CNT, and a voltage obtained by shifting VL to the negative voltage side. (Shift voltage) Connected to a switch 2610 that switches between the S4 terminal to which VL-α3 is applied. A low level voltage VL is applied to the S2 terminal of the switch 2609 from a voltage generation circuit (not shown).

  Similarly, the input terminal of the amplifier 2603 is connected to a switch 2612 that switches between the S5 terminal and the S6 terminal according to the polarity signal POL. Here, the S5 terminal of the switch 2612 is an S7 terminal to which a high level voltage (upper limit voltage) VH is applied from a voltage generation circuit (not shown) according to the correction control signal CNT, and a voltage obtained by shifting VH to the positive voltage side. (Shift voltage) VH + α3 is connected to a switch 2613 for switching to the S8 terminal to which VH + α3 is applied. A high bell voltage VH is applied to the S6 terminal of the switch 2612 from a voltage generation circuit (not shown). Here, the switches 2609, 2610, 2612, and 2613 constitute a switching circuit in the present invention.

  Therefore, in the gamma circuit 26 having such a configuration, when the polarity signal POL is high, that is, when the voltage at which the liquid crystal applied voltage VLCD increases is on the V0 side, the switch 2609 is switched to the S1 terminal side, The switch 2612 is switched to the S6 terminal side. In this state, during the correction period in which the correction control signal CNT is at a high level, the switch 2610 is switched to the S4 terminal side, so that the voltage VL-α3 is input to the amplifier 2602 and the voltage VH is input to the amplifier 2603. Is done. As a result, during the correction period, the lower limit voltage applied to the voltage divider 2601 is shifted by the voltage α3 to the negative voltage side where the absolute value of the liquid crystal application voltage VLCD increases, and each gradation voltage is the absolute value of the liquid crystal application voltage VLCD. The corrected gradation voltage is shifted to a larger value. When the correction control signal CNT becomes low level, the switch 2610 is switched to the S3 terminal side, so that the voltage VL is input to the amplifier 2602 and the voltage VH is input to the amplifier 2603, and each gradation voltage is It becomes a normal gradation voltage.

  Conversely, when the polarity signal POL is low, that is, when the voltage at which the liquid crystal applied voltage VLCD increases is on the V255 side, the switch 2609 is switched to the S2 terminal side, and the switch 2612 is switched to the S5 terminal side. In this state, while the correction control signal CNT is at the high level, the switch 2613 is switched to the S8 terminal side, so that the voltage VL is input to the amplifier 2602 and the voltage VH + α3 is input to the amplifier 2603. The As a result, during the correction period, the upper limit voltage applied to the voltage divider 2601 is shifted to the positive voltage side by the voltage α3, and each gradation voltage is shifted to the side where the absolute value of the liquid crystal application voltage VLCD is increased. Voltage. When the correction control signal CNT becomes a low level, the switch 2613 is switched to the S7 terminal side, so that the voltage VL is input to the amplifier 2602 and the voltage VH is input to the amplifier 2603, and each gradation voltage is It becomes a normal gradation voltage.

  In this way, in the gamma circuit 26, during the correction period in which the correction control signal CNT is at a high level, the voltage on the side where the absolute value of the liquid crystal application voltage VLCD increases becomes the side where the absolute value of the liquid crystal application voltage VLCD increases. A corrected gradation voltage is generated by shifting the voltage by the voltage α3. At this time, since the voltage on the side where the absolute value of the liquid crystal application voltage VLCD decreases does not shift, each gradation voltage in the correction period shifts to the side where the absolute value of the liquid crystal application voltage VLCD increases, and the shift amount for each gradation Varies depending on the gradation, and the shift amount of the gradation voltage on the side where the absolute value of the liquid crystal applied voltage VLCD increases becomes large. Here, when the absolute value of the liquid crystal application voltage VLCD is the largest at the highest gradation, the gradation voltage is the highest at the highest gradation when the absolute value of the liquid crystal application voltage VLCD is the largest and the load on the output AMP 27 is the largest. The amount of shift can be maximized, lower than the maximum gradation, and the amount of gradation voltage can be gradually reduced as the load is gradually reduced. Writing can be performed satisfactorily.

  In the voltage divider 2601 of the gamma circuit 26, the gradation voltages V0 to V255 are generated by dividing the voltage between V0 and V255 by a plurality of resistors R0 to R254 connected in series, but only the resistors R0 to R254 are used. If the resistance value of each resistor is set to a relatively large value in order to suppress the increase in power consumption by making the current flowing through the resistors R0 to R254 relatively small, Due to the time constant due to the parasitic capacitance up to the input of the DAC 25, a delay of a certain degree is caused until the value of the gradation voltages V0 to V255 is stabilized after the correction control signal CNT is switched to the high level or the low level.

Therefore, in the present embodiment, a series connection of the resistors Rs, Rt, Ru, and Rv is further provided in parallel with the resistors R0 to R254 of the voltage divider 2601, and this is performed during a period when the delay control signal CNTD is at a high level. A configuration for connection is provided. Through the switches 2604 to 2608, the resistor Rs is connected in parallel to the resistors R0 to R62, the resistor Rt is connected in parallel to the resistors R63 to R126, and the resistor Ru is parallel to the resistors R127 to R190. The resistor Rv is connected in parallel to the resistors R191 to R254. Here, for example, the resistor Rs has a resistance value of (R0 + R1 +... + R62) / 10, the resistor Rt has a resistance value of (R63 + R64 +... + R126) / 10, and the resistor Ru is (R127 + R128 +... + R190). The resistance Rv has a resistance value of (R191 + R192 +... + R254) / 10. Thus, when the resistors Rs, Rt, Ru, and Rv are connected in parallel to the resistors R0 to R254 via the switches 2604 to 2608 during a period when the delay control signal CNTD is at a high level, the gradation voltages V63, With respect to V127, V191, and V255, the time constant can be reduced to approximately 1/10 when the resistors Rs, Rt, Ru, and Rv are not connected, so that the values of the gradation voltages V0 to V255 are stabilized. The delay time can be reduced. However, when the delay control signal CNTD is at a high level and the resistors Rs, Rt, Ru, Rv are connected, the resistance between V0 and V255 is approximately 1/10 when the resistors Rs, Rt, Ru, Rv are not connected. Therefore, the current flowing between V0 and V255 increases. In order to suppress an increase in power consumption due to this, as shown in FIG. 6, the delay control signal CNTD corresponds to the stable time of the gradation voltages V0 to V255 after the correction control signal CNT becomes low level. the delay period delay to low-level wait.

  Further, for example, the bias current of the amplifiers 2602 and 2063 is increased during a period when the delay control signal CNTD is at a high level, and writing to the display pixel via the signal line Ld when the grayscale voltage is shifted is performed in a short time. You may be able to do it.

As described above, according to the second embodiment of the present invention, in the gamma circuit 26, the gradation voltage is shifted to the side where the absolute value of the liquid crystal applied voltage is increased during the initial correction period of writing, and then by the adjustment voltage to a normal value, the output AMP27, in the initial correction period of writing, and outputs a voltage of the display signal voltage normalized by the absolute value shift on the side increases the voltage applied to the liquid crystal, then Since a normal display signal voltage can be output, the writing time can be shortened as in the first embodiment.

  Further, the circuit scale is made smaller than that in the first embodiment by shifting the voltage on the side where the absolute value of the liquid crystal applied voltage VLCD of the gradation voltage generated by the gamma circuit 26 is increased. Can do.

  Furthermore, the resistors Rs, Rt, Ru, and Rv are connected in parallel to the resistors R0 to R254 of the voltage divider 2601 to reduce the time constant, so that the gradation voltage is changed when the gradation voltage is switched. It is possible to shorten the delay time required for the to stabilize.

In the second embodiment, when Rx = R0 + R1 +... + R253 + R254, Rs + Rt + Ru + Rv = Rx / 10 is used.

  Further, the resistors R0 to R254 are divided into four blocks, and the resistors Rs, Rt, Ru, and Rv are connected to each block by a switch in parallel. However, the present invention is not limited to this, and the number of blocks is from 2 blocks to 254. It can be divided into any number of blocks as long as it is a block.

  The present invention has been described above based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications and applications are possible within the scope of the gist of the present invention. .

  For example, in the embodiment, the case where the display data is 8 bits and 256 gradations has been described as an example. However, the present invention can be similarly applied to other bits and gradations.

FIG. 1 is a schematic configuration diagram showing an overall configuration of a liquid crystal display device according to a first embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the source driver in FIG. FIG. 3 is a diagram showing the configuration of each DAC in FIG. FIG. 4 is a timing chart of the polarity signal POL and the correction control signal CNT. FIG. 5 is a diagram showing a configuration of a gamma circuit in the liquid crystal display device according to the second embodiment of the present invention. FIG. 6 is a diagram illustrating a timing chart of the polarity signal POL, the correction control signal CNT, and the delay control signal CNTD in the second embodiment.

Explanation of symbols

10 ... liquid crystal display panel 11 ... liquid crystal pixels 20 ... source driver 21 ... shift register 22 ... level shifter 23 ... data register 24 ... data latch _{25 (25 1 ~25 n) ...} DAC
26: Gamma circuit 27 (27 _{1 to} 27 _n ): Output AMP
DESCRIPTION OF SYMBOLS 30 ... Gate driver 40 ... LCD controller 50 ... System control circuit 2501, 502, 2507, 2508, 2513, 2515, 2516, 2522, 2523, 2529 ... AND gate 2503, 2509, 2517, 2518, 2524, 2525, 2530 ... Inverter 2504, 2506, 2510, 2512, 2514, 2519, 2521, 2526, 2528, 2604 to 2614 ... switch 2505, 2511, 2520, 2527 ... OR gate 2601 ... voltage divider 2602, 2603 ... amplifier

Claims (13)

A pixel electrode, a counter electrode opposed to the pixel electrodes, the pixel and liquid crystal filled between said counter electrode electrodes, a display pixel comprising a, predetermined selection period based on the display data In the display driving device for driving the display,
A gradation voltage generating circuit for generating a plurality of gradation voltages according to the number of gradations of the display data;
During the selection period, select and output one of the plurality of gradation voltages generated by the gradation voltage generation circuit according to the gradation value of the display data, and apply to the pixel electrode, A writing circuit for writing a display signal voltage due to a potential difference between the pixel electrode and the counter electrode to the display pixel;
Comprising
In the correction period including the initial period of the selection period, the gradation voltage output from the writing circuit is set in accordance with the gradation value of the display data in a direction in which the absolute value of the display signal voltage increases. a correction means for the correction gradation voltage shifted by shift amount possess,
The gradation voltage generating circuit divides a potential difference between the upper limit voltage and the lower limit voltage by a plurality of voltage dividing resistors connected in series between the upper limit voltage and the lower limit voltage, and the plurality of gradation voltages. In the correction period, the voltage of either the upper limit voltage or the lower limit voltage is switched to a shift voltage having a voltage value shifted in a direction in which the absolute value of the display signal voltage increases. Means.
A display driving device characterized by that. The display signal voltage is controlled so that the polarity is inverted every selection period,
The gradation voltage generation circuit is supplied with a correction control signal indicating whether or not the correction period of the selection period is in progress and a polarity control signal indicating the polarity of the display signal voltage, and the correction control signal and the The display drive device according to claim 1, further comprising: a switching circuit that switches whether one of the upper limit voltage and the lower limit voltage is set to the shift voltage according to a polarity control signal . The grayscale voltage generation circuit is further provided in parallel with the plurality of voltage dividing resistors in the voltage dividing circuit, and has a resistance value smaller than the resistance values of the voltage dividing resistors. A resistor, and a delay control signal, and in response to the delay control signal, means for connecting the plurality of auxiliary resistors in parallel with the plurality of voltage dividing resistors in the correction period and a period immediately after the end of the correction period; the display driving apparatus according to claim 2, characterized in that it comprises a. The correction gradation voltage has a different value for each gradation,
2. The display driving device according to claim 1 , wherein the shift amount is set to a maximum value when a gradation value of the display data is a value at which an absolute value of the display signal voltage is maximum. . The gradation voltage generation circuit has a voltage higher than the maximum voltage of the gradation voltage and a voltage lower than the minimum voltage of the gradation voltage in addition to the gradation voltage corresponding to the gradation of the display data. Means for generating a shifted gradation voltage;
In the correction period, the writing circuit includes the gradation voltage or the display corresponding to the gradation on the side where the absolute value of the display signal voltage is larger than the gradation value of the display data from the plurality of gradation voltages. 5. The display driving device according to claim 1, further comprising means for selecting the shift gradation voltage on the side where the absolute value of the signal voltage is increased and outputting the selected gradation voltage as the corrected gradation voltage . The display signal voltage is controlled so that the polarity is inverted every selection period,
The writing circuit is supplied with a correction control signal indicating whether or not the correction period is in the selection period and a polarity control signal indicating the polarity of the display signal voltage, and the correction control signal and the polarity control signal The display driving apparatus according to claim 5, further comprising a selection circuit that switches whether to output a voltage to be output as the corrected gradation voltage . The selection circuit selects the correction gradation voltage in the correction period when the gradation value of the display data is a gradation on the side where the absolute value of the display signal voltage is larger than at least halftone. The display driving device according to claim 6, wherein the display driving device outputs . A pixel electrode arranged in a matrix corresponding to each intersection of a plurality of scanning lines and a plurality of signal lines and electrically connected to the scanning lines and the signal lines; a counter electrode facing the pixel electrodes; A liquid crystal filled between the pixel electrode and the counter electrode, and a display panel having a plurality of display pixels,
A scanning line driving circuit for sequentially selecting the plurality of scanning lines for each predetermined selection period;
A gradation voltage generation circuit that generates a plurality of gradation voltages according to the number of gradations of display data, and a gradation value of the display data within the selection period of each scanning line by the scanning line driving circuit And selecting one of the plurality of gradation voltages generated by the gradation voltage generation circuit and outputting the selected gradation voltage to the plurality of signal lines, and the pixel electrode on each display pixel of the selected scanning line. A write circuit for writing a display signal voltage due to a potential difference between the counter electrode and a signal line driving circuit,
With
The signal line driver circuit displays the gradation voltage output from the writing circuit in a correction period including an initial period of the selection period in a direction in which the absolute value of the display signal voltage increases. A correction means for correcting the gradation voltage shifted by the shift amount according to the gradation value of the data;
The gradation voltage generation circuit divides a potential difference between the upper limit voltage and the lower limit voltage by a plurality of voltage dividing resistors connected in series between the upper limit voltage and the lower limit voltage, and generates the plurality of gradation voltages. A voltage dividing circuit that generates and means for switching, in the correction period, one of the upper limit voltage and the lower limit voltage to a shift voltage having a voltage value shifted in a direction in which the absolute value of the display signal voltage increases. And having
A display device characterized by that . The display device further includes a control circuit that outputs a correction control signal indicating whether or not the correction period of the selection period is in effect and a polarity control signal indicating the polarity of the display signal voltage,
The display signal voltage is controlled so that the polarity is inverted every selection period,
The gradation voltage generation circuit is supplied with the correction control signal and the polarity control signal from the control circuit, and outputs either the upper limit voltage or the lower limit voltage according to the correction control signal and the polarity control signal. The display device according to claim 8, further comprising a switching circuit that switches whether to use the shift voltage . The grayscale voltage generation circuit is further provided in parallel with the plurality of voltage dividing resistors in the voltage dividing circuit, and has a resistance value smaller than the resistance values of the voltage dividing resistors. A resistor, and a delay control signal, and in response to the delay control signal, means for connecting the plurality of auxiliary resistors in parallel with the plurality of voltage dividing resistors in the correction period and a period immediately after the end of the correction period ; 10. The display device according to claim 9, further comprising: The correction gradation voltage has a different value for each gradation,
9. The display device according to claim 8 , wherein the shift amount is set to a maximum value when a gradation value of the display data is a value at which an absolute value of the display signal voltage is maximum . The gradation voltage generation circuit has a voltage higher than the maximum voltage of the gradation voltage and a voltage lower than the minimum voltage of the gradation voltage in addition to the gradation voltage corresponding to the gradation of the display data. Means for generating a shifted gradation voltage;
In the correction period, the writing circuit includes the gradation voltage or the display corresponding to the gradation on the side where the absolute value of the display signal voltage is larger than the gradation value of the display data from the plurality of gradation voltages. 12. The display device according to claim 8, further comprising means for selecting the shift gradation voltage on the side where the absolute value of the signal voltage is increased and outputting the selected gradation voltage as the corrected gradation voltage . The display device further includes a control circuit that outputs a correction control signal indicating whether or not the correction period of the selection period is in effect and a polarity control signal indicating the polarity of the display signal voltage,
The display signal voltage is controlled so that the polarity is inverted every selection period,
The writing circuit is supplied with the correction control signal and the polarity control signal from the control circuit, and determines whether or not to output a voltage to be the correction gradation voltage according to the correction control signal and the polarity control signal. The display device according to claim 12 , further comprising a selection circuit that switches between the two .

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