JP2000250491A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of suppressing the degradation of image quality due to fluctuations of effective voltage values which are to be generated because quantities of currents flowing into counter electrodes and compensating electrodes are changed in accordance with the data quantity of display data. SOLUTION: A circuit detecting the data quantity of display data which are to be inputted to an interface circuit 102 and a circuit generating a correcting period control signal controlling a time when a correcting voltage value is to be added to/subtracted from a counter electrode voltage value which is to be applied to counter electrodes in accordance with the data quantity of the detected display data are provided in the circuit 102 and a display having high image quality is realized by correcting the effective voltage values applied to liquid crystal even when quantities of currents flowing into counter electrodes and compensating electrodes are changed by providing a circuit performing a control adding the correcting voltage value to the counter electrode voltage/ substracting it from the counter electrode voltage for a certain period in accordance with the correcting period control signal 111 generated in the above described manner in this device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly to a driving method and a driving circuit for realizing high-quality display using a low-voltage driving circuit.

[0002]

2. Description of the Related Art A conventional liquid crystal display will be described with reference to FIGS.

FIG. 2 is a block diagram of a conventional liquid crystal display. FIG. 3 shows a driving waveform of a conventional liquid crystal display.

In FIG. 2, reference numeral 201 denotes an interface signal including display data and a synchronization signal transferred from a system (not shown). An interface circuit 202 generates display data and control signals for driving a conventional liquid crystal display. Reference numeral 203 denotes a signal drive circuit, which generates a gray scale voltage corresponding to display data.
A scan driving circuit 204 sequentially selects scan lines. Reference numeral 205 denotes a liquid crystal panel on which a display corresponding to display data input here is made. 206 is a power supply circuit.

[0005] Of the signals generated by the interface circuit 202, reference numeral 207 denotes a control signal for the signal drive circuit 203, which includes display data and a synchronization signal. Reference numeral 208 denotes a control signal for the scan driving circuit 204, which transfers a timing signal for sequentially operating scan lines. 209 is an AC signal 'M' to be transferred to the power supply circuit 206.

[0006] Of the signals generated by the power supply circuit 206, 2
Reference numeral 10 denotes a gray scale voltage signal to be transferred to the signal drive circuit 203, and transfers a reference voltage of a gray scale voltage corresponding to display data to be transferred to the liquid crystal of the liquid crystal panel 205. 211
Is a scan voltage signal to be transferred to the scan drive circuit 204, 212 is a counter electrode connected to the liquid crystal of the liquid crystal panel 205, and 213 is a compensation electrode connected to the compensation capacitance of the liquid crystal panel 205.

Reference numeral 214 denotes a signal line group for transferring a gray scale voltage corresponding to display data generated by the signal driving circuit 203. Reference numeral 215 denotes a state in which a scanning line generated by the scanning driving circuit 204 is selected or not selected. This is a scanning line group for transferring a scanning voltage.

Reference numeral 216 denotes a pixel portion constituting the liquid crystal panel 205, which is formed at the intersection of the signal line group 214 and the scanning line group 215, so that the liquid crystal panel 205 has a matrix structure. Further, the pixel portion 216 has the number of resolutions in the horizontal direction and the vertical direction.

In general, in the case of a liquid crystal display of a color display, one pixel is composed of three primary colors of red, green and blue. When each color pixel portion is arranged in the horizontal direction, the number of pixels in the horizontal direction is determined by the resolution. This is three times the number. The pixel units 216 arranged in the horizontal direction share one scanning line of the scanning line group 215, and the pixel units 216 arranged in the vertical direction share one signal line of the signal line group 214. Is common.

The pixel portion 216 includes a thin film transistor (Thin Film) 217 as a switching element.
Transistor, hereafter called TFT. ), 218 is a liquid crystal, and 219 is a compensation capacitance.

In FIG. 3, G1 is a driving waveform of the scanning line for driving the first line in the scanning line group 215 shown in FIG. 2, Vgon indicates a selection voltage level, and Vgo
ff indicates a non-selection voltage level. Similarly, G2 is a driving waveform of a scanning line for driving the second line. V
com is a driving waveform of the counter electrode 212,
mP is a positive voltage level, and VcomN is a negative voltage level. Vd indicates a gray scale voltage of the signal line group 214. When the voltage is on the negative side with respect to the common electrode voltage Vcom, a negative voltage is applied to the pixel portion 216 and the pixel portion 216 has a positive polarity. In this case, a positive voltage is applied to the pixel portion 216.

The liquid crystal display uses the common electrode voltage V
Com and the gradation voltage Vd operate so that the luminance changes with the potential difference.

In the conventional liquid crystal display shown in FIG. 2, the compensating electrode 213 causes the voltage applied to the liquid crystal 218 to leak current during the holding period, and
8 is generally provided to prevent the holding voltage of the counter electrode 8 from becoming unstable, and the driving voltage of the compensation electrode 213 is similar to the driving voltage waveform of the common electrode voltage Vcom. Will be omitted.

Referring again to FIG. 2, the operation of the conventional liquid crystal display will be described in detail.

Display data and a synchronization signal transferred by the interface signal 201 are input to the interface circuit 202, and the interface circuit 202 sends a control signal 207 to a signal drive circuit 203 and a scan drive circuit 204.
, And a liquid crystal alternating signal 209 to the power supply circuit 206.

In the signal drive circuit 203, the control signal 207
The display data for one horizontal line is sequentially fetched using the display data and the synchronization signal transferred in step 1. When the display data for one horizontal line has been fetched, the gradation corresponding to the fetched display data for one horizontal line is obtained. Apply voltage to signal line group 2
14 are output simultaneously. The signal drive circuit 203 keeps outputting the grayscale voltage for one horizontal line during one horizontal period.
Further, at this time, the signal drive circuit 203 carries out the operation of sequentially taking in the display data of the next horizontal line in parallel. Therefore, the display data output by the interface circuit 202 is output as a gray scale voltage to the liquid crystal panel 205 during the next horizontal period.

This operation is repeatedly performed by the signal drive circuit 203, and a gray scale voltage corresponding to display data for one frame, that is, one screen is output to the liquid crystal panel 205.

The gray scale voltage output from the signal drive circuit 203 is generated based on the gray scale voltage transferred by the gray scale voltage line 210. Generally, the reference voltage of the gray scale voltage transferred by the gray scale voltage line 210 is a voltage of a plurality of levels from a black display voltage to a white display voltage.

In the scan driving circuit 204, a control signal 208
The selection voltage is applied to the scanning line 215 sequentially from the first line in synchronization with the selection line. At this time, the TFT 217 of each pixel portion 216
Is in a selected state when a selection voltage is applied, and applies a gradation voltage transferred from the signal line group 214 to the liquid crystal 218 and the compensation capacitor 219. Then, when a non-selection voltage is applied to the scanning line 215, it is held until the next state is selected.

As described above, in the liquid crystal display, gradation control is performed by controlling scanning in a line-sequential manner and controlling the amount of light transmitted at the voltage level of the effective voltage value applied to the liquid crystal 218.

The operation of applying a voltage to the liquid crystal 218 of the pixel portion 216 will be described in more detail with reference to FIG.

As shown in FIG. 3, the selection voltage Vg is applied to the scanning line G1.
When “on” is applied, the TFT 217 shown in FIG.
As described above, when the non-selection voltage Vgoff is applied to the scanning line G1 when the non-selection voltage Vgoff is applied to the liquid crystal 218 of the pixel portion 216, the TFT 217 is turned off at this timing, and holds the voltage.

At the timing when the selection voltage Vgon is applied to the scanning line G1, the voltage level of the counter electrode 212 becomes Vc.
Since omN has a negative polarity, the voltage applied to the liquid crystal is a positive voltage. Similarly, the selection voltage Vgon is applied to the scanning line G2.
Is applied, the voltage level of the counter electrode 212 is VcomP and the polarity is positive, so the voltage applied to the liquid crystal is a negative voltage.

Generally, a liquid crystal is composed of one frame (about 60H).
z) Since it is necessary to apply an AC voltage in a cycle, in a line corresponding to each scanning line group 215, it is necessary to apply a voltage having the opposite polarity to the previously applied voltage at the next voltage application timing. .

Further, when the polarity of the gradation voltage applied to the entire screen is deviated to one side, a flicker phenomenon called flicker occurs. Therefore, in this conventional example, AC driving for each line is realized such that a positive and a negative gradation voltages are applied for each line. The voltage level of the opposing electrode 212 makes VcomP of the positive polarity and VcomN of the negative polarity alternate for each line.

The feature of the conventional driving method is that when a positive and negative gradation voltage is applied to the liquid crystal, a signal driving circuit having a dynamic range twice as large as the gradation voltage Vd shown in FIG. 3 is required. However, the counter electrode voltage Vc of the counter electrode 212
Since om is converted to AC, the dynamic range shown in FIG. 2, that is, the signal drive circuit 203 having a withstand voltage capable of generating a grayscale voltage of one polarity can be configured.

[0027]

Problems to be solved by the conventional liquid crystal display will be described with reference to FIGS.
FIG. 4 is an example of a display screen when displaying on a conventional liquid crystal display. FIG. 5 is a current path diagram for explaining image quality deterioration factors of a conventional liquid crystal display. FIG. 6 is a driving waveform diagram for explaining the image quality deterioration factor of the conventional liquid crystal display.

In FIG. 4, (a) shows an intermediate gray on the entire screen, a white rectangle in the center, and a light gray (gray with higher luminance (brightness) than gray displayed on the entire screen) rectangle. , A lighter gray (gray having a higher luminance (brightness) than the light gray) rectangle is displayed, and the grays of the left and right display areas of the three rectangles are different from the grays of the other areas. Thus, a phenomenon is shown in which the luminance decreases and the amount of gray luminance decrease in the left and right display areas of the rectangle changes according to the luminance levels of the three types of rectangles displayed at the center.

Similarly, in FIG. 4B, gray is displayed on the entire screen, and a black rectangle, a dark gray (gray whose luminance is lower than the gray displayed on the entire screen) rectangle in the center, and a darker gray This is an example of displaying a rectangle (gray having a lower brightness (brightness) than the dark gray), in which the gray in the left and right display areas of the three rectangles is lower in brightness than the gray in the other areas. This shows a phenomenon in which the gray luminance increase amounts of the left and right display areas of the three types of rectangles change in accordance with the luminance level of the rectangle displayed at the center further.

FIG. 5 shows a current path when the voltage applied to each pixel on the line selected by the scanning line G1 has a positive polarity.
13 shows a state in which current is concentrated.

In FIG. 6, CL1 is a horizontal synchronizing signal, which is enabled once in one horizontal period, and a timing signal for converting grayscale display data for one horizontal line into a grayscale voltage and outputting it. Become. M is a liquid crystal alternating signal. When the signal is at a “low” level, the common electrode voltage Vcom is set to a negative polarity.
At the time of the “high” level, control is performed such that the common electrode voltage Vcom has a positive polarity. Vda is a gray scale voltage waveform obtained by simplifying the description of the portion of Da shown in FIG. 4A (reducing the number of lines), and Vdb simplifies the portion of Db shown in FIG. 4A. 7 is a gray scale voltage waveform described in a simplified form (reduced in the number of lines).

With respect to the common electrode voltage Vcom, a solid line (V
(comA) is a waveform diagram of the counter electrode line 212 at the output end of the power supply circuit 206 shown in FIG. 2, and is indicated by a broken line (VcomB).
8 is a waveform diagram inside the liquid crystal panel 205.

Next, the causes of image quality deterioration described in FIG. 4 will be described in detail with reference to FIGS.

The luminance displayed by the conventional liquid crystal display is controlled by the effective voltage Vdrms applied to the liquid crystal 218. For example, when the effective voltage is high, a high-luminance color (white) is displayed. When the effective value is low, control is performed so that a low-luminance color (black) is displayed.

In FIG. 5, since the counter electrode 212 and the compensation electrode 213 are common to each pixel, current concentrates on the counter electrode 212 and the compensation electrode 213 in all pixel portions. When this current is concentrated, voltage distortion occurs in the counter electrode voltage and the compensation electrode voltage due to loads such as resistances (not shown) of the counter electrode 212 and the compensation electrode 213.

This voltage distortion is as shown in FIG. That is, during the periods of tH1 and tH2 (the upper gray display area of the rectangular area shown in FIG. 4A) and tH9 (the lower gray display area of the rectangular area shown in FIG. The level is constant in the horizontal direction like Vda and Vdb (grayscale voltage of the intermediate voltage level), and the counter electrode voltage is like VcomB, but tH3 and tH4 (both are white as shown in FIG. 4A). Display area of rectangular area), tH
In the period of 5, tH6 (the display area of the light gray rectangular area shown in FIG. 4A), and tH7 and tH8 (the display area of the light gray rectangular area shown in FIG. 4A), Vda In order to perform white rectangular display, lighter gray rectangular display, and light gray rectangular display, the amount of current increases.

As a result, the amount of current concentrated on the common electrode 212 and the compensating electrode 213 increases, so that the common electrode voltage VcomB inside the liquid crystal panel 205 does not reach the desired voltage level of the common electrode voltage VcomA. ΔVcom1 when displaying a rectangle, ΔVcom2 when displaying a lighter gray rectangle, and Δ when displaying a light gray rectangle.
The counter electrode voltage Vcom decreases by Vcom3.

The amount of current concentrated on the counter electrode 212 and the compensating electrode 213 also changes according to the rectangular luminance level displayed at the center, and the amount of decrease from the desired counter electrode voltage VcomA is ΔVcom1, ΔVcom2, ΔVcom3.
And change. Thus, the original effective voltage value Vdrms obtained at tH1, tH2, and tH9 is increased by tH
3, Vdrms-ΔVc in white rectangular display at tH4
In the light gray rectangular display at om1, tH5, and tH6, Vdrms-.DELTA.Vcom2, and in the light gray rectangular display at tH7, tH8, Vdrms-.DELTA.Vcom3, the reduced effective voltage values are applied to the liquid crystal 218.

Since the luminance displayed by the liquid crystal display is controlled by the effective voltage value applied to the liquid crystal 218, if the desired effective voltage value cannot be obtained, the display luminance changes.
As a result, the gray luminance of the left and right display areas of the rectangular area in the Db area illustrated in FIG. 4 is lower than the gray luminance of the other areas.

On the other hand, as shown in FIG. 4B, when a black rectangular area, a darker gray rectangular area, and a dark gray rectangular area are provided, the amount of current concentrated only in the line area decreases, so that the current applied to the liquid crystal is reduced. Since the effective voltage value increases, a phenomenon occurs in which the luminance increases.

As described above, in the conventional liquid crystal display, the counter electrode 212 and the compensating electrode 213 are set in accordance with the display data.
The amount of current concentrated on the electrode increases / decreases, and the amount of voltage distortion of the common electrode voltage and the compensation voltage fluctuates, thereby deteriorating the image quality.

The present invention has been made in view of the above points.
An object of the present invention is to provide a liquid crystal display device that realizes high-quality display using a low-voltage signal driving circuit and a driving method thereof.

[0043]

In order to achieve the above object, the present invention provides a liquid crystal panel having M pixels in a horizontal direction and N pixels in a vertical direction, including a switching element and a liquid crystal.
A signal driving circuit for inputting display data, generating a gray scale voltage corresponding to the input display data, and applying the same to the pixel unit in the horizontal direction corresponding to the display data; and the pixels arranged in the vertical direction. One of the pixels is sequentially selected, and a selection voltage is applied to the currently arranged pixel array arranged in the vertical direction, while the unselected pixels are arranged in the vertically arranged pixel array which is not selected at that time. A scan drive circuit for applying a voltage, wherein the liquid crystal has, on one side, a common counter electrode in each of the pixel portions, and a selection voltage to be output to the scan drive circuit is applied to the switching element of the pixel portion. In the liquid crystal display device or the driving method thereof, wherein a gray scale voltage generated by the signal driving circuit is applied to the liquid crystal and display luminance is controlled by an effective voltage value of the gray scale voltage with respect to the counter electrode, That a means for detecting a data amount of the display data, in response to said detected display data, and a voltage correction means for correcting for the counter electrode voltage or the voltage application period that every horizontal period.

Here, as an example, the voltage correction means outputs a correction period control signal for controlling a period for correcting the counter electrode voltage value for each horizontal period in accordance with the detected display data. A circuit for generating, and a control for adding / subtracting a constant correction voltage value to the common electrode voltage value only during a period corresponding to the detected display data amount within each horizontal period according to the generated correction period control signal. The circuit may be configured to include In this case, it is preferable that the circuit for generating the correction period control signal includes a data conversion circuit including a decoder circuit, a coincidence circuit, and a counter circuit. Further, it is preferable that the power supply circuit that controls addition / subtraction of the correction voltage value includes an analog addition / subtraction circuit and an analog selection circuit.

Further, as another example, the voltage correction means includes a circuit for generating a correction period control signal for correcting the common electrode voltage for a certain period within one horizontal period, and a circuit for generating the correction period. A circuit may be provided which includes a circuit for adding / subtracting a correction voltage value corresponding to the detected display data amount to the counter electrode voltage value for a certain period within one horizontal period in response to a control signal. In this case, it is preferable that the circuit that generates the correction period control signal includes a counter circuit and a coincidence circuit. It is preferable that the circuit for controlling the addition / subtraction of the correction voltage value includes a digital / analog conversion circuit, an analog addition / subtraction circuit, and an analog selection circuit.

Further, as another example, the voltage correction means includes a correction period control signal for controlling a period for correcting the common electrode voltage value within one horizontal period according to the detected display data. And a circuit that controls addition / subtraction of a correction voltage value corresponding to a display data amount to the common electrode voltage value only during a period corresponding to the generated correction period control signal. In this case, it is preferable that the circuit that generates the correction period control signal includes a data conversion circuit including a decoder circuit, a coincidence circuit, and a counter circuit. It is preferable that the circuit for controlling the addition / subtraction of the correction voltage value includes a digital / analog conversion circuit, an analog addition / subtraction circuit, and an analog selection circuit.

[0047]

FIG. 1 and FIGS. 7, 8, 9 and 10 show a first embodiment of a liquid crystal display device according to the present invention.
This will be described with reference to FIG.

FIG. 1 is a block diagram of the liquid crystal display of the present embodiment. FIG. 7 is a circuit diagram for calculating a voltage correction amount in the interface circuit. FIG. 8 is a circuit diagram for generating a correction period control signal for controlling the means for correcting the common electrode voltage value within one horizontal period according to the display data in the interface circuit of the present embodiment. . FIG. 9 is a counter electrode voltage correction circuit diagram in the power supply circuit of the present embodiment using the correction period control signal generated in FIG. FIG. 10 is a driving waveform diagram of the present embodiment.

In FIG. 1, reference numeral 101 denotes an interface signal including a display signal and a synchronization signal transferred from a system such as a computer (not shown). 102
Is an interface circuit, which generates display data and control signals for driving the liquid crystal display of the present embodiment. Reference numeral 103 denotes a signal drive circuit, which generates a gray scale voltage corresponding to display data. A scanning drive circuit 104 sequentially selects scanning lines. Reference numeral 105 denotes a liquid crystal panel on which a display corresponding to the display data is performed. 106 is a power supply circuit.

Of the control signals generated by the interface circuit 102, 107 is a control signal for the signal driving circuit 103, and includes display data and control signals. 108 is
This is a control signal for the scan drive circuit 104, and transfers a timing signal to sequentially select scan lines. 109
Is an alternating signal 'M' to be transferred to the power supply circuit 106, 110 is a control signal for transferring the voltage correction amount,
111 is a correction period control signal generated in the interface circuit.

Of the voltage signals generated by the power supply circuit 106, reference numeral 112 denotes a gray scale voltage signal to be transferred to the signal driving circuit 103, which is a reference voltage of a gray scale voltage corresponding to display data transferred to the liquid crystal panel 105. To transfer. 113
Is a scanning voltage signal transferred to the scanning drive circuit 104, 114 is a counter electrode connected to the liquid crystal of the liquid crystal 105, and 115 is a compensation electrode connected to the additional capacitance of the liquid crystal panel 105. Reference numeral 116 denotes a group of signal lines for transferring a gray scale voltage corresponding to display data, and 117 denotes a group of scanning lines for transferring a scanning voltage for selecting or deselecting a scanning line.

Numeral 118 denotes a pixel section constituting the liquid crystal panel 105, and 119 denotes a thin film transistor (Thin Film Transistor) which is a switching element.
r, hereinafter referred to as TFT. ), 120 is a liquid crystal, and 121 is a compensation capacitance.

In the correction amount data generating circuit shown in FIG. 7, reference numerals 701, 702, and 703 denote counters having a load function, and 704, 705, and 706 denote counters 70 respectively.
1, 702, and 703.
7, 708, and 709 are latch circuits;
1 and 712 are data buses output from the latch circuits 707, 708 and 709, respectively, and 713 is an adder circuit.

RD [7: 0] is red display data, GD [7: 0] is green display data, BD
[7: 0] is blue display data, DCLK is a clock synchronized with the previous display data, and HSYNC
Is a horizontal synchronizing signal, and VSYNC is a vertical synchronizing signal. Both of these signals are included in the interface signal 101 shown in FIG. 1 and transferred from a system (not shown).

In the correction period control signal generation circuit shown in FIG. 8, reference numeral 801 denotes a latch circuit; 802, an output data bus of the latch circuit 801; 803, a counter circuit with a load function; An output data bus of the counter circuit 803 includes a decoder circuit 805 that converts the display data amount output from the latch circuit 801 into a count value corresponding to a period in which the counter electrode voltage value is corrected. Conversion circuit, 8
06 is an output data bus of the data conversion circuit 805 composed of a decoder circuit, 807 is a coincidence circuit,
8 is an output signal line of the matching circuit 807, and 809 is
JK flip-flop. DCLK, HSYNC,
VSYNC is the same as the signal shown in FIG.

In the counter electrode voltage correction circuit shown in FIG. 9, reference numerals 901 and 902 denote resistors for voltage division.
Reference numerals 904, 90 denote correction voltage lines for the counter electrode voltage.
5, 906 are resistors for voltage division, 907 is a counter electrode reference voltage line of positive polarity, 908 is a counter electrode reference voltage line of negative polarity, and 909 is an analog voltage addition circuit. , 910 are analog voltage subtraction circuits, and 911 and 912 are analog voltage addition circuits 9 respectively.
09, output voltage lines of the analog voltage subtraction circuit 910, 913 and 914 are analog voltage selection circuits, 915 and 916 are output voltage lines of the analog voltage selection circuits 913 and 914, respectively, and 917 is An analog voltage selection circuit 918 is an output voltage line of the analog voltage selection circuit 917, and 919 is a current amplification circuit.

In FIG. 10, CL1 is a horizontal synchronizing signal, which is enabled once in one horizontal period, and a timing signal for converting grayscale display data for one horizontal line into a grayscale voltage and outputting it. Become. M is a liquid crystal alternating signal,
At the time of a “low” level, control is performed such that the counter electrode voltage Vcom has a negative polarity, and at the time of a “high” level, control has been performed such that the counter electrode voltage Vcom has a positive polarity. Vdc is tH1, tH2, tH5
Is a gray scale voltage for performing gray display, a gray scale voltage for performing white display in the period of tH3 and tH4, a gray scale voltage for performing brighter gray display at tH5 and tH6, and a gray scale voltage for performing light gray display at tH7 and tH8. 7 is a grayscale voltage waveform of a signal line that outputs an adjustment voltage. Vdd is tH1, tH2, tH3, tH4,
Each of tH5, tH6, tH7, tH8, and tH9 is a gradation voltage waveform of a signal line that outputs a gradation voltage for performing gray display. Regarding the common electrode voltage Vcom, a solid line (Vco
mC) is a waveform diagram of the counter electrode line 113 at the output end of the power supply circuit 106 shown in FIG. 1, and a dashed line (VcomD) is a waveform diagram inside the liquid crystal panel 105.

The detailed operation of the liquid crystal display according to the first embodiment of the present invention will be described again with reference to FIG.

The display data and the synchronization signal transferred by the interface signal 101 are input to the interface circuit 102, and the interface circuit 102
03, a control signal 108 for controlling the scanning drive circuit 104, a liquid crystal alternating signal 109 for controlling the power supply circuit 106, a control signal 110 for transferring the voltage correction amount, and a time for applying the correction voltage of the counter electrode voltage. Is generated.

The signal driving circuit 103 sequentially takes in the display data for one horizontal line, and when the display data for one horizontal line is completely taken in, the gradation voltage corresponding to the taken-in display data for one horizontal line is applied to the signal line. One horizontal line is simultaneously output from the group 115. The signal drive circuit 103 keeps outputting the grayscale voltage for one horizontal line during one horizontal period. At this time, the signal drive circuit 103 performs operations for sequentially taking in display data of the next horizontal line in parallel. Therefore, the display data output by the interface circuit 102 is output to the liquid crystal panel 105 as a gray scale voltage during the next horizontal period. This operation is repeatedly performed by the signal driving circuit 103, and the gradation voltage corresponding to the display data for one frame, that is, one screen, is applied to the liquid crystal panel 10.
5 will be output.

The gray scale voltage output from the signal drive circuit 103 is generated based on the gray scale voltage transferred by the gray scale voltage line 112. Generally, a reference voltage of a gray scale voltage transferred by the gray scale voltage line 112 is a voltage of a plurality of levels from a voltage for black display to a voltage for white display, and this embodiment will be described similarly. .

In the scanning drive circuit 104, the control signal 108
The selection voltage is applied to the scanning lines 117 sequentially from the first line in synchronization with the selection line. At this time, the TFT 119 of each pixel portion 118
Is in a selected state when a selection voltage is applied, and applies a gradation voltage transferred from the signal line group 116 to the liquid crystal 120 and the compensation capacitor 121. Then, when the non-selection voltage is applied to the scanning line 117, it is held until the next state is selected.

As described above, in the liquid crystal display, the pixel portion 118 having a matrix structure is controlled to scan in a line-sequential manner, and the amount of light transmitted at the voltage level applied to the liquid crystal 120 is controlled. Display is realized. The basic operation up to this point is the same as that of the conventional liquid crystal display (FIGS. 2 and 3).

In this embodiment, the interface circuit 10
2 and the power supply circuit 106 is characterized in that the counter voltage is corrected.

The correction amount data generation circuit shown in FIG. 7 is arranged in the interface circuit 102 and outputs a control signal 110 indicating voltage correction data. In this correction amount data generation circuit, the most significant bit RD7 of the red display data RD [7: 0], the most significant bit GD7 of the green display data GD [7: 0], and the blue display data BD [7: 0]
When the most significant bit BD7 becomes valid, each of the counters 701, 702, 703 causes the dot clock DCLK
Counts up in synchronization with. If each display data is not valid, the count-up operation is not performed.

When the horizontal synchronization signal HSYNC becomes valid, the values counted by the counters 701, 702, 703 are
It is held in each of the latch circuits 707, 708, 709. At this time, the count data of each of the counters 701, 702, and 703 is cleared by the horizontal synchronization signal HSYNC. The red display data, green display data, and blue display data stored in the latch circuits 707, 708, and 709 are added by an adder 713 to detect the amount of data in one horizontal period.

In this embodiment, when the amount of white display data is large, control is performed so that the correction amount data value is increased.

In the correction period control signal generation circuit shown in FIG. 8 included in the interface circuit 102, a correction period for controlling a period for correcting the common electrode voltage value within one horizontal period according to display data. The control signal 111 is output. In the correction period control signal generation circuit, the correction data transferred from the correction amount data generation circuit shown in FIG.
The data is held in the latch circuit 801. Then, the correction data is converted into digital data having a value within the range of the number of clocks in one horizontal period by a data conversion circuit 805 including a decoder circuit. Therefore, the data conversion circuit 805 including the decoder circuit operates so that the digital data corresponding to the correction period increases / decreases according to the correction data.

In the present embodiment, for example, when there is a large amount of white display data, the digital data corresponding to the correction period is controlled so that the number of clocks is increased so that the selection time of the counter electrode voltage to which the correction voltage is applied becomes longer. I do.

On the other hand, the counter circuit 803 always counts up in synchronization with the dot clock. The counter data of the counter 803 is a horizontal synchronization signal HSY.
Cleared by NC. The counter data of the counter 803 is transferred to the matching circuit 807 via the data bus 804.

In the matching circuit 807, when the digital data 806 corresponding to the correction period converted according to the correction data amount matches the counter data 804 output from the counter 803, a signal is output to 808. You.

In the JK flip-flop 809,
The output signal 808 of the matching circuit 807 and the horizontal synchronizing signal HS
YNC is input and the “high” level during the period from the rising of the horizontal synchronization signal HSYNC to the rising of the output signal 808 of the matching circuit 807 is set to “low” during the period from the rising of the output signal 808 of 807 to the end of one horizontal period. A correction period control signal having a level is output from the signal line 111.

The correction data amount calculated in FIG. 7 is a control signal 110, and the correction period control signal 111 generated in FIG.
Is transferred to the common electrode voltage correction circuit (FIG. 9) included in the power supply circuit 106. In the common electrode voltage correction circuit shown in FIG. 9, the common electrode voltage correction voltage generated by the voltage dividing resistors 901 and 902 is transferred by 903 and input to the analog voltage addition circuit 909 and the analog voltage subtraction circuit 910. Is done. Further, a positive counter electrode reference voltage 907 generated by the voltage dividing resistors 904, 905, and 906 is supplied to the analog voltage adding circuit 90.
9, the negative-electrode reference voltage 908 is input to the analog voltage subtraction circuit 910.

In the analog voltage adding circuit 909,
The counter electrode voltage correction voltage and the positive counter electrode reference voltage are added and output, and the analog voltage subtraction circuit 910 outputs the counter electrode voltage correction voltage and the negative polarity. The counter electrode reference voltage is subtracted and output.

The output of the analog voltage adding circuit 909 and the above-mentioned positive counter electrode reference voltage are input to the analog voltage selection circuit 913, and are output in one horizontal period according to the display data shown in FIG. In response, a control signal 111 transferred from a circuit for generating a correction period control signal for controlling a period for correcting the common electrode voltage value changes from a rise of the horizontal synchronization signal HSYNC in accordance with the correction data amount. During the period of the number of dot clocks corresponding to the period, the output of the analog voltage adding circuit 909 is selected, and for the remaining period of one horizontal period, the above-mentioned positive counter electrode reference voltage is selected.
17 is output.

Similarly, the output of the analog voltage subtraction circuit 910 and the negative-electrode reference voltage of the negative polarity are input to the analog voltage selection circuit 914, and the selection signal 111 for selecting the common-electrode voltage is used. Horizontal synchronization signal H
The output of the analog voltage subtraction circuit 910 is selected during the period of the number of dot clocks corresponding to the correction period that changes according to the correction data amount from the rise of the SYNC, and the negative polarity of the remaining horizontal period is selected. The common electrode reference voltage is selected and output to the analog voltage selection circuit 917.

The voltages output from the analog voltage selection circuits 913 and 914 are input to the analog voltage selection circuit 917, selected according to the polarity of the liquid crystal alternating signal 109 ′ M ′, and passed through the current amplification circuit 919. Are output to the counter electrode 114.

Here, when there is a large amount of white display data, the correction period control signal 111 for controlling the correction period generated by the correction period control signal generation circuit shown in FIG. 8 and the counter voltage correction circuit shown in FIG. As a result, tH shown in FIG.
The period Δt adjusted according to the correction data amount like the voltage waveform of VcomC in the periods 3, 3, tH5, tH7
The voltage level is increased by adding the voltage ΔVcom for correcting the common electrode voltage to the common electrode reference voltage of the positive polarity only during 1, Δt2, and Δt3, or the time tH shown in FIG.
Like the voltage waveform of VcomC during the periods 4, 4, tH6, and tH8, the counter electrode voltage is corrected to the negative counter electrode reference voltage only during the periods Δt1, Δt2, and Δt3 adjusted in the respective horizontal periods according to the correction data amount. By subtracting the use voltage ΔVcom, the voltage level can be reduced.

Therefore, the counter voltage inside the liquid crystal panel 105 originally has a large amount of white display data like VcomD, and the counter electrode voltage waveform V inside the liquid crystal panel shown in FIG.
period tH3, tH4 and period tH5, tH
ΔVcom1, ΔVco in H6 and periods tH7 and tH8
Even when the Vcom voltage increases / decreases by m2 and ΔVcom3, the counter electrode voltage correction voltage ΔVc
By adding / subtracting om only during the period of Δt that changes according to the amount of correction data, the effective voltage value Vdrms actually applied to the liquid crystal 120 becomes constant.

As a result, it is possible to reduce the image quality deterioration which has conventionally occurred in the liquid crystal display, and to realize a high image quality display.

In this embodiment, the most significant bit RD7 of the red display data RD [7: 0], the most significant bit GD7 of the green display data GD [7: 0], and the blue display data BD [7: 0], only the most significant bit BD7 is extracted from the display data. In effect, when any of the upper 128 gradations of the 256 gradation display data is input, it is determined that there is display data and the lower 128 bits are present. When any of the gradations is input, it is determined that there is no display data, and each counter 7
01, 702 and 703 are counted up,
Similar effects can be obtained by dividing the 256 gradations into three, four, etc., and determining the correction data by weighting each divided region.

Next, a second embodiment of the liquid crystal display of the present invention will be described with reference to FIGS.

FIG. 11 is a circuit for generating a correction period control signal for correcting the counter electrode voltage for a fixed period within one horizontal period. FIG. 12 is a circuit diagram of a common electrode voltage correction circuit in the power supply circuit of the present embodiment. FIG. 13 is a driving waveform diagram of the liquid crystal display of the present embodiment.

In FIG. 11, reference numeral 1101 denotes a counter circuit having a load function, and 1102 denotes a counter circuit 11
Reference numeral 1103 denotes data (fixed value) of the number of clocks corresponding to the correction period.
Is a matching circuit, 1105 is an output line of the matching circuit 1104, and 1106 is a JK flip-flop. D
CLK and HSYNC are the same as the signals shown in FIG. 7 described in the first embodiment.

In FIG. 12, reference numerals 1201 and 1202 denote:
Digital / analog conversion circuit, 1203, 120
4 are digital / analog conversion circuits 1201 and 12
02 is the correction voltage output,
Reference numeral 1207 denotes a voltage dividing resistor, 1208 denotes a positive-electrode reference voltage, 1209 denotes a negative-electrode reference voltage, 1210 denotes an analog addition circuit, and 1211 denotes an analog subtraction circuit. And 1212
Is the output voltage of the analog addition circuit 1210,
13 is an output voltage of the analog subtraction circuit 1211;
1214, 1215 and 1216 are voltage selection circuits, 1217 is an output voltage of the voltage selection circuit 1214, 1218 is an output voltage of the voltage selection circuit 1215, and 1219 is an output voltage of the voltage selection circuit 1216. And 1220 is a current amplifier circuit.

In FIG. 13, CL and M are the same as in the first embodiment shown in FIG. Vde is tH1,
The grayscale voltages for performing gray display at tH2 and tH5 are tH3,
The grayscale voltages for performing white display in the period of tH4 are represented by tH5 and tH5.
The grayscale voltage for performing a brighter gray display at H6 is tH7,
It is a gradation voltage waveform of a signal line that outputs a gradation voltage for performing a light gray display at tH8. Vdf is tH1, tH2, t
H3, tH4, tH5, tH6, tH7, tH8, tH
9 is a gradation voltage waveform of a signal line that outputs a gradation voltage for performing gray display. Regarding the common electrode voltage Vcom, the solid line (VcomE) indicates the power supply circuit 106 shown in FIG.
FIG. 11 is a waveform diagram of the counter electrode line 113 at the output end of FIG.
(comF) is a waveform diagram inside the liquid crystal panel 105.

In the second embodiment, the correction data generation circuit shown in FIG. 7 described in the first embodiment is used to generate the correction data. Hereinafter, the points different from the first embodiment will be mainly described.

In this embodiment, the interface circuit 10
In a circuit for generating a correction period control signal for performing correction for a certain period within one horizontal period shown in FIG. 11 included in FIG.
A count-up operation is performed in synchronization with K. The counter data output from the counter circuit 1101 is output bus 1
The signal is input to the coincidence circuit 1104 by 102.

The coincidence circuit 1104 has fixed count number data 110 corresponding to a period in which correction is performed within one horizontal period.
3 is input, and the coincidence circuit 1104 outputs a signal to the output signal line 1105 when the output 1102 of the counter circuit matches the fixed count number data 1103.

In the JK flip-flop 1106, the output 1105 of the coincidence circuit 1104 and the horizontal synchronization signal HSYNC are output.
Is input, and the “high” level during the period from the rising of the horizontal synchronization signal HSYNC to the rising of the output signal 1105 of the matching circuit 1104 is changed to “low” during the period from the rising of the output signal 105 of the matching circuit 1104 to the end of one horizontal period. The correction period control signal at which the
11 is output.

In the present embodiment, the correction amount data transferred from the correction amount data generation circuit of FIG. 7 included in the interface circuit 102 (FIG. 1) is included in the power supply circuit 106 by the control signal 110 as shown in FIG. Is transferred to the common electrode voltage correction circuit having the configuration shown in FIG.

The correction amount data 110 input to the common electrode voltage correction circuit of FIG. 12 is converted into analog voltages by digital / analog conversion circuits 1201 and 1202. FIG.
3, the correction voltage amount ΔVcom1 during the tH3 and tH4 periods.
1 and the correction voltage amount ΔVcom21 during the tH5 and tH6 periods.
And the correction voltage amount is generated depending on the data amount of the white display data, such as the correction voltage amount ΔVcom31 in the periods tH7 and tH8.

Therefore, the digital / analog conversion circuit 12
01, 1202, the operation is performed so that the voltage level increases / decreases according to the correction amount data value.

Voltage dividing resistors 1205, 1206, 1
In the voltage divided by 207, the counter electrode reference voltage 1208 of the positive polarity is Vcom of the tH1 period shown in FIG.
E is the voltage level of the peak value of E, and the counter electrode reference voltage 1209 of the negative polarity is Vcom in the tH2 period shown in FIG.
This is the voltage level of the peak value of F.

Further, a counter electrode reference voltage of positive polarity 120
8 and the output 1212 of the analog addition circuit 1210 are:
The signal is input to the analog voltage selection circuit 1214. In response to the correction period control signal 111 for performing correction for a certain period within one horizontal period output from the interface circuit 102, the analog voltage selection circuit 1214 outputs a signal during a certain period Δt shorter than one horizontal line period. , The output 1212 of the analog addition circuit 1210 is selectively output, and in other periods, the positive counter electrode reference voltage 1208 is selectively output.

Similarly, the negative electrode reference voltage 120
9 and the output 1213 of the analog subtraction circuit 1211 are:
The signal is input to the analog voltage selection circuit 1215. In response to the correction period control signal 111 output from the interface circuit 102 for performing correction for a certain period within one horizontal period, the analog voltage selection circuit 1215 outputs a signal during a certain period Δt shorter than one horizontal line period. , The output 1213 of the analog subtraction circuit 1211 is selectively output, and in the other periods, the counter electrode reference voltage 1209 of negative polarity is selectively output.

The voltages 1217 and 1218 output from the voltage selection circuits 1214 and 1215 are
At 216, the counter electrode 11 is selected according to the polarity of the liquid crystal alternating signal 109'M ',
4 is output.

Here, when there is a large amount of white display data, the digital / analog conversion circuits 1203 and 1204 and the analog addition circuit 121 correspond to the white display data amount.
0, analog subtraction circuit 1211 and voltage selection circuit 12
14, 1215, tH3, tH5,
Like the voltage waveform of VcomE in the period tH7, the correction voltage amounts ΔVcom11 and ΔVco corresponding to the white display data amount
By adding m21 and ΔVcom31 to the counter electrode reference voltage of positive polarity for a fixed period Δt shorter than one horizontal line period, the voltage level of the counter electrode voltage VcomF inside the liquid crystal panel 105 is changed to each of tH3, tH5, and tH7. During the period, ΔVcom1, ΔVcom2, ΔVcom3
Only each can be raised.

Further, tH4, tH6 and tH shown in FIG.
Like the voltage waveform of VcomE in eight periods, the correction voltage amount ΔVcom1 corresponding to the white display data amount in each period.
By subtracting 1, ΔVcom21 and ΔVcom31 from the negative-electrode reference voltage for a fixed period Δt shorter than one horizontal line period, the voltage level of the counter voltage VcomF inside the liquid crystal panel 105 is reduced by ΔVc in each period.
om1, ΔVcom2, and ΔVcom3, respectively.

Therefore, the counter voltage inside the liquid crystal panel 105 is added / subtracted by the correction voltage amount corresponding to the white display data amount only during the fixed period Δt shorter than one horizontal period, so that the VcomF shown in FIG. As described above, the voltage is stabilized at the values of the positive and negative counter electrode reference voltages without attenuation, and the effective voltage value Vdrm actually applied to the liquid crystal 120 is obtained.
s is constant irrespective of the amount of display data, so that image quality degradation that has conventionally occurred in liquid crystal displays can be reduced, and high image quality display can be realized.

Next, a third embodiment of the liquid crystal display of the present invention will be described with reference to FIGS.

FIG. 14 is a circuit diagram of a common electrode voltage correction circuit arranged in the power supply circuit 106 of the present embodiment. FIG.
FIG. 4 is a drive waveform diagram of the embodiment.

In FIG. 14, reference numerals 1401 and 1402 denote:
Each is a digital / analog conversion circuit, 140
3 and 1404 are digital / analog conversion circuits 140
1, 1402, and 1405, 140
Reference numerals 6 and 1407 denote resistors for voltage division, respectively.
Reference numeral 408 denotes a counter electrode reference voltage of positive polarity,
Is a negative reference electrode reference voltage, 1410 is an analog voltage addition circuit, 1411 is an analog voltage subtraction circuit, and 1412 is an analog voltage addition circuit 1
Reference numeral 410 denotes an output voltage line, and reference numeral 1413 denotes an output voltage line of the analog voltage subtraction circuit 1413;
Reference numeral 15 denotes an analog voltage selection circuit.
6, 1417 are analog voltage selection circuits 141, respectively.
Reference numerals 1414 and 1415 denote output voltage lines, 1418 denotes an analog voltage selection circuit, 1419 denotes an output voltage line of the analog voltage selection circuit 1418, and 1420 denotes a current amplification circuit.

In FIG. 15, CL1 and M are the same as in the first embodiment shown in FIG. 10, and Vdg is tH1 and tH1.
A grayscale voltage corresponding to gray display is output during the periods H2 and tH9, a grayscale voltage corresponding to white display data is output during the periods tH3 and tH4, and a lighter gray display is supported during the periods tH5 and tH6. The grayscale voltage is output, and tH7, tH
8 is a gray scale voltage waveform of a signal line that outputs a gray scale voltage corresponding to a light gray display in a period 8; Vdh is tH1,
tH2, tH3, tH4, tH5, tH6, tH7, t
Both H8 and tH9 are gray scale voltage waveforms of the signal line corresponding to gray.

Regarding the common electrode voltage Vcom, VcomG indicated by a solid line is a voltage waveform diagram of the common electrode line 114 at the output end of the power supply circuit 106 shown in FIG. 1, and VcomH indicated by a broken line is a liquid crystal. FIG. 6 is a voltage waveform diagram inside panel 105.

In the third embodiment, the correction data is generated using the correction amount data generation circuit shown in FIG. 7 described in the first embodiment and according to the detected display data amount. The generation of the correction period control signal for controlling the period for correcting the counter electrode voltage value in the horizontal period is performed using the correction period control signal generation circuit shown in FIG. 8 described in the first embodiment. In the following, a description will be given focusing on a portion different from the above embodiment.

First, in the common electrode voltage correction circuit shown in FIG. 14, the correction data transferred from the correction amount data circuit shown in FIG.
1402. The input correction data is converted into analog voltages by digital / analog conversion circuits 1401 and 1402, respectively. Therefore, the digital / analog conversion circuits 1401 and 1401
2 so that the voltage level of the analog voltage generated in step 2 increases / decreases.

The analog voltage value generated by the digital / analog conversion circuit 1401 is connected to a voltage dividing resistor 140.
5, 1406 and 1407 together with the positive counter electrode reference voltage 1408
0, and the added analog voltage is again input to the analog voltage selection circuit 14 together with the positive electrode reference voltage.
14 is input.

Similarly, the digital / analog conversion circuit 14
02 is a voltage dividing resistor 1
Analog voltage subtraction circuit 1 together with negative counter electrode reference voltage 1409 generated in 405, 1406 and 1407
The analog voltage input to the subtractor 411 and the subtracted analog voltage are again input to the analog voltage selection circuit 1 together with the negative-electrode reference voltage.
415 is input.

The analog voltage selection circuit 1414 is controlled by the control signal 111 generated by the correction period control signal generation circuit in the interface circuit shown in FIG. 8 from the rise of the horizontal synchronization signal HSYNC in one horizontal period.
During the period Δt until the rise of the control signal 111 that changes according to the correction data amount, the analog voltage adding circuit 1410
Is selected, and the counter electrode reference voltage of positive polarity is selected and output during the remaining period of one horizontal period.

Similarly, analog voltage selection circuit 1415
The analog voltage subtraction circuit 1411 calculates the period Δt from the rise of the horizontal synchronization signal HSYNC to the rise of the correction period control signal adjusted according to the correction data amount in one horizontal period by the correction period control signal 111.
, And the negative counter electrode reference voltage is selected and output during the remaining period of one horizontal period. The analog voltages output from the analog voltage selection circuits 1414 and 1415 are input to the analog voltage selection circuit 1418,
Selected according to the polarity of the liquid crystal alternating signal 109'M ',
The signal is output to the counter electrode 114 via the current amplification circuit 1420.

Here, when the amount of white display data is large, the display data amount 110 generated by the correction data amount generation circuit shown in FIG. 7 described in the first embodiment and the correction data shown in FIG. The correction period control signal 111 output from the period control signal generation circuit and the counter electrode voltage correction circuit described in FIG.
5, like the voltage waveform of VcomG in the period of tH7, Δ adjusted in accordance with the correction data amount in each horizontal period.
During the periods of t11, Δt21, and Δt31, the counter electrode correction voltage ΔVcom1 adjusted according to the correction data amount, respectively.
2, ΔVcom22 and ΔVcom32 are added to the counter electrode reference voltage of positive polarity and output, so that the voltage level can be increased.

Further, tH4 and tH shown in FIG.
6, Δt adjusted according to the correction data amount in each horizontal period, like the voltage waveform of VcomG in the period tH8.
11, Δt21, Δt31, the counter electrode correction voltage Δ adjusted according to the correction data amount in each horizontal period
Vcom12, ΔVcom22, and ΔVcom32 are subtracted and output from the negative-electrode reference voltage to reduce the voltage level.

Accordingly, the counter voltage inside the liquid crystal panel 105 originally has a large amount of white display data like VcomH, and for example, the period tH like VcomB shown in FIG.
ΔVc at 3, tH4, tH5, tH6, tH7 and tH8
om1, ΔVcom2, ΔVcom3, and Vco
Even when the voltage m increases / decreases, the counter electrode correction voltage ΔVcom adjusted according to the correction data amount
Is added / subtracted for a period of Δt which is also adjusted according to the correction data amount, so that the effective voltage value Vdrms applied to the liquid crystal 120 becomes constant. Therefore, image quality degradation that has conventionally occurred in liquid crystal displays is reduced,
High quality display can be realized.

[0115]

According to the first embodiment of the present invention, the amount of data to be displayed is detected, and the period in which a fixed counter electrode correction voltage is added to / subtracted from the counter electrode reference voltage is detected. By adjusting within the range within one horizontal period according to the display data amount, it is possible to correct the counter electrode voltage depending on the display data amount, keep the effective voltage value applied to the liquid crystal constant, and drive at low voltage. Even if a corresponding signal drive circuit is used, there is an effect that high-quality display can be realized.

Further, according to the second embodiment of the present invention,
By detecting the amount of display data and adding / subtracting the counter electrode correction voltage according to the display data amount to / from the counter electrode reference voltage during a certain period, it is possible to correct the counter electrode voltage level depending on the display data amount. In this case, the effective voltage value applied to the liquid crystal is kept constant, and a high-quality display can be realized even if a signal driving circuit corresponding to low-voltage driving is used.

According to the third embodiment of the present invention,
By detecting the amount of display data and adjusting the period for adding / subtracting the counter electrode correction voltage according to the display data amount to the counter electrode reference voltage within one horizontal period according to the display data amount. In addition, it is possible to correct the counter electrode voltage depending on the display data amount, to keep the effective value applied to the liquid crystal constant, and to achieve high image quality display even by using a signal driving circuit compatible with low voltage driving.

In the first and third embodiments of the present invention, the period for adding / subtracting the common electrode correction voltage to / from the common electrode reference voltage is adjusted depending on the display data amount within the range of one horizontal period. Therefore, the effective value applied to the liquid crystal is kept constant regardless of the length of one horizontal period due to the increase or decrease of the total number of the scanning lines of the liquid crystal panel, and the signal circuit corresponding to the low voltage driving is used. Even if it is used, there is an effect that high quality display can be realized.

Further, in the first to third embodiments of the present invention, the use of the signal driving circuit corresponding to the low-voltage driving has an effect that low power consumption can be realized.

Further, according to the first to third embodiments of the present invention, it is possible to use a signal drive circuit corresponding to low voltage drive, and a signal drive circuit can be formed by a low-cost general-purpose LSI process. The price of the entire liquid crystal display can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a liquid crystal display of the present invention.

FIG. 2 is a block diagram of a conventional liquid crystal display.

FIG. 3 is a driving waveform diagram of a conventional liquid crystal display.

FIG. 4 is an explanatory view showing a display example of a conventional liquid crystal display.

FIG. 5 is an explanatory diagram showing a current path of a conventional liquid crystal display.

FIG. 6 is a driving waveform diagram of a conventional liquid crystal display.

FIG. 7 is a block diagram of a correction amount data generation circuit according to the present invention.

FIG. 8 is a block diagram of a correction period control signal generation circuit according to the present invention.

FIG. 9 is a block diagram of a common electrode voltage correction circuit according to the present invention.

FIG. 10 is a driving waveform diagram of the liquid crystal display of the present invention.

FIG. 11 is a block diagram of a correction period control signal generation circuit according to the present invention.

FIG. 12 is a block diagram of a common electrode voltage correction circuit according to the present invention.

FIG. 13 is a driving waveform diagram of the liquid crystal display of the present invention.

FIG. 14 is a block diagram of a common electrode voltage correction circuit according to the present invention.

FIG. 15 is a driving waveform diagram of the liquid crystal display of the present invention.

[Explanation of symbols]

101: interface signal, 102: interface circuit, 103: signal drive circuit, 104: scan drive circuit,
105: liquid crystal panel, 106: power supply circuit, 107: control signal, 108: control signal, 109: alternating signal, 110
.., Control signal, 111, correction period control signal, 112, gradation voltage signal, 113, scanning voltage signal, 114, counter electrode,
115: Compensation electrode, 116: Signal line group, 117: Scan line group, 118: Pixel portion, 119: Thin film transistor, 12
0: liquid crystal, 121: compensation capacitance, 201: interface signal, 202: interface circuit, 203: signal drive circuit, 204: scan drive circuit, 205: liquid crystal panel, 2
06: power supply circuit, 207: control signal, 208: control signal, 209: AC signal, 210: gradation voltage signal, 21
DESCRIPTION OF SYMBOLS 1 ... Scan voltage signal, 212 ... Counter electrode, 213 ... Compensation electrode, 214 ... Signal line group, 215 ... Scan line group, 216 ... Pixel part, 217 ... Thin film transistor, 218 ... Liquid crystal, 21
9: Compensation capacity, 701: Counter with load function, 7
02: Counter with load function, 703: Counter with load function, 704: Data bus, 705: Data bus, 706: Data bus, 707: Latch circuit, 70
8 Latch circuit, 709 Latch circuit, 710 Data bus, 711 Data bus, 712 Data bus, 71
3. Addition circuit, 801 Latch circuit, 802 Data bus, 803 Counter circuit with load function, 804 Data bus, 805 Data conversion circuit composed of decoder circuit, 806 Data bus, 807 Match circuit, 808
Output signal line, 809 ... JK flip-flop, 901 ...
Resistance, 902: Resistance, 903: Correction voltage line, 904: Resistance, 905: Resistance, 906: Resistance, 907: Positive counter electrode reference voltage, 908: Negative counter electrode correction voltage,
909: analog voltage adding circuit, 910: analog voltage subtracting circuit, 911: output voltage line, 912: output voltage line,
913: analog voltage selection circuit, 914: analog voltage selection circuit, 915: output voltage line, 916: output voltage line,
917: an analog voltage selection circuit, 918: an output voltage line,
919: current amplifier circuit, 1101: counter circuit with load function, 1102: data bus, 1103: data bus, 1104: coincidence circuit, 1105: output signal line 110
6 JK flip-flop, 1201 digital / analog conversion circuit, 1202 digital / analog conversion circuit, 1203 correction voltage line, 1204 correction voltage line, 1
205: resistor, 1206: resistor, 1207: resistor, 12
08 ... positive counter electrode reference voltage, 1209 ... negative counter electrode reference voltage, 1210 ... analog voltage addition circuit,
1211 ... analog voltage subtraction circuit, 1212 ... output voltage line, 1213 ... output voltage line, 1214 ... analog voltage selection circuit, 1215 ... analog voltage selection circuit, 1216 ...
Analog voltage selection circuit, 1217 ... output voltage line, 121
8 output voltage line, 1219 output voltage line, 1220 current amplification circuit, 1401 digital / analog conversion circuit,
1402 digital / analog conversion circuit, 1403 correction voltage line, 1404 correction voltage line, 1405 resistance, 1
406: resistance, 1407: resistance, 1408: positive counter electrode reference voltage, 1409: negative counter electrode reference voltage, 1410: analog voltage addition circuit, 1411: analog voltage subtraction circuit, 1412: output voltage line, 1413 ...
Output voltage line, 1414... Analog voltage selection circuit, 141
5 ... analog voltage selection circuit, 1416 ... output voltage line, 1
417: output voltage line, 1418: analog voltage selection circuit, 1419: output voltage line, 1420: current amplifier circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Norihisa Ono 3300 Hayano Mobara City, Chiba Prefecture Hitachi, Ltd.Electronic Device Division (72) Inventor Sumisa Ohishi 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Hitachi, Ltd. F-term in the System Development Laboratory (Reference) 2H093 NA16 NA43 NC13 NC21 NC25 NC27 NC34 NC49 NC62 NC90 ND15 NF04 5C006 AA01 AA16 AA22 AC27 AF42 AF44 AF46 AF52 BB16 BF04 BF06 BF14 BF16 BF22 BF25 BF26 DD03 FA04 EE29 FF11 JJ02 JJ03 JJ04

Claims (5)

[Claims] 1. A liquid crystal panel having M pixels in a horizontal direction and N pixels in a vertical direction including a switching element and a liquid crystal, and inputting display data and generating a gradation voltage according to the input display data. And a signal drive circuit for applying the same to the pixel unit in the horizontal direction corresponding to the display data, and sequentially selecting one of the pixel units arranged in the vertical direction, and arranging in the vertical direction selected at that time. A pixel section to be applied is provided with a scanning drive circuit that applies a selection voltage to the pixel section that is not selected at that time and that is arranged in the vertical direction, and applies a non-selection voltage to the pixel section. When a selection voltage to be output to the scan driving circuit is applied to the switching element of the pixel portion, a gradation voltage generated by the signal driving circuit is applied to the liquid crystal, and Before In a liquid crystal display device that controls display luminance with an effective voltage value of a gray scale voltage, a display data amount detection unit that detects a data amount of the input display data, and each horizontal period according to the detected display data amount. A liquid crystal display device comprising: a voltage correction unit for correcting at least one of the common electrode voltage value and the voltage application period for each time. 2. The liquid crystal display device according to claim 1, wherein the voltage correction means controls a period for correcting the counter electrode voltage value for each horizontal period according to the detected display data amount. A circuit for generating a correction period control signal for performing the correction, and in response to the generated correction period control signal, the counter electrode voltage value is previously set to a value corresponding to the detected display data amount within a corresponding horizontal period. A liquid crystal display device having a circuit for controlling addition or subtraction of a determined correction voltage value. 3. The liquid crystal display device according to claim 1, wherein the voltage correction means includes a correction period control signal for correcting the common electrode voltage for a predetermined period within each horizontal period. A generating circuit, and adding or subtracting a correction voltage value corresponding to the detected display data amount to the common electrode voltage value only for a predetermined period in each horizontal period, in accordance with the generated correction period control signal. A liquid crystal display device comprising: a control circuit. 4. The liquid crystal display device according to claim 1, wherein the voltage correction means controls a period for correcting the common electrode voltage value for each horizontal period according to the detected display data. A circuit for generating a correction period control signal for the same; and a circuit for adding or subtracting a correction voltage value corresponding to the display data amount to the counter electrode voltage value for a period corresponding to the generated correction period control signal. A liquid crystal display device comprising: 5. A liquid crystal panel having M pixels in a horizontal direction and N pixels in a vertical direction including a switching element and a liquid crystal, and inputting display data and generating a gradation voltage according to the input display data. And a signal drive circuit for applying the same to the pixel unit in the horizontal direction corresponding to the display data, and sequentially selecting one of the pixel units arranged in the vertical direction, and arranging in the vertical direction selected at that time. A pixel portion to be applied is provided with a scanning drive circuit for applying a selection voltage, and a non-selected pixel portion arranged in the vertical direction at that time is applied with a non-selection voltage, and the liquid crystal is shared on one side by the pixel portions. When a selection voltage to be output to the scan driving circuit is applied to the switching element of the pixel portion, a gradation voltage generated by the signal driving circuit is applied to the liquid crystal, and Before In a driving method of a liquid crystal display device for controlling display luminance with an effective voltage value of a gray scale voltage, a data amount of the input display data is detected, and in accordance with the detected display data amount, A method of driving a liquid crystal display device, wherein at least one of a common electrode voltage value and a voltage application period is corrected.