JPH0221803Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to glitch removal circuits incorporated within high performance amplifiers.

[Technical background of the invention and its problems]

Since glitches often included in signals have harmful effects such as circuit malfunction, several circuits have been proposed to remove them.

FIG. 1 shows an example of a conventional glitch removal circuit. In the figure, the output of a current output digital-to-analog converter (hereinafter referred to as DAC) 1 is subjected to current-to-voltage conversion by an amplifier u1. Generally, when the digital input to the DAC changes from X to Y, the timing of the change of each bit of the digital input is slightly different from each other.
1111)→…→(…0111)=Y, and finally settles on Y through other values. As a result, glitches appear in the DAC output. In order to eliminate this glitch, the circuit of FIG. 1 is provided with a sample-and-hold circuit consisting of FET Q1, capacitor Ch, and amplifier u2. Then, just before the digital input to the DAC changes, the FET Q is connected from terminal 3.
By applying a control signal that opens a switch consisting of 1, the current value of amplifier u1 is held. When the output of the amplifier u1 has stabilized, the control signal at the terminal 3 is removed so that the value of the output appears at the output terminal 5.

However, even if an attempt is made to insert the above-mentioned glitch removal circuit into a signal system that requires extremely high accuracy of, for example, about 1 ppm, it is difficult to realize it due to the following drawbacks.

The first drawback is that it works as a switch.
Due to the charge injection effect associated with the capacitance Cs between the gate and drain of FET Q1, each time a control signal is applied or removed from terminal 3, FET Q1
Charge is injected into the drain of the output terminal 5, and another noise appears at the output terminal 5. Current output DAC1
If a 20-bit precision signal is used, the magnitude of this noise will be several tens of times larger than the value represented by the least significant bit of the digital input signal. Therefore, when changing only the lower bit group of the digital input signal, it is preferable not to operate the glitch removal circuit.

A second drawback is that the conventional glitch removal circuit shown in FIG. 1 requires an extra amplifier u2 to provide sample and hold. In other words, even if we use elements with amplification Av = 120 dB and common mode rejection ratio (hereinafter referred to as CMRR) = 114 dB, which are the highest performances available today as single amplifiers u1 and u2, one stage of amplifier u About 1ppm, amplifier u2
When it reaches the stage, the error becomes about 3ppm,
There is no point in using a 20-bit precision current output DAC1 (with 20-bit precision, the error is 1 ppm).

Additionally, in many cases, system nonlinearity poses a major problem. Since the amplification degree and CMRR change due to fluctuations in the input/output levels of amplifiers u1 and u2,
Nonlinearity appears in the output. To prevent this nonlinearity, not only amplifier u1 but also amplifier u2
It is also necessary to use a specially designed one.

[Purpose of invention]

The present invention solves the drawbacks of the conventional glitch removal circuits mentioned above, eliminates the need for an amplifier used only for glitch removal, and eliminates the causes of errors and nonlinearity from a high-precision signal system. The purpose is to provide a removal circuit.

[Summary of the idea]

To achieve this purpose, in the glitch removal circuit of the present invention, first and second amplifiers are connected in series, and a band-limiting circuit is inserted between them to prevent oscillation. Insert the switch. This switch is placed between the band limiting circuit for oscillation prevention and the preceding amplifier.
While the switch is open, the potential can be held by the capacitor in this band limiting circuit, so in the same way as the conventional circuit shown in Figure 1,
While there is a possibility of a glitch occurring, the glitch is removed by opening the switch. This eliminates the need for a dedicated amplifier for the glitch removal circuit, and thus eliminates the conventional problems associated with this. Furthermore, in order to prevent the generation of noise due to the charge injected into the switch, an amount of charge sufficient to cancel out the charge injected when the switch is on and off is applied to the subsequent stage of the switch at each time point.

[Example of idea]

Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 2 is a circuit diagram showing a circuit incorporating a glitch removal circuit according to an embodiment of the present invention. In the figure, a code, which is a digital value outputted from a control logic circuit 7, is applied to a latch 9 by a latch signal L.
and is given to the current output DAC1. The current output DAC1 has very high accuracy, e.g.
It has a bit. The latch signal L is a positive pulse, and a code is set in the latch 9 at the timing of its fall. In addition, the part U surrounded by the broken line in the same figure is the amplifier u shown in FIG.
Corresponds to 1. That is, the front stage is composed of the amplifier U1, and the amplifier U2 and the resistors R6 and R7
The rear part is constructed by: In addition, a circuit (hereinafter referred to as a CR circuit) consisting of resistors R4 and R5 and a capacitor C3 is inserted between the input section and the output section for band limiting to prevent oscillation. Feedback is performed through a capacitor Cf having low dielectric absorption characteristics.

Since the operation of the amplifier circuit shown in FIG. 2 is not directly related to the gist of the present invention, a detailed explanation will not be provided, but FIG. 5 shows an example of the above-mentioned band limiting process. In the figure, the vertical axis represents the degree of amplification in decibels. Further, the horizontal axis represents frequency on a logarithmic scale. In the figure, A is the characteristic of the front part,
B shows the characteristics of the CR circuit, C shows the characteristics of the latter stage, and D shows the part U surrounded by the broken line when there is no capacitor Cf.
, and ho shows the overall characteristics when a capacitor Cf is added.

Now, how the glitch is removed in an embodiment of the present invention will be explained below.

In FIG. 2, a glitch removal circuit is inserted between the front stage section and the CR circuit. That is,
The glitch removal circuit in FIG. 2 consists of a one-shot circuit 11 that inputs a latch signal L and generates a negative pulse Q and a positive pulse of a predetermined width, an FET Q2 which is normally in an on state, a resistor R1, and a capacitor. It consists of a switch section consisting of C1, a charge/injection compensation section (hereinafter simply referred to as a compensation section) consisting of resistors R2 and R3, capacitors C2 and Ck, and diode CR1. With this configuration, the switch part inputs a negative pulse Q and turns off the FET Q2 during that time, thereby preventing glitches that occur when the code applied to the current output DAC1 changes from being transmitted to the next stage.
Figure 3 shows latch signal L, negative pulse Q, and current output.
Output current Idac including glitch of DAC1, output voltage with glitch removed at output terminal 5
Shows the relationship between Vout.

By the way, as explained using FIG.
Another noise is generated by injection.
In order to remove this noise, the compensation section
The injection generates enough charge to cancel the charge injected into the rear stage of the switch part and supplies it to the rear stage of the switch part. The operation of this compensator will be explained below with reference to FIG. 2 and FIG. 4, which shows temporal changes in signals related to this operation.

The basic configuration of the compensator is to introduce a positive pulse with the opposite phase from the negative pulse Q that is the drive signal to the switch section from the one-shot circuit 11, and connect it to the subsequent stage of the switch section via the capacitor Ck. are doing. As a result, a compensation operation is performed by injecting charges having opposite polarity and the same absolute value as the charges injected into the switch portion. However, since the amount of charge injected into the switch section differs when the switch section is on and off, as shown in Figure 4, the values of the capacitor Ck and resistor R3 are adjusted in the compensation section shown in Figure 2. I am dealing with this by doing this. That is, the resistors R2 and R3, the diode CR1, and the compensator shown in FIG.
Due to the action of capacitor C2, when a positive pulse Q is applied to point a, voltages Vb and Vc at points b and c change as shown in FIG. 4, respectively. Therefore, by adjusting the capacitor Ck, it is possible to cancel the charge injected from the switch section when the switch is off, and then by adjusting the resistor R3, it is possible to cancel the charge injected when the switch is on.

Of course, the configuration of the compensator is not limited to that shown in FIG. 2. For example, a first compensation system injects a compensation charge suitable for the amount of compensation when the switch section is off, both when it is off and when it is on (with the opposite polarity to when it is off), and a first compensation system that operates only when the switch section is on; A second compensation system injects charge that cancels out an excess amount of compensation charge injected by the first compensation system when the first compensation system is turned on.
The compensation unit may be constructed from the compensation system.

Further, in the embodiment shown in FIG. 2, the glitch removal circuit of the present invention is provided in the amplifier circuit provided for current-to-voltage conversion, but the structure is not necessarily limited to this. That is, the signal system through which a signal indicating the possibility of a glitch (e.g., latch signal L) is obtained and through which the signal containing the glitch passes includes an amplifier circuit that performs band-limiting processing as described above. If so, the present invention can be applied.

Furthermore, if only the bits in the lower part of the code in the circuit shown in Figure 2 change, and the size of the glitch that occurs does not reach a harmful level, the glitch removal circuit may be constructed so that it does not operate. good.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional glitch removal circuit, FIG. 2 is a circuit diagram showing a circuit incorporating a glitch removal circuit according to an embodiment of the present invention, and FIG.
Figure 4 is a time chart showing the operation of removing glitches in the circuit shown in Figure 2. Figure 4 is a time chart showing the operation of canceling the noise caused by the charge injection of the switch section in Figure 2. FIG. 3 is a diagram illustrating an example of band restriction processing. 1: Current output digital to analog converter,
7: Control logic circuit, 9: Latch, 11: One shot circuit, L: Latch signal, Q1, Q2: FET,
u1, u2, U1, U2: amplifier.

Claims (1)

[Claims for Utility Model Registration] (1) A band limiting circuit is inserted in series between the first and second amplifiers connected in series, and the output of the second amplifier is connected to the first amplifier through a resistor. the first amplifier in an amplifier circuit connected in a feedback connection to an input terminal of the amplifier at a feedback connection and configured to obtain a voltage output from the second amplifier that is proportional to an input current flowing through the feedback connection; a glitch removal circuit inserted in series between the output section of the second amplifier and the band-limiting circuit, the band-limiting circuit being configured to include a capacitor connected in parallel to the input section of the second amplifier; A switch is provided which inputs a signal indicating a time period in which a glitch is included in the signal input to the amplifier circuit and opens during the time period, and during the time period, the voltage held in the capacitor is applied to the second amplifier. A glitch removal circuit designed to give (2) between the switch and the second amplifier,
a circuit that applies a first predetermined charge in response to the switch opening and a second predetermined charge that is determined independently of the first predetermined charge in response to the switch closing; A glitch removal circuit according to claim 1, characterized in that the glitch removal circuit is provided as a utility model.