JPH0983363A - A/d converting circuit - Google Patents

A/d converting circuit

Info

Publication number
JPH0983363A
JPH0983363A JP23568395A JP23568395A JPH0983363A JP H0983363 A JPH0983363 A JP H0983363A JP 23568395 A JP23568395 A JP 23568395A JP 23568395 A JP23568395 A JP 23568395A JP H0983363 A JPH0983363 A JP H0983363A
Authority
JP
Japan
Prior art keywords
converter
output
operational amplifier
signal
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23568395A
Other languages
Japanese (ja)
Inventor
Kazuo Sato
一男 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaskawa Electric Corp
Original Assignee
Yaskawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaskawa Electric Corp filed Critical Yaskawa Electric Corp
Priority to JP23568395A priority Critical patent/JPH0983363A/en
Publication of JPH0983363A publication Critical patent/JPH0983363A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an A/D converter which accelerates speed and improves accuracy without switching any input. SOLUTION: This circuit has an operational amplifier 1 for outputting a differential signal Vd of an analog input signal Vi and an output signal Va of a D/A converter 5, A/D converter 3, comparator 2 parallelly connected to the output of the operational amplifier, and up/down counter 4 for counting clock pulses while switching up and down operations by the comparator 2 to perform an output Vc corresponding to the polarity of output from the operational amplifier 1, and is composed of the D/A converter 5 for converting an output Vo of the up/down counter 4 to an analog signal and outputting it to the operational amplifier 1. Then, a digital output is extracted from the A/D converter 3 and the up/clown counter 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、アナログ信号をディジ
タル信号に変換するA/D変換回路に関し、特に安価で
高速かつ高精度のA/D変換回路の改良に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D conversion circuit for converting an analog signal into a digital signal, and more particularly to improvement of an inexpensive, high speed and highly accurate A / D conversion circuit.

【0002】[0002]

【従来の技術】従来の、高速かつ高精度なA/D変換器
の構成を図2に示す。同図において、21、22はとも
にオペアンプで、それぞれゲインの異なるものである。
23、24はアナログ入力信号の大きさに応じてオペア
ンプ21、22のどちらかを選択してA/D変換器25
に接続するスイッチ、25は接続されたオペアンプのア
ナグロ出力をデジタル変換するA/D変換器である。い
ま、アナログ入力信号があると、その大きさを図示して
ないレベル検出手段によって検出し、入力の大きさに応
じてゲインの異なったオペアンプ21又は22をスイッ
チ23又は24によってA/D変換器25に切換接続
し、A/D変換していた。
2. Description of the Related Art FIG. 2 shows the structure of a conventional high-speed and highly accurate A / D converter. In the figure, reference numerals 21 and 22 are both operational amplifiers having different gains.
23 and 24 select either the operational amplifier 21 or 22 according to the size of the analog input signal and select the A / D converter 25.
A switch 25 connected to the input terminal 25 is an A / D converter that digitally converts the analog output of the connected operational amplifier. Now, if there is an analog input signal, its magnitude is detected by a level detecting means (not shown), and an operational amplifier 21 or 22 having a different gain according to the magnitude of the input is switched to an A / D converter by a switch 23 or 24. 25 was switched and connected, and A / D conversion was performed.

【0003】[0003]

【発明が解決しようとする課題】ところが従来技術で
は、入力の大きさを判断し別の入力を選択しないといけ
ないので変換時間がかかり、また入力を切換えた所がリ
ニアにならないという問題があった。本発明は、入力を
切換えることなく、高速で高精度なA/D変換器を提供
することを目的とする。
However, in the prior art, there is a problem that it takes time for conversion because it is necessary to judge the size of the input and select another input, and the place where the input is switched is not linear. . It is an object of the present invention to provide a high speed and highly accurate A / D converter without switching the input.

【0004】[0004]

【課題を解決するための手段】上記課題を解決するた
め、本発明は、アナログ入力信号とD/A変換器の出力
信号との差信号を出力するオペアンプと、該オペアンプ
の出力に並列接続されたA/D変換器およびコンパレー
タと、前記オペアンプの出力の極性に応じて出力する前
記コンパレータによってアップ・ダウン動作が切替わっ
てクロックパルスをカウントするアップ・ダウンカウン
タと、該アップ・ダウンカウンタの出力をアナログ信号
に変換して前記オペアンプに出力するD/A変換器とか
ら成り、前記A/D変換器およびアップ・ダウンカウン
タからデジタル出力を得るものである。これは高速で安
価なD/A変換器とA/D変換器とを組合せ、上位デー
タをD/A変換器とカウンタで構成し、そのアナログ量
をコンパレータで比較し、また下位データ分はA/D変
換器にて量子化する。
In order to solve the above-mentioned problems, the present invention relates to an operational amplifier for outputting a difference signal between an analog input signal and an output signal of a D / A converter, and an operational amplifier connected in parallel to the output of the operational amplifier. And an A / D converter and a comparator, and an up / down counter that counts clock pulses by switching up / down operations by the comparator that outputs according to the polarity of the output of the operational amplifier, and an output of the up / down counter Is converted into an analog signal and output to the operational amplifier, and a digital output is obtained from the A / D converter and the up / down counter. This is a combination of a high-speed and inexpensive D / A converter and an A / D converter, the upper data is composed of a D / A converter and a counter, the analog amount of which is compared by a comparator, and the lower data is A Quantize with the / D converter.

【0005】上記手段により従来技術のように入力を切
換えることなく、高速で精度の良いA/D変換回路を構
成することが出来る。
With the above means, a high-speed and accurate A / D conversion circuit can be constructed without switching the input as in the prior art.

【0006】[0006]

【作用】本発明の構成によれば、オペアンプ1、コンパ
レータ2、アップダウンカウンタ4およびD/A変換器
5から成る閉ループはアナログ入力信号をA/D変換し
て上位データを出力し、またA/D変換器3はアナログ
入力信号をA/D変換して下位データを出力するので、
双方の変換出力を合成することによってアナログ入力信
号のデジタル変換出力を得ることができる。
According to the structure of the present invention, the closed loop composed of the operational amplifier 1, the comparator 2, the up / down counter 4 and the D / A converter 5 A / D-converts the analog input signal and outputs the higher-order data. Since the / D converter 3 A / D converts the analog input signal and outputs the lower data,
A digital conversion output of an analog input signal can be obtained by synthesizing both conversion outputs.

【0007】[0007]

【実施例】本発明について図面を参照しながら説明す
る。図1は本発明の実施例の構成を示すブロック図であ
る。同図において、1はアナログ入力信号Vi とD/A
変換器5の出力信号Va との差信号Vd を出力するオペ
アンプ、2はオペアンプ1の出力側にA/D変換器3と
ともに並列接続されたコンパレータで、オペアンプ1の
信号出力Vd の極性を判断する。3はオペアンプ1の信
号出力Vd をデジタル変換して出力をする下位桁のA/
D変換器である。4はオペアンプ1の信号出力Vd の極
性に応じて出力Vc するコンパレータ2の異なる出力レ
ベルによってアップ・ダウン動作が切替わってクロック
パルスをカウントし、出力Vo をする上位桁のアップ・
ダウンカウンタ、5はアップ・ダウンカウンタ4の出力
o をアナログ信号Va に変換して前記オペアンプ1に
帰還出力するD/A変換器である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, 1 is an analog input signal V i and D / A
An operational amplifier 2 that outputs a difference signal V d from the output signal V a of the converter 5 is a comparator that is connected in parallel with the A / D converter 3 on the output side of the operational amplifier 1, and the polarity of the signal output V d of the operational amplifier 1 To judge. 3 is the lower digit A / which digitally converts the signal output V d of the operational amplifier 1 and outputs it.
It is a D converter. Reference numeral 4 indicates up / down operation switched by different output levels of the comparator 2 that outputs V c according to the polarity of the signal output V d of the operational amplifier 1, counts clock pulses, and outputs the output V o.
Down counter 5 is D / A converter for feeding back the output to the operational amplifier 1 converts the output V o of the up-down counter 4 to an analog signal V a.

【0008】以上のように構成された回路について、そ
の動作を説明する。オペアンプ1は入力のアナログ信号
i とD/A変換器5の出力Va の差をそのまま出力V
d する。そして、その差がある時はコンパレータ2は反
転して出力するので、それをカウンタ4のアップ・ダウ
ン信号として入力する。カウンタがアップするとデータ
が1つ上がり、D/A変換器の出力も大きくなりオペア
ンプ1の差出力Vd を減じる。このようにして、オペア
ンプ1からD/A変換器5迄のループは平衡状態にな
り、カウンタ4の出力Va を用いて上位データとする。
カウンタ4の最下位桁よりさらに細かい分解能について
はA/D変換器3により得て下位データとする。そし
て、上位データと下位データとを合成して求めるデジタ
ル値とすればよい。
The operation of the circuit configured as described above will be described. The operational amplifier 1 outputs the difference between the input analog signal V i and the output V a of the D / A converter 5 as it is to output V
d . When there is a difference, the comparator 2 inverts and outputs, so that it is input as the up / down signal of the counter 4. When the counter is incremented, the data is incremented by 1, the output of the D / A converter is also increased, and the differential output V d of the operational amplifier 1 is reduced. In this way, the loop from the operational amplifier 1 to the D / A converter 5 is in a balanced state, and the output V a of the counter 4 is used as upper data.
A resolution finer than the least significant digit of the counter 4 is obtained by the A / D converter 3 and used as lower data. Then, the digital value may be obtained by combining the upper data and the lower data.

【0009】いまD/A変換器を8ビット、A/D変換
器を12ビットにすると20ビット相当のA/D変換器
となり高精度のA/D変換器とすることができる。また
A/D変換器3とD/A変換器5の変換誤差は既知の適
当な入力信号を印加して補正し、さらに精度を上げるこ
とができる。
If the D / A converter is 8 bits and the A / D converter is 12 bits, an A / D converter corresponding to 20 bits can be obtained and a high precision A / D converter can be obtained. Further, the conversion error of the A / D converter 3 and the D / A converter 5 can be corrected by applying a known appropriate input signal to further improve the accuracy.

【0010】[0010]

【発明の効果】以上述べたように、本発明によれば、入
力を切換えることがないので、変換時間が短く簡単な回
路で安価に精度の良いA/D変換器を構成することがで
きる。
As described above, according to the present invention, since the input is not switched, it is possible to construct an A / D converter with high accuracy at a low cost with a simple circuit having a short conversion time.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の構成を示すブロック図FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

【図2】従来技術の構成を示すブロック図FIG. 2 is a block diagram showing a configuration of a conventional technique.

【符号の説明】[Explanation of symbols]

1 オペアンプ 2 コンパレータ 3 A/D変換器 4 アップダウンカウンタ 5 D/A変換器 21、22 オペアンプ 23、24 スイッチ 25 A/D変換器 DESCRIPTION OF SYMBOLS 1 operational amplifier 2 comparator 3 A / D converter 4 up / down counter 5 D / A converter 21, 22 operational amplifier 23, 24 switch 25 A / D converter

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 アナログ入力信号とD/A変換器の出力
信号との差信号を出力するオペアンプと、該オペアンプ
の出力に並列接続されたA/D変換器およびコンパレー
タと、前記オペアンプの出力の極性に応じて出力する前
記コンパレータによってアップ・ダウン動作が切替わっ
てクロックパルスをカウントするアップ・ダウンカウン
タと、該アップ・ダウンカウンタの出力をアナログ信号
に変換して前記オペアンプに出力するD/A変換器とか
ら成り、前記A/D変換器およびアップ・ダウンカウン
タからデジタル出力を得ることを特徴とするA/D変換
回路。
1. An operational amplifier for outputting a difference signal between an analog input signal and an output signal of a D / A converter, an A / D converter and a comparator connected in parallel to the output of the operational amplifier, and an output of the operational amplifier. An up / down counter that counts clock pulses by switching up / down operations by the comparator that outputs according to polarity, and a D / A that converts the output of the up / down counter into an analog signal and outputs the analog signal to the operational amplifier. An A / D conversion circuit comprising a converter and obtaining a digital output from the A / D converter and an up / down counter.
JP23568395A 1995-09-13 1995-09-13 A/d converting circuit Pending JPH0983363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23568395A JPH0983363A (en) 1995-09-13 1995-09-13 A/d converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23568395A JPH0983363A (en) 1995-09-13 1995-09-13 A/d converting circuit

Publications (1)

Publication Number Publication Date
JPH0983363A true JPH0983363A (en) 1997-03-28

Family

ID=16989668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23568395A Pending JPH0983363A (en) 1995-09-13 1995-09-13 A/d converting circuit

Country Status (1)

Country Link
JP (1) JPH0983363A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004102167A1 (en) * 2003-05-15 2004-11-25 Niles Co., Ltd. Rain sensor-use signal detection circuit and signal detection method
KR101136982B1 (en) * 2009-06-29 2012-04-19 에스케이하이닉스 주식회사 Semiconductor integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004102167A1 (en) * 2003-05-15 2004-11-25 Niles Co., Ltd. Rain sensor-use signal detection circuit and signal detection method
KR101136982B1 (en) * 2009-06-29 2012-04-19 에스케이하이닉스 주식회사 Semiconductor integrated circuit
US8169258B2 (en) 2009-06-29 2012-05-01 Hynix Semiconductor Inc. Semiconductor integrated circuit

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