JPS6342524A - System for setting operation mode of logic circuit block - Google Patents

Abstract

PURPOSE:To improve the reliability of a logic circuit operation against the disturbance such as a power noise by adding a timing pulse generating circuit to periodically set contents again to a latch register in a logic circuit block. CONSTITUTION:The first timing pulse CL1 of a timing pulse generating circuit 6 is inputted to the terminal CLK of a latching register 5 and the terminal LD of a shifting register 3, and a second timing pulse CL2 is inputted to the terminal CLK of a shifting register 4 and an inverter 7 and is inputted to the terminal CLK of the shifting register 3. The parallel output from the shifting register 4 is inputted to the latching register 5 is a logic circuit block 8 in accordance with a first timing pulse to update data held in the latching register 5 till then. Since the state of the latching register 5 is always updated, operation mode setting information is automatically set again after a certain time even if the contents of the latching register 5 are broken by the disturbance such as the power noise.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a logic circuit block operation mode setting method,
In particular, the present invention relates to a logic block operation mode setting method that serially transfers and sets operation mode setting information to logic circuit blocks.

Conventional technology] Conventionally, in the logic circuit block operation mode setting method for large-scale integrated circuits (hereinafter referred to as L and SI), etc., it is only necessary to set the states of the required number of modes due to the limited number of input/output terminals of the LSI. If the number of input terminals for LS I [ There is one that converts the data into serial data synchronized with the clock from 1 and inputs it to the LSI.

Inside the LSI, this serial information is converted back into parallel data using a serial input parallel output conversion circuit (hereinafter referred to as an S-P conversion circuit), so that the input section of the p-s conversion circuit provided outside the LSI is converted into parallel data. You can get the same condition as .

As a result, even when the number of usage modes increases and the amount of information to be set increases because the LSI has more degrees of freedom, the LSI
The number of input/output terminals that must be prepared by I can be reduced as much as possible.

(Problems to be Solved by the Invention) In the conventional logic circuit block operation mode setting method described above, data is set only at the time of initial setting. If the mode setting information is destroyed by a disturbance such as power supply noise, there is a drawback that recovery is impossible and operation is not guaranteed until reinitialization is performed.

An object of the present invention is to provide a logic circuit block operation mode setting method that allows operation mode setting information to be reset periodically.

Means for Solving the Problems] The logic circuit block operation mode setting method of the present invention provides a first timing pulse having a predetermined period and a first timing pulse that occurs with a predetermined period between the pulses of the first timing pulse. a timing pulse generation circuit that generates a second timing pulse; and a timing pulse generation circuit that is provided outside the logic circuit block and writes data from a parallel data input means in response to the first timing pulse and writes data in response to the second timing pulse. a parallel input serial output conversion circuit that serially outputs the input data; and a parallel input serial output conversion circuit provided inside the logic circuit block that writes the data from the parallel input serial output conversion circuit in parallel in response to the second timing pulse. A serial input parallel output conversion circuit for outputting, and a parallel output from the serial input parallel output conversion circuit provided within the logic circuit block according to the first timing pulse and held before that input. It is configured to include a holding circuit that updates data.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

As shown in FIG. 1, switch group 1 is combined with resistor group 2 to constitute parallel data input means, and is connected to parallel input terminals A, B to H of shift register 3 as a p-s conversion circuit.

The final stage output terminal Qu of the shift register 3 is connected to the input terminal Sl of a shift I register 4 as an SP conversion circuit provided inside the logic circuit block 8, and its parallel output terminals QA, Qn to QH are the input terminals of the latch register 5 as a holding circuit. , DI to D7. However, in this embodiment, the mode setting information is 8 bits wide.

A clock CL as the first timing pulse of the timing pulse generation circuit 6 is input to the latch clock input terminal CLK of the latch register 5 and the parallel data load control input terminal LD of the shift register 3, and when timing j<
The clock CL2 as the second timing pulse of the pulse generating circuit 6 is inputted to the shift clock input terminals CLK of the shift 1 to register 4 and the input terminal of the inverter 7,
The output of the inverter is input to the shift 1 clock input terminal CLK of the shift register 3.

FIG. 2 is a timing diagram of the clock from the timing pulse generation circuit for explaining the operation of the embodiment shown in FIG.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

At time 1 in FIG. 2, the clock CL1 output from the timing pulse generation circuit 6 is supplied to the shift register 3, and the operation mode setting information set by the switch group 1 and the resistor group 2 is sent in parallel to the shift register 3. is input.

The operation mode setting information is serially transferred to the shift register 4 in the logic circuit block 8 by the clock CL2 output from the timing pulse generation circuit 6 during time t2 to time t3. When the information transfer is completed, the parallel output terminals QA to QI+ of the shift register 4
The same data as the operation mode setting information set to the parallel input terminals A to I of the shift register 3 is outputted to the parallel input terminals A to I of the shift register 3.Next, at time t, 4, the clock outputted from the timing pulse generation circuit 6 CL becomes the input terminal of the latch register 5. , Dl-D7 maintain the same level as the parallel output terminals QA-Q8 of the shift register 4, and are simultaneously output to the output terminals Qo, Q+-Q7.

At the same time, at time t4, the shift register 3 receives the operation mode setting information set by the switch group 1 and the resistor group 2 again in parallel.

After time t5, the state of the latch register 5 is constantly updated by repeating the above-mentioned operation. Operation mode setting information is set again.

〔Effect of the invention〕

As explained above, the logic circuit block operation mode setting method of the present invention adds the timing pulse generation circuit and periodically resets the latch register in the logic circuit block to prevent the logic circuit from disturbances such as power supply noise. This has the effect of improving operational reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a timing diagram of a clock from a timing pulse generation circuit for explaining the operation of the embodiment shown in the figure.

Claims (1)

[Claims] a timing pulse generation circuit that generates a first timing pulse having a predetermined period and a second timing pulse that is generated with a predetermined period between the pulses of the first timing pulse; and a timing pulse generation circuit provided outside the logic circuit block. a parallel input serial output conversion circuit for writing data from the parallel data input means in response to the first timing pulse and serially outputting the written data in response to the second timing pulse; a serial input parallel output conversion circuit provided inside the logic circuit block for writing and outputting the data from the parallel input serial output conversion circuit in parallel in response to the second timing pulse; and a holding circuit that inputs the parallel output from the serial input parallel output conversion circuit in response to a timing pulse of the logic circuit block to update previously held data.