JPH1174466A - Clock circuit for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock circuit which can prevent unnecessary electric power consumption. SOLUTION: A clock circuit 10 comprises a hierarchy tree structure including trunk lines 13, 13' supplied with clock pulses from a clock pulse source 11, and a plurality of branch lines 14, 14' connected to the trunk lines 13, 13'. In this structure, the branch line 14 in at least a hierarchy is connected to a lower hierarchy through switching elements 16 (16a, 16b) to transmit a lower hierarchy of the clock pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock circuit for supplying a clock pulse to each part of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, a clock pulse as a synchronous signal is applied to each unit such as a counter or a register comprising a large number of latches, flip-flops and memory elements provided in the semiconductor integrated circuit. A clock circuit for supplying is incorporated.

However, for example, if there is a difference in the wiring length to each part to which the clock pulse is supplied, clock skew, which is a relative shift in clock phase, occurs in the clock pulse supplied to each part of the semiconductor integrated circuit. . Therefore, in order to prevent the occurrence of the clock skew, a hierarchical tree structure including, as a clock circuit, a trunk line receiving supply of a clock pulse from a clock pulse source and a plurality of branch lines connected to the trunk line Has been proposed. According to the clock circuit having the hierarchical tree structure, the operation of each unit is synchronized without generating clock skew by supplying a clock pulse to each unit requiring a synchronous operation in the same hierarchy of the tree structure. be able to.

[0004]

However, in the above-mentioned conventional clock circuit, clock skew is generated for each functional block such as an image processing function section and an audio processing function section in addition to the count timer block. In order to prevent this from happening, the clock circuit is supplied to each unit in each functional block from the branch line for each same hierarchy in the tree structure, regardless of whether the operation of the functional block is in a programmatic pause state, for example. Are constantly supplied with clock pulses.

[0005] Supplying a clock pulse to a functional block whose operation is in a sleep state wastes power. For this reason, the emergence of a clock circuit capable of preventing unnecessary power consumption has been strongly desired.

[0006]

The present invention adopts the following constitution in order to solve the above points. <Structure> The present invention is a clock circuit for supplying a clock pulse from a clock pulse source to each part of a semiconductor integrated circuit, comprising: a trunk line receiving a clock pulse from the clock pulse source; A plurality of branch lines, and the branch lines in at least one layer are connected to the lower layer via a switching element for interrupting transmission of the clock pulse to the lower layer. It is characterized by having been done.

<Operation> In the clock circuit according to the present invention, since the switching element for interrupting the transmission of the clock pulse to the lower layer is provided in the hierarchical tree structure, the switching element controls the clock element. The supply of the clock pulse to the lower layer branch path connected via the switching element can be stopped.

Therefore, by selectively intermittently operating the switching element, the supply of the clock pulse to the functional block whose operation is at rest is suspended, and the clock pulse is continuously supplied selectively to the other functional blocks. Therefore, unnecessary power consumption can be prevented.

The switching element can be provided on each of the branch lines of a certain hierarchy, so that, for example, the switching element can be inserted between the first hierarchy and the second hierarchy below it. it can.
By inserting the switching element, it is possible to control the supply of all the clock pulses in the lower layers including the second layer.

[0010] The switching element can be constituted by an AND logic circuit that outputs a clock pulse input to the other input terminal to an output terminal in response to input of an enable signal to one input terminal. It is desirable to add a driver function to the AND logic circuit to adjust the waveform of the output signal and amplify the output signal.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. <Example> FIG. 1 shows an example of a clock circuit according to the present invention. The clock circuit 10 according to the present invention supplies a clock pulse as a synchronous signal to each unit such as a counter or a register including a latch, a flip-flop and a memory element of a semiconductor integrated circuit (not shown). It is provided in a semiconductor integrated circuit.

The clock circuit 10 includes a trunk line 13 connected to the clock pulse generation source 11 via a connection line 12 and a crossing of the trunk line 13 so as to receive a clock pulse from the clock pulse generation source 11. And each has a parallel branch line 14 connected to the trunk line. A conventionally well-known driver 15 for adjusting the rounding of the waveform of the clock pulse and amplifying the output signal is inserted into the connection line 12. The trunk line 13 and the branch line 14 connected to the trunk line constitute a first hierarchy.

At both ends of each of the branch lines 14 protruding from both sides of the trunk line 13, each of the trunk lines 13 ′ constituting the second hierarchy and intersecting the trunk line via switching elements 16. The branch lines 14 'which are arranged at the same time and are respectively connected to the trunk lines 13' are connected so as to form respective branch paths for the branch lines 14 of the first hierarchy. Therefore, in the illustrated example, the first hierarchy composed of one trunk line 13 and a plurality of branch lines 14 and the second hierarchy composed of a plurality of trunk lines 13 'and a plurality of branch lines 14' are each composed of a switching element 16 , A tree structure of a total of two layers is formed.

Each branch line 14 'is connected to a clock input terminal of a flip-flop, for example, which constitutes each functional block of the semiconductor integrated circuit (not shown).

In the example shown, each switching element 16
(16a, 16b) is composed of an AND logic circuit having two input terminals and one output terminal. The AND logic circuits 16 are arranged in two series, corresponding to both ends of the branch line 14 of the first hierarchy.

Each of the AND logic circuits 16a arranged in the first series located on the left side in the figure has one input terminal connected in parallel to the first enable signal terminal 17a. The other input terminal of the AND logic circuit 16a is connected to one end of each corresponding branch line 14. Further, the output terminal of each AND logic circuit 16a is connected to each corresponding trunk line 13 'in the second hierarchy.

In the AND logic circuits 16b arranged in the second series on the right side in the drawing, one input terminal is connected in parallel to the second enable signal terminal 17b. The other input terminal of the AND logic circuit 16b is connected to the other end of each corresponding branch line 14. Further, the output terminal of each AND logic circuit 16b is connected to the corresponding trunk line 1 of the second hierarchy.
3 '.

Each AND logic circuit 16 outputs a signal to its output terminal in response to a signal input to two input terminals. Therefore, the clock pulse from the clock pulse generation source 11 is transmitted through the trunk line 13 and the branch line 14,
By controlling an enable signal input to the one input terminal in a state where the clock signal is input to the other input terminal of each AND logic circuit 16, a clock pulse is output from the output terminal in accordance with the enable signal. be able to.

In the example shown in the figure, the enable signal can be individually controlled by two systems of enable signal terminals 17a and 17b. Therefore, each enable system is connected to the output terminal of the AND logic circuit 16a for each system. It is possible to individually control the supply of clock pulses to the first series of functional parts and the second series of functional parts connected to the output terminal of the AND logic circuit 16b.

Thus, by controlling the enable signal to the enable signal terminal 17, the supply of the clock pulse to the functional part connected in the first or second series can be selectively performed, and an unnecessary clock can be supplied. Power consumption in the line can be prevented.

It is desirable for each AND logic circuit 16 to have a well-known driver function for adjusting the waveform of the output signal and thereby amplifying the output.

An application example according to the output control method of each enable signal of the clock circuit 10 shown in FIG. 1 will be described below. The application example shown in FIG. 2 is a case where there is a master-slave relationship between the functional block 18a connected to the first stream and the functional block 18b connected to the second stream. As the master-slave relationship, for example, there is an example of a notebook personal computer and a PCI card used therein.

The function block 18a on the main body side, which is a notebook personal computer, always operates. However, for example, a sub-function block 1 such as a PCI bridge chip for a PCI card is used.
8b does not operate until there is an operation request from the main function block 18a. In such an example, as shown in FIG.
Enable signal terminal 17 for main function block 18a
To a, an enable signal is always input when the personal computer is driven. On the other hand, the one input terminal of each AND logic circuit 16b in the second series for the slave function block 18b, that is, the enable signal input terminal is connected via an enable signal line 17b extending from the main function block 18a.
An enable signal is input.

Therefore, in the example shown in FIG. 2, the main function block 18a controls the supply of the clock pulse to the sub function block 18b.

The example shown in FIG.
Monitors the operation of each of the functional blocks 18 and 18 'on the monitor line 2.
Monitoring is performed intensively by a monitor signal input through "0". In response to the monitoring information, the power management block 19 selectively supplies clock pulses to the functional blocks 18 and / or 18 'that require the clock pulses, and provides the AND logic circuit via enable signal lines 17a and 17b. 16 is operated.

The example shown in FIG.
The software supplies the clock pulses to the functional blocks 18 and 18 'in a software manner in accordance with the program stored in. By writing the program of the power management register 21 from outside, the power management register 21 controls the supply of the clock pulse to each of the functional blocks 18a and 18 'according to the program.
The AND logic circuit 16 (16a and 16b) is operated via the enable signal lines 17a and 17b.

In the example shown in FIG. 5, a control signal is input to a decoder 23 having a control input terminal 22.
Through each of the first and second series of AND logic circuits 1
It controls the input of enable signals to 6a and 16b.

FIG. 6 shows a modification of the switching element according to the present invention. In the switching element 24 shown in FIG.
A large number of AND logic circuits 16 are collectively arranged.
Numerous enable signal input terminals Enb0 to Enb are connected to the one input terminal of each AND logic circuit 16, respectively. The other input terminal of each AND logic circuit 16 is connected to a clock pulse generation source. 11 are connected in parallel to the clock pulse input terminal Cin.
In the illustrated example, a driver 25 is inserted in each AND logic circuit 16 in series, and the output terminal of each driver 25 has a corresponding clock output terminal Cout1-mout.
It is connected to the.

According to the switching element 24, the clock driver 24 having one input, multiple enable inputs and multiple outputs is formed. By using the clock driver 24, the configuration of the branch path in the multilayer hierarchical clock circuit is simplified. Can be achieved.

In the above description, the clock circuit according to the present invention has been described as an example of a two-layer structure. However, the present invention can be applied to a multi-layer structure.

[0031]

According to the present invention, as described above, by controlling the switching elements provided in the hierarchical tree structure, the clock pulse to the lower hierarchical branch path connected via the switching elements is controlled. The supply of clock pulses to the function blocks whose operation is in a halt state can be stopped, and the supply of clock pulses to the other function blocks can be continued selectively. Thus, unnecessary power consumption can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram schematically showing a specific example of a clock circuit according to the present invention.

FIG. 2 is a circuit diagram similar to FIG. 1, illustrating a first application example of the clock circuit according to the present invention.

FIG. 3 is a circuit diagram similar to FIG. 1, showing a second application example of the clock circuit according to the present invention.

FIG. 4 is a circuit diagram similar to FIG. 1, showing a third application example of the clock circuit according to the present invention.

FIG. 5 is a circuit diagram similar to FIG. 1, showing a fourth application example of the clock circuit according to the present invention.

FIG. 6 is a circuit diagram showing a modified example of the switching element according to the present invention.

[Explanation of symbols]

Reference Signs List 10 clock circuit 11 clock pulse generation source 13, 13 'trunk line 14, 14' branch line 16 (16a, 16b), 24 (AND logic circuit) switching element

Claims (4)

[Claims] 1. A clock circuit for supplying a clock pulse from a clock pulse source to each part of a semiconductor integrated circuit, comprising: a trunk line receiving a clock pulse from the clock pulse source; and a trunk circuit connected to the trunk line. A plurality of branch lines, wherein the branch lines in at least one hierarchy are connected to the lower hierarchy via a switching element for interrupting transmission of clock pulses to the lower hierarchy. A clock circuit for a semiconductor integrated circuit, comprising: 2. The clock circuit according to claim 1, wherein the switching element is provided in each of the branch lines of a certain hierarchy. 3. The clock circuit according to claim 1, wherein the switching element is an AND logic circuit that outputs a clock pulse input to the other input terminal to an output terminal in response to input of an enable signal to one input terminal. 4. The clock circuit according to claim 3, wherein the AND logic circuit has a driver function for adjusting the waveform of the output signal and amplifying the output signal.