KR100357426B1 - Clock circuit suitable for sequential control system with multifunction - Google Patents

Abstract

A clock circuit having a multilayer structure according to the present invention includes a clock pulse generator terminal, a first layer trunk line connected to the clock pulse generator, and a plurality of first layers each connected to the first layer trunk line. A branch line, a plurality of second layer branch lines each connected to one of the plurality of second layer trunk lines, a plurality of trunk lines of the upper layer and a plurality of branch lines of the upper layer, similar to the above And a switching element provided between a trunk line according to one selected from the plurality of branch lines and the trunk line according to one selected from the plurality of branch lines.

Description

Clock circuit suitable for sequential control system with multifunction

The present invention relates to an improvement of a clock circuit suitable for a sequential control system having a multifunction. In particular, the present invention relates to an improvement designed to reduce power consumption by a clock circuit having a multilayer structure.

A sequential regulation system, consisting of a combination of each part controlled according to a sequential instruction such as a counter, a register, a memory, a latch, a flip-flop circuit, each of which operates according to a clock pulse or a plurality of clock pulses, There is a need for a clock circuit that generates and supplies a series of clock pulses with regular time intervals between them. In particular, in a synchronous system, the uniformity of a plurality of clock pulses has a significant meaning. That is, clock pulses should be given to each terminal at the same time or exactly at the same time.

However, since the resistance for each of the circuit constants, particularly the clock pulse transmission circuits, is not necessarily uniform, for all clock pulse transmission circuits, in particular, the sequential control system has a large scale, so that the sequential control system requires a constant clock signal. If the destination unit is required, it is not easy to make the clock pulse transmission period uniform. This problem is even worse for sequential control systems with multifunction. As a result, in the case as described above, each clock pulse does not necessarily arrive at each destination unit at the same time. As such, the phenomenon that each of the clock pulses arrive at each destination unit with a time difference is called a clock skew. As illustrated in FIG. 1, a clock circuit having a multilayer structure in which a clock circuit is formed of a plurality of layers each configured by a combination of a trunk line and a plurality of branch lines is developed to prevent the occurrence of such clock skew. Referring to FIG. 1, the first tier consists of one trunk line 1 and ten branch lines 2, and the second tier consists of one trunk line 1 ′ and five branch lines 2 ′. It consists of a plurality of combinations. Since all functional units requiring clock pulses simultaneously can be designed to follow the same layer, the occurrence of clock skew can be prevented.

However, a clock pulse circuit having a multilayer structure according to the related art is a plurality of units necessary for some units to perform a specific class or a specific function regardless of whether some units actually require a clock pulse for a certain period of time. Irrespective of belonging to the group consisting of, it is configured to supply clock pulses to all units requiring such a clock pulse.

The supply of clock pulses in this manner requires a little power consumption, of course. As for the small clock pulse circuit, the power consumption used by the system in which the clock pulses are supplied to all destination units is not a problem. However, this becomes a problem when the clock pulse circuit is a large clock pulse circuit.

After all, it is an object of the present invention to provide a clock pulse circuit having a multi-layer structure with little power consumption.

1 is a circuit diagram of a clock pulse circuit having a multilayer structure according to the prior art;

2 is a circuit diagram of a clock pulse circuit having a multilayer structure according to a first embodiment of the present invention;

3 is a circuit diagram of a clock pulse circuit having a multilayer structure according to a second embodiment of the present invention;

4 is a circuit diagram of a clock pulse circuit having a multilayer structure according to a third embodiment of the present invention;

5 is a circuit diagram of a clock pulse circuit having a multilayer structure according to a fourth embodiment of the present invention;

6 is a circuit diagram of a clock pulse circuit having a multilayer structure according to a fifth embodiment of the present invention;

7 is a circuit diagram of an interface that can be used as a first layer circuit bonded to each of the clock circuits according to the present invention.

Explanation of symbols on the main parts of the drawings

11: terminal for receiving clock signal 13: trunk layer 1st floor

13 ': second floor trunk line 14: first floor branch line

14 ': second floor trunk line 15: driver

16a, 16b: AND circuit 17a, 17b: enable signal terminal

18a: master block 18b: slave block

19,21: Power Management Register

In order to achieve the above object, a clock pulse circuit having a multilayer structure according to the present invention,

A clock pulse generator terminal,

A first layer trunk line connected to said clock pulse generator;

A plurality of first floor branch lines, each of which is connected to the first floor trunk line;

A plurality of second layer branch lines each connected to one of the plurality of second layer trunk lines,

A plurality of combinations consisting of a plurality of trunk lines of the layer and a plurality of branch lines of the upper layer, each of which is configured in a manner similar to the above

A switching element is provided between one selected from the plurality of branch lines and a trunk line according to one selected from the plurality of branch lines.

In the clock pulse circuit having the multilayer structure, an AND circuit activated by an enable signal given by an external unit of the circuit and a clock pulse may be used as the switching element.

In the above-described clock pulse circuit having a multilayer structure, in which the switching circuit is an AND circuit activated by an enable signal given by an external unit of the circuit and a clock pulse, the leading edge of the clock pulse given to the AND circuit is steeply raised. A driver circuit formed at the leading edge can be provided.

The above-described clock pulse circuit having a multilayer structure can be used in a sequential control system having a multifunction.

The invention will now be described in more detail with reference to the accompanying drawings, along with various features and advantages of the invention.

First embodiment

A multi-layered clock having a first layer consisting of one trunk line and ten branch lines and a second layer consisting of ten trunk lines and 40 branch lines, the second layer being divided into two groups. Pulse circuit.

Referring to FIG. 2, a clock pulse circuit having a multilayer structure according to a first embodiment of the present invention includes a terminal 11 and a driver 15 for receiving a clock signal generated by a clock pulse generator (not shown). A first floor trunk line 13 connected to a clock pulse generator (not shown), ten first floor branch lines 14 connected to the first floor trunk line 13, respectively, An input line connected to one of the first layer branch lines 14, another input line connected to the enable signal terminals 17a and 17b to receive the enable signal, and a corresponding second layer trunk line. Ten AND circuits 16a, 16b having output lines connected to one of ten second layer trunk lines 13 'connected to ten second layer branch lines 14' connected to 13 '. ). The function of the above-described driver 15 is to make the shape of the leading edge of the clock pulse uniform and make it into a steep staircase shape.

Each branch line 14 'of the second layer is connected to a group (not shown) of a plurality of units requiring clock pulses at the same period. Each of these units (not shown) is a combination of a plurality of elements (not shown) that require clock pulses at the same period, such as a counter, register, memory, latch, flip-flop, and the like.

The AND circuits 16a and 16b also allow the clock pulses to pass through themselves when the enable signal is given. In Fig. 2, when the enable signal is supplied to the enable signal receiving terminal 17a, all AND circuits 16a on the left side of the trunk line 13 operate simultaneously, and the enable signal is an enable signal. When supplied to the receiving terminal 17b, all AND circuits 16b placed on the right side of the trunk line 13 operate simultaneously. As a result, all the second layer clock circuits on the left side of the trunk line 13 pass clock signals simultaneously, while the second layer clock circuits on the right side of the trunk line 13 pass clock signals simultaneously.

This means that the group of the second layer clock circuits in which the clock circuit according to the first embodiment of the present invention is operating can be selected. In other words, the clock circuit existing in the unselected state uses no power at all and can maintain it in the standby state.

Second embodiment

A first layer consisting of one trunk line and ten branch lines, and a second layer consisting of ten trunk lines and 40 branch lines, divided into two groups, wherein the first five of the second layers And a remaining five blocks of the second layer are connected to a slave block that operates in accordance with a command generated by the master block.

Referring to FIG. 3, the first five layers of the second layer are connected to the master block 18a to supply clock pulses to the master block, and the remaining five clock pulses are generated only when the master block 18a commands. It is connected to the supplied slave block 18b. An example of such a combination of the master block and the slave block is a combination of a notebook type personal computer and a peripheral card interface. Although the master block 18a, which is a notebook-type personal computer in this case, operates permanently, in this case, the slave block 18b, which is a plurality of card interfaces that are peripheral devices, is instructed by the master block to start operation. Will only work if given. In the present embodiment, the enable signal is permanently given to the master block as long as the personal computer operates, but the enable signal from the master block 18a is given to the AND circuit 16b of the slave block 18b.

As a result, power consumption is reduced for the clock pulse circuit having the multilayer structure according to the second embodiment of the present invention.

Third embodiment

A first layer consisting of one trunk line and ten branch lines, and a second layer consisting of ten trunk lines and 40 branch lines and divided into two groups, the monitor signal transmission line 20 A multi-layer clock pulse circuit having power management registers installed to manage each functional block 18 or 18 'in accordance with information given by the transmitted monitor signal.

Referring to FIG. 4, a power management register 19 is installed to manage each functional block 18 or 18 'in accordance with information given by the monitor signal transmitted through the monitor signal transmission line 20. The power management register 19 transmits an enable signal through the enable signal terminal 17a or the enable signal terminal 17b to the AND circuit 16a of the first functional block A or the AND circuit of the second functional block B. Output to 16b respectively.

As a result, power consumption for the clock pulse circuit having the multilayer structure according to the third embodiment of the present invention is reduced.

Fourth embodiment

According to the present invention, there is provided a first layer consisting of one trunk line and ten branch lines, and a second layer consisting of ten trunk lines and 40 branch lines and divided into two groups. A clock pulse circuit having a multilayer structure wherein is a computer unit which operates in accordance with a computer program loaded therein.

Referring to FIG. 5, the power management register 21 is a computer unit operating according to a computer program loaded therein, and the power management register 21 is connected through an enable signal terminal 17a or an enable signal terminal 17b. The enable signal is supplied to the AND circuit 16a of the first functional block A or the AND circuit 16b of the second functional block B, respectively.

As a result, power consumption for the clock pulse circuit having the multilayer structure according to the fourth embodiment of the present invention is reduced.

Fifth Embodiment

A first layer consisting of one trunk line and ten branch lines, and a second layer consisting of ten trunk lines and 40 branch lines, divided into two groups, finally with block A 18 and block To operate the B 18 ', a decoder (i.e., to supply an enable signal to the AND circuits 16a and 16b through the terminal 17a for the AND circuit 16a and the terminal 17b for the AND circuit 16b). 23) A clock pulse circuit having a multi-layer structure provided.

Referring to FIG. 6, the decoder 23 receives a coded signal through a coded signal receiving terminal 22. After decoding this coded signal, the decoder sends instructions to the AND circuit 16a and the AND circuit 16b through the terminal 17a for the AND circuit 16a and the terminal 17b for the AND circuit 16b, respectively. To operate block A 18 and block B 18 '.

As a result, power consumption for the clock pulse circuit having the multilayer structure according to the fifth embodiment of the present invention is reduced.

Modification of the first layer circuit suitable for the clock circuit of the present invention

According to the invention, it has a multilayer structure, having a first layer consisting of one trunk line and ten branch lines, and a second layer consisting of ten trunk lines and 40 branch lines and divided into two groups. An interface that can replace a first layer circuit applicable to any clock pulse circuit.

Referring to FIG. 7, all AND circuits 16 have a common input terminal 11 for receiving a clock signal from a clock pulse generator (not shown). Each of the AND circuits 16 has a terminal for receiving the enable signals Enb (1) to Enb (k). The output signal of each of the AND circuits 16 is generated from the corresponding output terminals Out 1 to Out k after the shape of the leading edge of each clock pulse is modified by the driver 25.

Application of this interface comprises, according to the invention, a first layer consisting of one trunk line and ten branch lines, and a second layer consisting of ten trunk lines and 40 branch lines and divided into two groups. It is effective to simplify the structure for the first layer circuit of each of the clock pulse circuits having one multilayer structure.

As can be seen from the foregoing, the present invention is directed to a first layer consisting of one trunk line and ten branch lines, a second layer consisting of ten trunk lines and 40 branch lines, divided into two groups. Provided is a clock pulse circuit having a multilayer structure having a layer and almost no power consumption.

Although the present invention has been described with reference to specific embodiments, these embodiments should not be construed as limiting the invention. From the foregoing invention, it is obvious that various modifications of the disclosed embodiments as well as other embodiments of the invention can be made by those skilled in the art to which the invention pertains. Accordingly, the appended claims should be construed to cover such modifications or embodiments as fall within the true scope of the invention.

Claims (8)

A clock pulse generator terminal, A first layer trunk line connected to said clock pulse generator; A plurality of first floor branch lines, each of which is connected to the first floor trunk line; A plurality of second layer branch lines each connected to one of the plurality of second layer trunk lines, Consisting of a plurality of trunk lines of the upper layer and a plurality of branch lines of the upper layer, each having a plurality of combinations configured in a similar manner as described above, And a switching element is provided between one selected from the plurality of branch lines and a trunk line according to one selected from the plurality of branch lines. The method of claim 1, And said switching element comprises a plurality of AND circuits activated by an enable signal given by an external unit of said circuit and a clock pulse. The method of claim 2, A clock pulse circuit having a multi-layer structure, further comprising a driver circuit attached to at least one trunk line to modify the shape of the leading edge of each clock pulse. The method of claim 1, A clock pulse circuit having a multilayer structure, wherein the clock pulse circuit having a multilayer structure is used in a sequential control system. The method of claim 1, At least a portion of the branch line of the first layer circuit is connected to a master block, and the remaining portion of the branch line of the first layer circuit is enabled by the master block before being connected to a slave block. Clock pulse circuit having a multi-layer structure, characterized in that configured to be activated by a signal. The method of claim 2, And a power management register which operates in response to a plurality of blocks and provides an enable signal to each of the plurality of AND circuits, thereby activating each of the plurality of blocks. The method of claim 6, And the power management register is a computer unit operating according to a computer program. The method of claim 1, And a decoder means for decoding an instruction received from the outside and outputting an enable signal to each of the switching circuits.