RU66560U1 - MANAGEMENT DEVICE - Google Patents

Abstract

The proposed utility model relates to automatic control systems and can be used to control complex technical systems for various purposes, mainly with a discrete nature of the technological cycle. The technical task of the proposed utility model is to expand the functionality of the device, as well as the implementation of the mechanism for reassigning the sequence of application of alternative control command codes, which does not require dismantling the device. The device contains two registers, three blocks of AND elements, three memory blocks, a comparison circuit, an address counter, a control unit, a clock generator, an AND element of a device with one inverse input, a block of OR elements, n blocks for generating alternative control command codes, a counter, a decoder devices and priority assignment logic block.

Description

The proposed utility model relates to automatic control systems and can be used to control complex technical systems for various purposes, mainly with a discrete nature of the technological cycle.

Of the known devices of the same purpose, characterized by a combination of features similar to the set of essential features of the proposed utility model, the closest in technical essence is the DEVICE FOR SITUATIONAL MANAGEMENT (USSR author's certificate No. 1278811 G05B 19/18), which is taken as a prototype. This device searches for the equivalence class of the current situation by the characteristic vectors of equivalence classes sequentially retrieved from the memory block and generates a control command code corresponding to the found class at the output. The disadvantage of this device is the appointment for the class of equivalence of situations of a single control command code. Meanwhile, practice shows that, in a number of cases, the same situation on a managed object can be resolved by applying one of several different alternative control command codes. In addition, when applying the required number of such alternative control command codes in series, applying the previous alternative control command code, if it was unable to resolve the current situation, can create the necessary conditions for the effective use of the subsequent alternative control command code, and so on, until the situation allowed. All this is especially true.

when resolving emergency situations (failures) at a managed facility. Since the managed object by its nature is, in general, a complex system, the individual elements of which are interconnected and interdependent, emergency situations arising at this object will usually also have a complex character (for example, a group failure of equipment) . Applying only one control command code in such situations in most cases may not be effective enough. In addition, the disadvantage of the above device is the lack of technical capabilities for such a reassignment of the priority application of alternative control command codes, in which it would not be necessary to dismantle the device. This reduces the functionality of the device and, therefore, significantly narrows the scope of its practical application.

The technical task of the proposed utility model is to expand the functionality of the device, as well as the implementation of the mechanism for reassigning the sequence of application of alternative control command codes, which does not require dismantling the device.

The solution of the technical problem is achieved due to the fact that the device is additionally introduced into the device according to the USSR copyright certificate No. 1278811 G05В 19/18, containing two registers, a block of AND elements, three memory blocks, a comparison circuit, an address counter, a control unit and a clock generator. an AND element of a device with one inverse input, a block of OR elements, a second block of AND elements, n blocks for generating alternative control command codes, a counter, a device decoder, a third block of AND elements, a priority priority logical unit c, wherein the group of outputs of the block of OR elements is connected to the group of inputs of the second register, the first group of inputs of the block of OR elements is connected to the group of outputs of the second

the AND block of elements, the group of inputs of which is connected to the group of outputs of the second memory block, in the block of elements OR the outputs of all elements are combined into a group of outputs of the block, the first inputs of all elements are combined into the first group of inputs of the block, and the second inputs of all elements are combined into the second group of inputs of the block , in the second block of elements AND the outputs of all elements are combined into a group of outputs of the block, the first inputs of all elements are combined into a group of inputs of the block, and the second inputs of all elements are connected to each other and to the control input of this block , the outputs of all blocks of alternative control command generation codes having the same serial numbers are interconnected and connected to the second group of inputs of the OR block of elements, a separate output of the address counter is connected to the control input of the second block of AND elements, the counter reset input and the inverse input of the AND element devices with one inverse input, the direct input of which is connected to the output of the AND element of the control unit and with the sync inputs of the first and second registers, the output of the AND element of the device with one inverse input connected to the counter input of the counter, the group of outputs of which is connected to the group of inputs of the device decoder, n + 1 the output of which is the alarm output of the device, the third block of elements And contains (nxn) elements, has n inputs, n outputs and an input information bus, all AND elements are combined into n groups, n elements in each group, the outputs of all n elements that are part of one group are interconnected and with the corresponding output of the third block of AND elements, the second inputs of all AND elements are combined into an input the information bus of the third block of AND elements, the first inputs of the i-th elements AND of each group (i∈ [1; n]) are connected to each other and with the i-th input of the third block of AND elements, the priority assignment logical block has n! control inputs, the output information bus and contains a decoder, and

each control input is connected to the corresponding input of the decoder, the outputs of which are combined in the output information bus, the output information bus of the priority assignment logical unit being the input information bus for the third block of AND elements, each of the n inputs of the third block of AND elements is connected to the corresponding output of the device decoder, and each of the n outputs of this block is connected to the control input of the corresponding block for generating alternative control command codes.

Functional diagram of the operational control device is presented in figure 1; functional diagram of the control unit - figure 2; functional diagram of the block of elements OR - figure 3; functional diagram of the second block of elements And - figure 4; functional diagram of the third block of elements And - figure 5; a functional diagram of a priority assignment logic block is shown in FIG. 6.

The device (Fig. 1) contains: pos. 1 - first register, pos. 2 - first block of AND elements, pos. 3 - third memory block, pos. 4 - comparison circuit, pos. 5 - first memory block, pos. 6 - address counter, item 7 - second register, item 8 - second memory unit, item 9 - control unit, item 10 - clock generator, item 17 - OR block, item 18 - second block of AND elements , pos.19 - n blocks for generating alternative control command codes, pos.20 - an AND element of a device with one inverse input, pos.21 - a counter, pos.22 - a device decoder, pos.23 - the third block of And elements, pos.24 - logical block assigning priorities.

The control unit 9 (figure 2) contains: position 11 - element OR and position 12 - element And, and also has inputs 13 and 14 and outputs 15 and 16.

The block of elements OR 17 (figure 3) contains m elements OR, and also has two groups of inputs and one group of outputs.

The second block of elements And 18 (figure 4) contains m elements And, and also has a group of inputs, a group of outputs and a control input.

The third block of elements And 23 (figure 5) contains n groups of elements And 30, n elements in each group, has n inputs 26, n outputs 25, input information bus 27.

The priority assignment logic 24 (FIG. 6) has n! control inputs 29, the output information bus 28 and contains a decoder 31, which has n! inputs 33 and (n × n) outputs 32.

The prototype device implements such a search scheme that does not search for a situation code that matches the current one, but a whole equivalence class to which the current situation belongs.

The equivalence class of situations is a set of situations. inducing the same solution R _i (having the same control command code). Class characteristic vectors a pair of vectors h _i and g _i is called such that the relations

where S _j is the binary vector of the jth situation of the class .

The vector h _i (g _i ) contains one in the kth bit if the kth bit of all situation vectors S _j from this class contains one (zero). Then the condition that the current situation belongs to the class is described by the following logical expression:

This condition can be formulated as follows. The situation S _t belongs to the class in the event that the situation code S _t has units in all digits in which units has h _i and does not have units in all those digits in which g _i has units. If for

any pair of classes and (i ≠ j) h _i & h _j = h _j or g _i & g _j = g _j , then the situation class can be uniquely determined from condition (2) without sequential viewing of all situations and a command to the controls is issued immediately.

The circuit of the device operates as follows.

The binary vector (situation code) from the control object is fed to the information inputs of the first register 1. At the time of the search for the previous control command at the input 14 of the control unit 9, a signal appears with the level of the logical unit from the comparison circuit 4, opening the AND element 12 in the control unit 9, and on the trailing edge of the next pulse from the generator 10, the control command code is written from the second memory block 8 to the second register 7 and the current situation code is in the first register 1. If the code class of the current situation matches the class of the situation code recorded on the previous measure, then from the comparison circuit 4 a signal with the level of a logical unit is still received, and the process repeats until the class of the current situation changes. All this time in the second register 7, the previous control command code is stored. When changing the code of the current situation, which changes the class of the situation, the logical unit is removed from the input 14 of the control unit 9, the And 12 element is locked, stopping the recording of information in the first register 1 and second register 7, and on the trailing edge of the signal at the output 15 of the control unit 9 formed with the OR element 11, the contents of the address counter 6 are incremented by one. Then, along the trailing edge of the pulses of the generator 10, which pass through the OR element 11 to the output 15 of the control unit 9, the contents of the address counter continue to increase, th selection information from the first memory unit 5, the second memory unit 8 and the third memory unit 3. In this case, the memory blocks are selected vector h _i, the command code vector R _i and _{f i = (h i ∨g i} ) , respectively. The vector f _{i is} bitwise multiplied by a vector

the current situation S _t in the first block of AND 2 elements, the outputs of which go to the second input of the comparison circuit 4, where the obtained vector is compared with the vector h _i , i.e. definition of a class of a situation in accordance with expression (2). The address counter 6 operates cyclically, providing a sequential selection of all instruction codes R _i and all vectors h _i and f _i . When the vector S _i & (h _i ∨ g _i ) coincides with the vector h _i , a signal is generated with a logic unit level at the output of the comparison circuit 4, which allows writing the code of the command R _i in the second register 7 and writing the code of the new situation in the first register 1 After that the process is repeated.

Implemented the solution of the technical task as follows. Alternative control command codes assigned to the equivalence class of situations identified as emergency are arranged in advance in the sequence of their application in accordance with the selected priorities. With this streamlining, it is taken into account that, first of all, it is rational to apply one of the alternative control command codes that could provide a solution to the current emergency at a lower cost, i.e. by applying more cost-effective and (or) time-consuming means, in comparison with the subsequent alternative code of the control command. At the same time, each subsequent control command code, which is more expensive than the previous one, should be more efficient, i.e. able to resolve the current emergency more likely. The sequential use of alternative control command codes ensures the resolution of the current emergency using any one of the alternatives or gives an alarm signal that the device is not able to resolve the emergency on its own, when the sequential use of all n assigned alternatives did not lead to a positive result . Number of Alternative Codes

control commands assigned to the equivalence class corresponding to emergency situations are selected so that, firstly, to cover the maximum number of alternative ways to resolve them and, secondly, so that in the process of sequential enumeration of alternative control command codes, the device’s operating time for a given performance did not exceed a certain maximum allowable value that can be allocated to resolve the emergency, and is determined by the characteristics of each specific control the property being defunded.

Before an emergency occurs at a managed facility, the logical unit level is constantly maintained at a separate output of address 6 counter. As this output, one of the group of outputs of the address counter 6 is assigned. In the event of an emergency on the managed object, it is identified (classified) by the device and from a separate output of the address counter 6 to the control input of the second block of elements And 18, the input of the reset counter 21 and the inverse input of the element And 20 of the device receives a signal with a logic level of zero. In this case, the second block of elements And 18 is blocked, prohibiting the recording of information from the second block of memory 8 in the second register 7, and the element And 20 of the device is opened, allowing the receipt of clock pulses from the output 16 of the control unit 9 to the counting input of the counter 21. Upon receipt of the first clock pulse to the counting the input of the counter 21 its content is increased by one, while the level of the logical unit is set at the first output of the decoder of the device 22 and after passing through the third block of elements And 23 goes to the control input respectively stvuyuschego block formation of alternative control command codes 19. In this case, formed in the block 19, an alternate control command code through the block elements 17 is supplied to OR input group of second register 7 for overwriting. After dubbing

the first register 1 and second register 7, the control object can be taken out of emergency, which will be identified by the device and the logical unit level will be set on a separate output of address counter 6. In this case, the counter 21 is set to its initial state (reset to zero), the device element And 20 is closed, the level of the logical unit is removed from the first output of the decoder of the device 22, thereby stopping the supply of an alternative control command code from the output of the corresponding alternative control command generation unit 19, and the group of inputs of the second register 7 through the second block of elements AND 18 receives the control command code from the output of the second memory block 8.

If the emergency resolution after applying the first alternative code of the control command has not occurred, the logic zero level at the separate output of the address counter 6 is saved, the second clock pulse is transmitted to the counter input of the counter 21 through the device element And 20 and, in the same way, the second register 7 is rewritten to the second alternative control command code, i.e. the second attempt to remove the control object from the emergency. This continues until an emergency at the control object is resolved, or, if all n alternative codes of the control command are used, but do not resolve the situation, at n + 1 clock cycle of counter 21, a signal with a logic level of n + 1 the output of the decoder of the device 22 will go to the alarm (indication) and provide a signal that the device is not able to independently resolve the emergency. When an alarm is given, the operation of the control object can be automatically stopped, for example, by turning off the power.

Reordering mechanism

alternative control command codes are implemented as follows. In the priority assignment logic 24, the decoder 31 has n! inputs 33 and (n × n) outputs 32. Thus, the number of outputs 32 of the decoder 31 used in the device of different states is n !. To assign priority to the application of alternative codes of the control command in accordance with the selected priorities, a signal with the level of a logical unit is supplied and constantly maintained at one of the control inputs 29 of the priority assignment logic block 24 and is supplied to the corresponding input 33 of the decoder 31. At the same time, at the n outputs 32 of the decoder 31 at the same time a signal appears with the level of a logical unit. From the i-th output of the decoder 31, the signal with the level of the logical unit enters the third block of elements And 23 to the second input of the corresponding element And 30 and opens it, thereby connecting one of the outputs of the decoder of the device 22 to the control input of the corresponding block for generating alternative control command codes 19. The signal of a logical unit simultaneously opens no more than one AND element 30 in each group of AND elements of the third block of AND 23 elements, and at the same time in different groups of AND elements x elements And 30 serial numbers do not match, which ensures the assignment of its priority for each alternative code of the control command.

Thus, the proposed device implements such a mechanism for reassigning the sequence of application of alternative control command codes, which does not require disassembling the device, which significantly expands its functionality.

The alternative control command codes assigned for the equivalence class corresponding to emergency situations are set during the installation (installation) of n blocks into the device

the formation of alternative codes of the control command 19. Each of these blocks, upon receipt of control of the level of a logical unit at its input, issues a corresponding alternative code of the control command to the group of its outputs. As such blocks, as well as decoder 31, combinational logic circuits can be used, the optimization (minimization) of which during development is advisable to be done using Carnot cards. Various microcircuits can be used as the counter 21, for example, K155IE5, and K155ID3 as the decoder of the device 22. Used in the proposed device, the mutual connection circuit of the counter 21 and the decoder of the device 22 is widespread and is used, for example, in electronic music calls, in electronic clocks, timers. The principles for constructing the remaining elements are also well known and are presented in the corresponding reference books. Thus, the technical implementation of the proposed device is not difficult.

The proposed device can be used in the management of complex technical systems mainly with a discrete nature of the technological cycle, for example, production lines, numerically controlled machines and other complex technical automatic control systems.

Claims (1)

An operational control device comprising first and second registers, first, second and third memory blocks, an address counter, a first block of AND elements, a comparison circuit, a control unit and a clock generator, characterized in that it further comprises an AND element of a device with one inverse input , block of OR elements, second block of AND elements, n blocks for generating alternative control command codes, counter, device decoder, third block of AND elements, priority assignment logical block, and the group of outputs and OR elements are connected to the group of inputs of the second register, the first group of inputs of the block of OR elements is connected to the group of outputs of the second block of AND elements, the group of inputs of which is connected to the group of outputs of the second memory block, in the block of OR elements, the outputs of all elements are combined into the group of outputs of the block, the first the inputs of all elements are combined into a first group of block inputs, and the second inputs of all elements are combined into a second group of block inputs, in the second block of elements AND the outputs of all elements are combined into a group of block outputs, the first in the moves of all elements are combined into a group of inputs of the block, and the second inputs of all elements are connected to each other and to the control input of this block, the outputs of all blocks of formation of alternative codes of the control command having the same serial numbers are connected to each other and connected to the second group of inputs of the block of elements OR , a separate output of the address counter is connected to the control input of the second block of AND elements, the counter reset input and to the inverse input of the AND element of the device with one inverse input, the direct input of which is connected with the output of the AND element of the control unit and with the sync inputs of the first and second registers, the output of the And element of the device with one inverse input is connected to the counting input of the counter, the group of outputs of which is connected to the group of inputs of the device decoder, n + 1 the output of which is the alarm output of the device, the third a block of AND elements contains (n × n) AND elements, has n inputs, n outputs and an input information bus, and all AND elements are combined into n groups, n elements in each group, the outputs of all n elements included in one group, are interconnected and with the corresponding output of the third block of AND elements, the second inputs of all elements AND are combined into the input information bus of the third block of AND elements, the first inputs of the i-th AND elements of each group (i∈ [1; n]) are connected between by itself and with the i-th input of the third block of AND elements, the priority assignment logical block has n! control inputs, the output information bus and contains a decoder, each control input connected to a corresponding input of the decoder, the outputs of which are combined into an output information bus, the output information bus of the priority assignment logical unit being the input information bus for the third block of AND elements, each of n inputs the third block of elements And is connected to the corresponding output of the device decoder, and each of the n outputs of this block is connected to the control input correspondingly th block of formation of alternative control command codes.