SU1580373A1 - Device for addressing memory units - Google Patents

Abstract

The invention relates to automation and computing and can be used to form a continuous address field in modular memory systems. The purpose of the invention is to increase the reliability of the device. This is achieved by introducing a block 5 for shutting off the faulty address driver groups. The device contains N address drivers 1, combined into M groups with the number of SJ address drivers in each J-th group, output 2 of the address sample of the I-th memory block, input 3 of the current address, input 4 of the base address, M blocks 5 of the failed groups , input 6 control, input 7 sets the number of address formers in the group. 1 hp ff, 2 ill.

Description

The invention relates to automation and computer engineering and can be used to form a continuous address fields in modular memory systems ₀

The aim of the invention is to increase the reliability of the device.

In Fig. 1 shows a functional · diagram of a device for addressing memory blocks; figure 2 is a functional block diagram of the shutdown of faulty groups of address formers ,,

The device 'contains m groups of address forwarders 1 (each Sj address forwarders), outputs 2 of the i-ro memory block address sample, input 3 of the current address, input 4 of the base address, block 5 for disconnecting faulty groups of address formers, input 6. control, 'input 7 sets the number of address formers in the group.

Block 5 disable malfunctioning groups (Fig, 2) Contains an adder 8, a comparison circuit 9, a D-trigger 10 and a multiplexer 11,

In addition, the driver 1 addresses (figure 1) contains a switch 12, the comparison circuit 13 and the adder 14,

The device can operate in three modes: in the control mode of correct addressing of memory blocks, inside each group of address formers, in the mode of assigning continuous addresses to unconnected memory blocks and in external access mode.

First, the correctness of the addressing of the memory blocks within each group of address formers 1 is checked. At the same time, at the input 6 of the device control, a high level signal is set, which translates the address formers 1 into a single state. After this, the addresses on the first and second information inputs of each block 5 should differ from each other by the amount

S j, t, e “of units 1 by the value of the number of addresses formed in each group, since in the control mode of addressing correctness all memory blocks and all formers. 1 addresses are considered serviceable. If there is a malfunction in the addressing chain of the memory blocks of the group (defect in the address drivers, open or short circuit of the address buses), then the addresses on the first and second information inputs of block 5 differ from each other by an amount that is not equal to S., which causes the output of the comparison circuit 9, a high-level signal is recorded in the D-flip-flop 10 '. There is a unit which, from its direct output, goes to the control input of the multiplexer 11, which leads to the transfer of the code from the first information input of block 5 of the jth group to the first information input of block and 5 (j + lj-th group.

If there are no malfunctions in the addressing circuit, then the codes are transferred from the second information input of block 5 of the jth group to the first information input of block 5 (j + 0th group.

After checking the addressing of the memory blocks within the group and setting the low-level signal at the device control input 7, the device starts operating in the mode of assigning continuous addresses to the suitable memory blocks. At the same time, functional checks are carried out only for those memory blocks that are in disconnected groups of address 1 formers; this. In this case, the switch 12 corresponding to the memory block being checked is set to a single state if the memory block is suitable, and to zero if the memory block is faulty. After checking the last storage unit and setting the desired state of the corresponding switch 12 it is believed that fit all the memory blocks assigned logical _addresses; forming a continuous field, and the device is ready to work in external access mode,

In the external access mode, the current address from the input 3 of the device is supplied simultaneously to the first inputs of all formers 1 of the group address. If the address located on the second input of i-ro of the former 1 addresses and the external address of the address is accessed, the memory block обращение "

Claims (2)

Claim 1. A device for addressing memory blocks containing m groups of address formers, each of which contains Sy address formers (S = 1.2 about <,., 1. <J <m), and the first inputs of the address formers are connected to the input of the current address devices, second input of the first shaper of the address of the first group of the connection, tel framing devices (i = with the input of the base address of the device - $ first --------- ----- --------- -addresses of addresses the outputs of all formations are inputs of the high memory unit I, .. о, η, where η = S, + + + оо »+ Sj + ,,, + S ^), о t l, which means that in order to increase the reliability of the device, w blocks are introduced into it shutdown of faulty groups of address conditioners, the first information input of the first block disconnecting faulty groups of address conditioners connected to the input of the base address of the device, the first information input of the k-th block disconnecting faulty groups of address conditioners (k = 2, ₀₀₁ >) connected to the output (k- 1) of the off block of faulty groups of address formers, respectively, the second information in the course of each j-ro block for disconnecting faulty groups of address formers is connected to the input Sj-ro of the address former of the j-th group, the synchronization input for all blocks for disconnecting faulty groups of address formers is connected to the third inputs of all the address formers and the input 1580373. 6 control of the device, and the second outputs of the address formers from the first to (Я.-1) -th of each group are connected to the second inputs of the formers ₍ address from the second to Sj-th, respectively, the third information input j-ro block off malfunctioning groups of formers the address is connected to the jth input of setting the number of address forwarders in the group, 2. The device according to π, 1, characterized in that the block for disconnecting faulty groups of address formers contains an adder, a comparison circuit, a D-trigger and a multiplexer ·, the first input of the adder connected to the first information input of the block, the second input of the adder connected to the third information input of the unit, the output of the adder is connected to the first input of the comparison circuit, the second input of which is connected to the first information input of the multiplexer · and is the second information input of the unit, the output of the multiplexer is the output of the unit, vlyayuschy multiplexer input coupled to a direct output of D-flip-flop having an information input coupled to an output of the comparison circuit, a clock input connected to the input of block synchronization. Figure 2