UA37651C2 - Network programmable controller - Google Patents

Abstract

The proposed network programmable controller relates to the devices for programmable discrete control of objects that are designed for performing cyclic operations. The controller contains a memory unit for storing the date concerning the object states, a memory unit for storing control instructions, a comparator, and an address counter. The first input of the address counter is used as the first input of the controller. The output of the address counter is used as the first output of the controller and is connected to the address inputs of the memory unit for storing the date concerning the object states and the memory unit for storing control instructions. The information output of the memory unit for storing the date concerning the object states is connected to the first input of the comparator. The second input of the comparator is used as the second input of the controller. The second output of the controller is the first (information) output of the memory unit for storing control instructions. Additionally, the controller contains a memory unit for storing branch instructions, a logic control unit, and an AND logic element. The address input of the memory unit for storing branch instructions is used as the third input of the controller. The first (information) input of the memory unit for storing branch instructions is connected to the first input of the address counter. The second input and the third input of the address counter are connected accordingly to the first output and the second output of the logic control unit. The first input of the logic control unit is connected to the second output of the memory unit for storing branch instructions. The second input and the third input of the logic control unit are connected accordingly to the second output of the memory unit for storing control instructions ant the output of the AND logic element. The first input of the AND logic element is used as the fourth input of the controller. The second input of the AND logic element is connected to the output of the comparator. The present invention allows the hardware of a programmable controller to be simplified.

Description

Description of the invention

The invention belongs to automation, and more precisely to devices for logical control of objects of discrete cyclic action.

The famous programmable logic controller (a.s. 857933 of the USSR, 27.06.79, (505 V 19/18, publ. 23.08.81, Bull.

Mo31), which is a control device of parallel action and contains a counter, a comparator, main and additional memory blocks, a switch and a control block made in the form of two elements | and element NO, and the counter and the main memory block are connected in series, the first output of the main memory block is connected to the 710 output of the device, and the second - to one input of the comparator, the second input of which is connected to the first input of the device, output of the first element | connected to the first input of the counter directly, and the output of the second element AND! - to the second input of the counter through an additional memory block connected by the second input to the third output of the main memory block and one input of the switch, the second input of which is connected to the second input of the device, and the first inputs of both elements | are connected to the output of the comparator, and the second inputs of the first and second AND elements are connected to the output of the switch, respectively, through the NOT element and directly.

Analog provides software control of objects with a deterministic sequence of performed operations, however, it is characterized by two serious disadvantages. The first disadvantage consists in the fact that with the help of this device it is impossible to programmatically control objects with a random sequence of performed operations (the device lacks the necessary blocks and connections between them), the second disadvantage consists in the fact that this device has a specific hardware redundancy.

The closest in terms of features to the proposed invention is a programmable logic controller (a.s. 1302242 USSR, 30.12.85, 5 05 В 19/18, publ. 07.04.97. Byul. Mo13), which contains memory blocks of states and commands, a comparison circuit and an address counter, the first input of which is the first input of the device, the output of the address counter is the first output of the device and is connected to the address inputs of the memory blocks of states and commands, the information c 29 output of the memory block of states is connected to the first the input of the comparison circuit, the second input of which is the second input of the device, the second output of which is the first (informational) output of the command memory block, in which the first drawback of the analog is completely eliminated: the possibility of controlling objects with both deterministic and random sequence of performed operations.

The reasons that prevent the prototype from achieving the expected technical result are the following: when building controller networks based on the prototype, some blocks become inactive (excessive), in addition, the prototype uses the method of analysis of transition conditions, the implementation of which is connected with increased hardware costs. at

The basis of the invention is the task of improving the "network programmable controller by introducing new blocks and connections to it, which provide an economical layout scheme of the controller network, 35 as well as the implementation of the method of analysis of combinations of transition conditions, which requires reduced hardware costs.

The implementation of the given task is achieved by the fact that in the network programmable controller containing state and command memory blocks, a comparison circuit and an address counter, the first input of which is the first input of the device, the output of the address counter is the first output of the device and is connected to the address inputs memory blocks of states and commands, the information output of the memory block of states is connected to the first input of the comparison circuit, the second input Z 40 of which is the second input of the device, the second output of which is the first (informational) output of the command memory block, c are introduced block of memory of transitions, node of logical control and logical element "Ii, and the address input

From" the jump memory block is the third input of the device, the first (informational) output of the jump memory block is connected to the first input of the address counter, the second and third inputs of which are connected to the first and second outputs of the logical control node, the first input of which connected to the second output of the memory block 45 transitions, the second and third inputs of the logical control node are connected, respectively, to the second output of the command memory block and to the output of the logic element "I", the first input of which is the third input of the device, the second input -I of the logical element "I" is connected to the output of the comparison circuit.

The introduction of the indicated distinguishing features of the invention allows to eliminate the hardware redundancy of the device due to the use of an economical layout scheme of controller networks, in which the controller network is a set of 20 slave controllers controlled by one master controller, as well as an effective method of analyzing combinations of transition conditions, which requires reduced hardware expenses

C In fig. a block diagram of the proposed device is given.

The device includes a comparison circuit 1, a state memory block 2, an address counter 3, a transition memory block 4, a command memory block 5, a logic control node 6 and a logic element "AND" 7, and the first input of the address counter C is is the first input of the device, the address counter output C is the first output of the device and is connected to

GF) address inputs of state and command memory blocks 2 and 5, the information output of state memory block 2 is connected to the first input of comparison circuit 1, the second input of which is the second input of the device, the second output of which is the first (information) output of the block 5 of the command memory, the address input of the block 4 of the transition memory is the third input of the device, the first (informational) output of the block 4 of the transition memory is connected to the first input 60 of the address counter 3, the second and third inputs of which are connected according to the first and the second outputs of the logical control node b, the first input of which is connected to the second output of the block 4 of the transition memory, the second and third inputs of the logical control node 6 are connected, respectively, to the second output of the command memory block 5 and to the output of the logic element "I " 7, the first input of which is the third input of the device, the second input of the logic element "AND" 7 is connected to the output of the comparison circuit 1. because Block 2 of the state memory and block 5 of the command memory are designed to store the program (which in general In this case, it consists of K subroutines) managing the operation cycle of the serviced object. The cycle control program in the proposed controller is a sequence of lines, each of which consists of two parts: 1) combinations of commands to turn on and off t mechanisms, 2) combinations of states in which H sensors should come as a result of activation of t mechanisms, while block 5 of the command memory records a sequence of combinations of commands to turn on and off the mechanisms, and to block 2 of the state memory - a sequence of state combinations to which the sensors that fix the position of the mechanisms must arrive as a result of the execution of the corresponding commands, and in each line block 5 of the command memory, one digit is allocated for programming the end of the program (subprogram) sign - KP. 70 Blocks 2 and 5 are addressed in parallel using address counter 3.

Unit 4 of the memory of transitions is intended for storage and execution of the program for selecting the initial addresses of subroutines, which are recorded in units 2 and 5 of the state and command memory.

The comparison scheme 1 is intended for parallel (simultaneous) comparison of combinations of the actual states of cycle sensors with their expected values, which are recorded in the ith line of block 2 of the state memory.

Logical control unit b, depending on the combination of signals at its inputs, performs logical control of the work of address counter 3.

The logical element "I" 7 is intended for the formation of the equivalence signal E at the input of the logical control node 6 when building controller networks.

Standard elements (microcircuits) can be used as the blocks that make up the proposed device: counters, comparison circuits; memory blocks can be implemented, for example, on non-volatile programmable memory devices (PPMS), and the logic control node - on a programmable logic matrix (PLM).

A network programmable parallel controller works like this. Conventionally, it can be divided into two nodes: a slave controller (a/-ai), which includes a comparison circuit 1, memory blocks of states and Commands 2 and 5 and a logic element "I" 7, as well as a master controller , which includes an address counter 3, a memory block of transitions 4 and a logical control node 6. The master controller is used to analyze i) combinations of states of sensors of transition conditions, addressing of slave controllers in the process of executing subprograms, as well as for organizing interrupt functions. The slave controller executes subroutines directly, generates control commands and end-of-subroutine (CP) and equivalence (E) signals. The construction of controller networks based on the proposed device takes place by cascading slave controllers controlled by one master controller, due to which savings in hardware costs are achieved. i am

Setting the device to the initial state is carried out with the help of an external pulse signal "about the initial setting of the PV, which resets the address counter to zero. The process of working out the control program consists of two stages: 1) analysis of combinations of sensor states of transition conditions (states of the external environment) and formation of the starting address of the subprogram; 2) the actual execution of the selected subprogram, with the analysis of the states of the external environment being carried out in parallel and independently of the execution of the subprogram.

In the last line of each subroutine, as well as in the zero line of the program, only the sign of the end of the KP subroutine is written, which is used as a permission for the device to move to the execution of any of the recorded « 40. In blocks 2 and 5 of the subroutines. z с Selection of the initial address of the subprogram is carried out using block 4 of the transition memory, which, in the event of one of the programmed combinations occurring at its input, sets the address counter to the corresponding ;" given state combination. If an unprogrammed combination occurs at its input, the address counter will be set to zero or will remain in it.

The following logic equations are written to the logical control node 6: o KP ZHPRUA, EKP PR - M, - where PR is an interruption sign, E is an equivalence signal from the output of logic element "I" 7.

If the logic equation is solved: KP - A, then at the second output of the logical control node 6, the "Address" ("A") signal appears, according to which the address counter Z carries out re-addressing of blocks 2 and 5 of the memory of states and c 50 commands to the first address of the selected routine or to the zero line.

If the logic equation is solved: there is a PPC P --, then at the first output of the logic control node 6 t the signal "1" appears, according to which the address counter Z addresses blocks 2 and 5 of the memory of states and commands to the next (in-1 ) line.

If a mechanism or sensor fails (which does not lead to an emergency situation) at any step of the subroutine, the transition to the next line of the subroutine does not occur, because the circuit is not triggered

GF) comparison 1, which blocks the logical element "I" 7. 7 In case of failure of mechanisms or sensors, prohibited combinations of states of mechanisms may occur, in which emergency situations may appear in controlled objects that require immediate intervention to management process. For the reaction of the device to emergency situations, one of the outputs of the unit 4 of the memory of the transitions 60 is allocated for fixing and issuing to the third input of the logical control node 6 the signal of the PR interruption sign, while solving the logic equation: PR-A, as a result of which the address counter does not wait at the end of the execution of the working subroutine redirects blocks 2 and 5 of the state and command memory to the initial address of the interrupting subroutine.

When designing controller networks based on the proposed device, an equivalence signal e;

The first inputs of logical elements "I" 7 of all slave controllers except for the last receive the signal E;, which is the product of equivalence signals e 4 e-201... ey.

The first input of the logical element of the last slave controller ar is connected to O. Thus, the equivalence signal E is the product of the equivalence signals of each of the slave controllers: Ehe/ e»o ... ey.

IN OTHER WORDS, the formation of an equivalence signal at the third input of the logical control node would be possible only if this signal is present at the outputs of comparison circuits 1 of all slave controllers.

Claims (1)

The formula of the invention is a network programmable controller that contains memory blocks of states and commands, a comparison circuit and an address counter, the first input of which is the first input of the device, the output of the address counter is the first output of the device and is connected to the address inputs of the memory blocks of states and commands, the information output of the state memory block is connected to the first input of the comparison circuit, the second input of which is the second input of the device, the second output of which is the first (informational) output of the command memory block, which differs in that the memory block transition memory, a logical control node and a logic element "Ii", and the address input of the transition memory block is the third input of the device, the first (informational) output of the transition memory block is connected to the first input of the address counter, the second and third inputs of which are connected according to the first and second outputs of the logic control node, the first input of which is connected to the second output of the transition memory block, the second and third inputs of the logic node of control are connected, respectively, to the second output of the command memory block and to the output of the logic element "AND", the first input of which is the third input of the device, the second input of the logic element "AND" is connected to the output of the comparison circuit. Official bulletin "Industrial Property". Book 1 "Inventions, useful models, topographies of integrated microcircuits", 2003, M 9, 15.09.2003. State Department of Intellectual Property of the Ministry of Education and Science of Ukraine. "- IF) (Se) in village - and? (95) -i (o) 1 - name) 60 b5