UA71200C2 - Programmable logic controller - Google Patents

Abstract

The proposed programmable logic controller can be used in program discrete control systems. The controller contains memory units for storing data on the state of the control system, commands, and intermediate data, an address counter, a comparator, a displaying unit, a logical control unit, and additionally, a memory unit for storing data on the prohibited states of the control system and an output data register. The present invention provides a possibility to exclude the output of prohibited control signals to the actuators of the control system.

Description

Description of the invention

The invention belongs to automation, and more precisely to devices for software-logical control of objects of discrete cyclic action.

The famous programmable logic controller G(a.s. 1302242 USSR, 30.12.85, 505819/18, publ. 07.04.97, Byul.

Mo13), which is a control device of parallel action and contains memory blocks of states and commands, an address counter, a comparison circuit and an indication block, and the first input of the address counter (setting input) is the first input of the device, the information output of the address counter is connected to the address inputs state memory blocks 70 and commands, as well as to the first input of the indication block, the second input of which is connected to the first output of the comparison circuit, the first input of which is connected to the information output of the state memory block, the second input of the comparison circuit is the second the input of the device, the output of which is the first (informational) output of the command memory block.

Analog provides software control of objects with both a deterministic and a random sequence of operations performed, but it is characterized by two serious disadvantages. The first disadvantage is that the analysis of possible combinations of transition conditions is carried out sequentially, condition by condition, by scanning a certain area of memory, as a result of which the duration of the scanning cycle is directly dependent on the number of combinations of transition conditions, which limits the speed of the device. The second disadvantage is that the device lacks control over possible issuance of prohibited combinations of output signals.

The closest in terms of features to the proposed invention is a programmable logic controller (Patent of Ukraine 39306 A, IPC 505819/18. Publ. 15.06.2001, Bull. Mob), which contains memory blocks for states, commands and transitions, an address counter, a circuit a comparator, an indication block and a logic control block, and the first input of the address counter (setting input) is the first input of the device, the second (information) input of which is connected to the first input of the comparison circuit and the input of the jump memory block, the first output of which is connected to of the first input of the logical control block, the first and second outputs of which are connected to the second and third inputs of the address counter, the fourth (informational) input of which is connected to the second (informational) output of the block (3 memory transitions, and the output of the address counter from connected to the address inputs of the state and command memory blocks, as well as to the first input of the indication block, the second input of which is connected to the first output of the comparison circuit, the second input of which is connected to the output state memory block, and the second output is connected to the second input of the logic control block, the third input of which is connected to the first output of the command memory block, in which the first drawback of the analog is completely eliminated: the structure of the programmable logic controller is improved by Ha») application of parallel (simultaneous) analysis of all possible combinations of transition conditions and increased device performance is ensured. with

The reasons that prevent the prototype from achieving the expected technical result are the following: the device lacks control over the possible issuance of prohibited combinations of output signals in

If the controller fails. -

The basis of the invention is the task of improving the structure of the programmable logic controller by introducing control of output of prohibited combinations of output signals.

The implementation of the given task is achieved by the fact that in the programmable logic controller, which contains blocks of memory of states, commands and transitions, an address counter, a comparison circuit, an indication block and a block of logical Z 50 control, and the first input of the address counter (setting input) is the first input of the device, the second c (informational) input of which is connected to the first input of the comparison circuit and the input of the transition memory unit, the first output of which is connected to the first input of the logical control unit, the first and second outputs of which are connected to the second and the third input of the address counter, the fourth (information) input of which is connected to the second (information) output of the transition memory block, and the output of the address counter is connected to the address inputs of the state and command memory blocks, as well as to the first input of the indication block , the second entry of which is this. connected to the first output of the comparison circuit, the second input of which is connected to the output of the state memory block, and the second output is connected to the second input of the logic control block, the third input of which is connected to the first output of the command memory block, according to the invention a memory block of forbidden states and an output register are introduced, the output of which is the output of the device, and the first input is connected to the second (informational) output of the memory block of 20 commands and an input of the memory block of forbidden states, the first output of which is connected to the fourth input of the logical control unit, and the second output is connected to the second input of the output register. c Entering the specified signs allows you to monitor the appearance of prohibited combinations of output signals at the output of the programmable logic controller and, in the event of such, to block their submission to the executive mechanisms of the controlled object and to transfer the controller to the emergency interrupt processing mode. 25 In fig. a block diagram of the proposed device is given.

GF) The device contains an indication block 1, a comparison circuit 2, a logic control block 3, memory blocks of states 4, transitions b and commands 7, an address counter 5, a memory block of forbidden states 8 and an output register 9, and the first input address counter 5 (setting input) is the first input of the device, the second (informational) input of which is connected to the first input of the comparison circuit 2 and the input of the transition memory block 6, the first output of which is connected to the first input of the logic control block C, the first and the second outputs of which are connected to the second and third inputs of the address counter 5, the fourth (information) input of which is connected to the second (information) output of the memory block of transitions 6. The output of the address counter 5 is connected to the address inputs of the memory blocks states 4 and commands 7, as well as with the first input of the display unit 1, the second input of which is connected to the first output of the comparison circuit 2, the second input of which is connected to the output of the state memory unit 4. because the second output of the comparison circuit 2 is connected to the second input of the logical control unit 3, the third input of which is connected to the first output of the command memory unit 7. The first input of the output register 9 is connected to the second (informational) output of the command memory unit 7 and the input of the memory unit forbidden states 8, the first output of which is connected to the fourth input of the logical control unit Z, and the second output is connected to the second input of the output register 9, the output of which is the output of the device.

State memory unit 4 and command memory unit 7 are designed to store the program (which generally consists of K subprograms) for controlling the operation cycle of the serviced object. The cycle control program in the proposed controller is a sequence of lines, each of which consists of two parts: 1) combinations of commands to turn on and turn off t mechanisms; 2) combinations of states in which n sensors should enter 70 as a result of activation of t mechanisms, while the sequence of combinations of commands to turn on and off the mechanisms is recorded in unit 7 of the command memory, and the sequence of combinations of states is recorded in block 4 of the state memory, to which the sensors that fix the position of the mechanisms as a result of the execution of the corresponding commands should come. Moreover, in each line of block 7 of the command memory, one digit is allocated for programming the end of program (subprogram) sign - KP.

Blocks 4 and 7 are addressed in parallel using the address counter 5. Block 6 of the memory of transitions is intended for storing and working out the program for selecting the initial addresses of subroutines, which are recorded in blocks 4 and 7 of the state and command memory. The comparison scheme 2 is intended for parallel (simultaneous) comparison of combinations of the actual states of cycle sensors with their expected values, which are recorded in the i-th line of block 4 of the state memory. Logical control unit C, depending on the combinations of signals at its inputs, performs logical control of the address counter 5.

Block 8 of the memory of forbidden states is designed to store forbidden combinations of output signals of the controller. Output register 9 is intended for temporary storage of combinations of output signals and blocking of output of prohibited combinations of output signals.

The proposed device can be built, for example, on programmable logic integrated circuits (PLCs), using the MAX krinz II 10.0 VAZENIME software package.

A programmable logic controller works as follows. Setting it to the initial state i) is carried out with the help of an external pulse signal of the initial setting of the PU, which resets the address counter 5. The process of working out the control program consists of two stages: 1) analysis of combinations of sensor states, transition conditions (states of the external environment) and formation of the initial address of the subprogram ; (sub-section 2) the actual execution of the selected subprogram, and the analysis of the states of the external environment is carried out in parallel and independently of the execution of the subprogram. at

In the last line of each subroutine, as well as in the zero line of the program, only the sign of the end of the KP subroutine is written, which is used as a permission to move the device to the execution of any of the subroutines written in blocks 4 and 7. --

The selection of the initial address of the subprogram is carried out using the block 6 of the transition memory, which, in the event that one of the programmed combinations occurs at its input, sets the address counter 5 to the state corresponding to this combination. The following logical equations are written to the logical control node Z;

KPAPRITAPRO2-A,

EOKPOPRT OPR - M, where KP is the sign of the end of the subprogram; - с PRI - a sign of interruption from block 6 of the memory of transitions; and PR - a sign of interruption from block 8 of the memory of forbidden states; ,» A - starting address of the subprogram;

E - equivalence signal from the second output of comparison circuit 2;

Ж- - the signal by which the address counter 5 addresses memory blocks of states 4 and commands 7 to the next line. -i If the logical equation KP-A is true, then at the second output of the logical control node Z, the signal "Address" (A) appears, according to which the address counter 5 redirects blocks 4 and 7 of the memory of states and commands to the first address selected routine. If there is a true logical equation. PRI. PR - i, then the signal "1" appears at the first output of the logical control node Z, according to which the address counter 5 addresses blocks 4 and 7 of memory av | 20 states and commands to the next (in1) line.

If at any step of the routine there is a failure of the actuator or the sensor (which does not lead to an emergency situation), the transition to the next line of the routine does not occur, because the comparison circuit 2, from the first output of which to the second input of the display unit, does not work 1 gives information about the non-equivalence of the state of the i--o sensor (sensors) programmed (programmed) on this subroutine line. In addition, the status of counter address 5 (subroutine line number) is issued before the first entry of the block

GF) indications 1. The specified information can be used for automatic diagnostics of the controlled object.

In case of failure of mechanisms or sensors, forbidden combinations of states of mechanisms may occur, in which emergency situations may appear in the controlled object that require immediate intervention in the control process. In order for the device to respond to these emergency situations, one of the outputs of the block b of the transition memory 60 is allocated for fixation and output to the third input of the logic control block Z signal of the interrupt sign PR1 (at the same time, the logic equation PRI1-A is true), as a result of which the address counter 5 without waiting for the end of the execution of the working subroutine, redirects blocks 4 and 7 of the state and command memory to the starting address of the interrupt subroutine 1.

In the event of failure of the controller and the appearance of a prohibited combination of output signals on the second (informational) output of block 62 of command memory 7, block 8 of the memory of prohibited states by a BV signal

(output blocking) prohibits the supply of these signals to the output of the device and issues to the logical control block Z a signal indicating the interruption of PR (at the same time, the logic equation PR2-A is true), as a result of which the address counter redirects blocks 4 and 7 of the memory of states and commands to of the starting address of the interrupt routine 2.

Claims (1)

Formulation of the invention Programmable logic controller containing memory blocks of states, commands and transitions, an address counter, a comparison circuit, an indication block and a logic control block, and the first input of the address counter (setting input) is the first input of the device, the second (information ) the input of which is connected to the first input of the comparison circuit and the input of the transition memory block, the first output of which is connected to the first input of the logical control block, the first and second outputs of which are connected to the second and third inputs of the address counter, the fourth (informational) the input of which is connected to the second (informational) output of the memory block of transitions, and the output of the address counter is connected to the address inputs of the state and command memory blocks, as well as to the first input of the indication block, the second input of which is connected to the first output of the comparison circuit , the second input of which is connected to the output of the state memory block, and the second output is connected to the second input of the logic control block, the third input of which is connected to the first output of the command memory block, which is distinguished by the fact that a forbidden states memory block and an output register are introduced to it, the output of which is the output of the device, and the first input is connected to the second (informational) output of the memory block commands and the input of the memory block of prohibited states, the first output of which is connected to the fourth input of the logic control block, and the second output is connected to the second input of the output register. c 6) "c) "c) c "- and - - and? -i - name) ("in) (42) name) because b5