SU1721587A1 - Logical concurrent programmable controller - Google Patents

Abstract

The invention relates to automation, in particular, to devices for programmatically controlling objects of discrete cyclic action. The aim of the invention is to improve the speed of the device. This is achieved by the fact that a situation analysis block, a controller state analysis block, a register and a second comparison block are inserted in the device, which allow parallel (simultaneous) analysis of all possible combinations of transition conditions, which increases the controller speed. Zil.

Description

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The invention relates to automation, in particular, to devices for programmatically controlling objects of discrete cyclic action.

The aim of the invention is to improve the speed of the device.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - time diagram of the device; in fig. 3 is a block diagram of a comparison.

The device contains the first comparison unit 1, a pulse generator 2, a situation analysis unit 3, a state memory block 4, a controller state analysis block 5, a second counter 6; register 7, second comparison unit 8, first pulse counter 9, command instruction block 10.

The state memory block 4 and the command memory block 10 are intended for storing a program (generally consisting of K

subroutines) management cycle of the serviced object. The cycle control program is a sequence of lines, each of which consists of two parts: a combination of commands for switching on and off m mechanisms, as well as combinations of states that n sensors have to go to as a result of m mechanisms, and in block 10 These commands record a sequence of command combinations for switching on and off mechanisms, and in block 4 of the state memory, a sequence of combinations of states to which the sensors fixing the positions of the mechanisms (sensors ki cycle) by performing appropriate commands, wherein each line block memory commands THAT one bit allocated for programming the terminator program (CP). In quality

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Standard programmable read-only memory with built-in nodes, address decryption and information reading control can be used in memory blocks. The addressing of blocks 4 and 10 is carried out parallely with the help of the second 9 counter.

The situation analysis unit 3, which can be performed, for example, on a programmable logic array (PLA), is designed to store and refine the program for selecting initial addresses of subroutines recorded in state and command memory blocks, while in block 3 a set of logical equations is written The arguments of which are the states of the conditions of the transition conditions (inputs of the PLA), and the combinations of the values of the functions (the states of the outputs of the PLAs) are the codes of the addresses of the transitions to the corresponding subroutines recorded in blocks It is five conditions and commands.

The first comparison unit 1 serves for parallel (simultaneous) comparison of the combination of the actual states of the cycle sensors (Xi, XaHp) with their expected values (X /,). recorded in the i-th line of the state storage unit. The first comparison unit can be performed by one of the known methods, for example as shown in FIG. 3, where 3xi Eha Ehp signals of non-equivalence

programmed and actual sensor states.

Generator 2 is used to synchronize the operation of device blocks. The second counter b serves to digitally filter the control signals generated in block 5.

Register 7 is used to temporarily store a combination of the states of the sensors of the transition conditions, which is checked by means of the comparison unit 8 for truth, i.e., an analysis is carried out whether the combination of states, sensors of the transition conditions recorded in the register is stable or The combination was formed during short-term false triggering of sensors and (or) as a result of the effect of interference at the first input of the device.

Block 5 (which can be performed, for example, on a programmable logic array), depending on the combination of signals at its inputs, performs logical control of the operation of the first counter 9 (address counter). As sensors connected to the device: both the actual ones installed on the mechanisms, and the control and protection controls, control signals of information and electrical interlocks from other devices can be used.

. The device works as follows.

The device is reset to its initial state by means of an external pulse signal of the initial setting.

0 (НУ) and consists in zeroing the first counter 9. The testing of the control program consists of two stages: analyzing the combination of the states of the sensors of the transition conditions (state of the external environment) and forming

5 of the initial address of the subprogram, as well as the actual processing of the selected subprogram, the analysis of the state of the environment is carried out in parallel and independently of the subprogram working.

0 In the last line of each subroutine, combinations of the states of the sensors and control commands are not recorded, but only the end of the KP subroutine, which is used as

5 allowing the device to go to work on any of the memory, states and commands recorded in blocks 4 and 10. For the convenience of users, the flag can be written in the zero line of blocks 4 and 10 of memory

0 states and subroutine commands, which corresponds to the state of the first counter 9 (address counter) after the initial setup signal has been processed.

The selection of the start address of the subroutine 5 that is to be tested at a given time is carried out using the situation analysis block 3, which analyzes combinations of the states of the sensors of transition conditions (states of the external environment).

0 In the event that one of the programmed combinations is formed at its output, this combination will be entered into register 7 by the next pulse of generator 2 and fed to the information input of the second counter 9 and to the second input of the comparison unit 8. The first input of this block receives a combination of signals from the outputs of block 3 of the situation analysis. With the coincidence of combinations of signals on the first and second

The 0 inputs of the comparison unit 8 form the signal Equivalence 2 (E2) at its output, which is fed to the second input of the block 5. In block 5, the following logical equations are written:

5E2КППР + Э2ПР + КППРЭ1 У0:

E2KUPRUP + E2PRUP A; E1KPRRU „+1,

where Et is the equivalence signal from the second output of the first comparison unit 1; OL is a sign of interruption;

Wo - signal installation in the second counter 6;

Pack - signal Overflow at the output of the second counter 6.

In case the logical equation holds

E2KPRP Y0,

Then the reset signal is removed from the setup input of the counter b, thereby allowing the pulse count of the generator 2 to enter the counting input of the counter 6, which is used to repeatedly confirm (control) the validity of the signal US, at the second output of the controller state analysis block 5. The duration of repeated monitoring is selected depending on the specific conditions of use of the device. In the event that the occurrence of a signal at the installation input of the counter b is random (for example, caused by interference at the first input of the device), then the restoration of the signal V0 at the installation input returns the counter 6 to the zero state. If the occurrence of the signal V0 on the installation input of the counter 6 is not accidental, then upon completion of multiple monitoring, the output of the counter 6 generates an overflow pulse, which is fed to the input of the controller state analysis unit 5, if the logical equation

E2KUPRUP A.

then the output of block 5 is the Address (A) signal, through which counter 9 redirects blocks 4 and 10 of the state memory and commands to the first address of the selected subroutine. At the same time, the output of block 10 of the command memory to the controlled object is used to issue control commands written on this line, the corresponding mechanisms are triggered, and consequently the sensors, and the combination of actual states of the cycle sensors is compared with block 1 compared to a combination of states read from block 4 of the state memory. When the actual combination of conditions coincides with that of the comparative unit 1 programmed at the second output, the Equivalence 1 (E1) signal appears at the first input of the controller state analysis unit 5. If at the same time in block 5 the logical equation is realized

E1KPRP Y0,

This again includes a digital filter built on the counter 6 and with repeated confirmation of the truth of the signal V 0 in block 5 of the state analysis of the controller 5, the logical equation is realized

E1KP PRUP +1,

as a result, a +1 signal appears at the output of block 5, increasing the contents of counter 9 by one. When this happens, the addressing of blocks 4 and 10 to the next step of the subroutine occurs. Further, the process of working out

the rows (steps) of the subroutine are executed as described.

In the event that at any step of the subroutine a failure occurs or the mechanism or sensor fails, the transition to

the next line of the subroutine does not occur, since block 1 of the comparison cannot be triggered, the output of which gives information about the nonequivalence state of the i-ro sensor (s) programmed (programmed) on this program line. The specified information can be used for automatic functional diagnostics of the operation of the controlled object. In addition, the state of the second counter 9 (the line number of the program) is output to the second output of the device and can also be used for diagnostics. When a malfunction is rectified, the device automatically continues to work on the next lines of the subprogram. When the last step of the subroutine is being processed, a signal appears at the output of the command memory block 10. The end of the subroutine (CP) signal is blocking

the operation of the block 5 of the analysis of the states of the controller 5 by the signal E1 before proceeding to the working out of the next subroutine.

Transitions in the program are implemented in the next subprogram, that is, in strictly deterministic moments of time. At the same time, in real objects, upon failure to build mechanisms or sensors, combinations of the states of mechanisms (and, consequently, sensors) may be formed, which are prohibited, i.e., such that emergency situations can occur in controlled objects requiring immediate intervention in the management process. For the device to respond to emergency situations, one of the outputs of the situation analysis unit 3 and one bit of the register 7 and the address bus are allocated to latching and issuing a signal to the third input of the signal.

(OL), while in block 5 the logical equation is realized

E2PR U0,

and after control on the digital filter and the equation

E2PRUP A,

As a result, the second counter 9, without waiting for the end of the working subprogram to be completed, enters the transition address to the interrupting subprogram corresponding to the emergency situation at the controlled object.

The described principle is illustrated by a time diagram of the operation of the device (Fig. 2), where the times ti -t correspond to the sequential processing of the rows of the subprogram;

t - te transition to the new (working) subprogram;

tg - tio - transition to the emergency routine.

Claims (1)

Invention Programmable parallel action logic controller containing a first comparison unit, a pulse generator, state and command memory blocks, first and second pulse counters, the first input of the first comparison block being the first input of the device, and the output of the first input of the first comparison block state memory, and the first output of the first comparison unit is the first output of the device, the installation the input of the first pulse counter is connected to the second input of the device, and the output of the first pulse counter is connected to the address inputs of the memory blocks and commands and is the second output of the device, the third output of which is the first output of the instruction memory block, characterized in that, in order to increase the speed of the device, a situation analysis unit, a controller state analysis unit, a register and a second comparison unit, the first input of the device connected to the situation analysis unit input, the output of which is connected to the register information input and the first input of the second comparison unit, the second input of which is connected to the register output and information input. the first pulse counter, the first summing and second the address inputs of which are connected to the first and second outputs of the controller state analysis unit, the third output connected to the installation input of the second pulse counter, whose counting input and register recording input are connected to the output of the pulse generator, the second pulse counter output is connected to the first input of the state analysis unit controller, the second input of which is connected to the second output of the first comparison unit, the third input of the controller state analysis unit is connected to the output of the second comparison unit, quarters analyzing input states of the controller block is connected to one bit of register rows, and a fifth input analysis unit controller states coupled to the second output of the block memory commands. / d ;. f. ED $ o, u. i h 1C THOSE U3T / 7 / y / 31 ol Ujfid i-n z Рцг.З