RU2254603C1 - Device for building programmable digital microprocessor systems - Google Patents

Abstract

FIELD: computer science.

SUBSTANCE: device has input block, commutation-computing block, random access memory block, output block, programmable block, synchronization block, multi-channel operation block, conditional transfers block, sub-programs block, interruptions block, common buses.

EFFECT: broader functional capabilities, lower laboriousness.

14 dwg

Description

The proposed device relates to systems of logical-programmed control and regulation of technological objects in various industries and to the means of solving logical problems.

A device is known that contains input and output blocks, RAM and synchronization blocks, address buses, a pulse generator, a program block, a switching and computing unit consisting of a three-input decoder, three two-input AND elements, an OR element, an EXCLUSIVE OR element, and a controlled memory cell, command buses, arriving, like address buses, from the outputs of the program unit / 1 /.

The disadvantage of this device is the relatively low speed, a large amount of memory cells in the program block when implementing, for example, the process of comparing binary codes.

The most technically closest is a device containing an input unit interconnected in a certain way that receives signals from sensors and generates a specific code at its output, an output unit for recording and storing the received code values coming from the logical channels of a multi-channel operating unit, as well as from switching a computational unit, a program unit where the program of the device’s operation is stored, a RAM unit for storing intermediate results of calculations and other logical operations, synchronization unit, providing stable operation of the entire device / 2 /.

The disadvantages of this device include the need to re-enter its repeating parts into the main program each time, for example, each time binary numbers are subtracted, as well as the inability to transfer certain data inside the device, depending on the results of the analysis of these data in the switching and computing unit and the impossibility of the functional implementation of priority interruption during the execution of the main program by signals from the sensors of the control object.

The aim of the invention is to expand the functionality of the device by organizing the process of priority interruption and communication of the results of the calculations with the process of data transfer, as well as reducing the amount of programming.

To this end, in an apparatus containing an input unit that receives signals from sensors and generates a specific code at its output, an output unit for recording the values of codes coming from all logical channels to memory cells and transmitting them through digital-to-analog converters to electrical actuators, a program unit, RAM unit, synchronization unit and switching and computing unit, consisting of an AND element OR an EXCLUSIVE OR element, five AND elements, a memory cell, OR or NOT elements, the first inputs of two and the AND-OR element is connected respectively to the third and fourth outputs of the decoder, and the second inputs are connected to the output of the input block connected by the first and second groups of inputs to the group of information outputs of the control object and to the group of address outputs of the program block, as well as to the output of the RAM block, the output of the AND-OR element is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to a specific output of the program unit, the output of the EXCLUSIVE OR element is connected to the first input of the third element And, connected by the second input to the corresponding output of the synchronization unit, and by the output to the control input of the memory cell, and its information input is connected to the output of the OR element, the second input of which is connected to the output of the fifth AND element, the second input of the latter is connected to a certain bus of the program unit, the first the input of the fifth AND element is connected to the output of the NOT element, and the input of the latter is connected to the second input of the fourth AND element with the corresponding bus of the program unit, the first input of the fourth AND element is connected to the inverse output the memory cell, and its output is connected to the first input of the OR element, the direct output of the memory cell is connected to the information inputs of the output block and the RAM block, the first inputs of the first and second elements And are connected to the first and second outputs of the decoder, their second inputs are combined and connected with the corresponding output of the synchronization unit, and the outputs are connected to the corresponding inputs of the output unit and the RAM unit for controlling the recording of information, a multi-channel operation unit containing a controlled element , nine AND elements, seven OR elements, first and second decoders, a controlled memory cell and "n" parallel logical channels having the same structure, each of which contains an EXCLUSIVE OR element inside itself, the first, second and third AND elements, the first and the second OR element, the first and second counting triggers, while in each logical channel of the multichannel operational block the output of the EXCLUSIVE OR logic element is connected to the first input of the first OR element, the second input of which is connected to the first mu input of the first element And and the output of the second element And, and the output is connected to the first input of the third element And, the output of the last is connected to the counting input of the first counting trigger, the output of which is connected to the second input, the first element And to the counting input of the second counting trigger, the output of the latter is connected to the first input of the second OR element, the second input of which is connected to the output of the first AND element, while inside the multi-channel operation unit, the output of the first OR element is connected to the second inputs of the EXCLUSIVE OR elements logical channels, the first and second inputs of the first OR element are connected respectively with the outputs of the first and second AND elements, and the two inputs of the first AND element are connected to one of the outputs of the second decoder and the output of the third OR element, the inputs of which are connected to two corresponding outputs of the first decoder, the first the input of the second AND element is connected with one of the inputs of the third OR element and with a specific output of the first decoder, the second input of the second element And is connected to the output of the seventh element And, the first and second input The second OR element is connected to the outputs of the sixth and seventh AND elements, and the third input is to the output of the third AND element, the inputs of which are connected to the corresponding output of the second decoder and from logic 1, the first inputs of the sixth and seventh AND elements are connected to the corresponding outputs of the second decoder and the second inputs, respectively, to the direct and inverse outputs of the memory cell, the information input of which is connected to the output of the second OR element of the last logical channel, and the control input of the controlled memory cell is connected with the output of the fourth element And, the first input of which is connected, together with the first inputs of the second elements AND of all logical channels, to the corresponding output of the first decoder, the second input of the fourth element And, together with the second inputs of the third elements And of all logical channels, connected to a specific output of the synchronization unit, and the third input of the fourth element And is connected with a specific output of the second decoder, in a multi-channel operating unit, the control input of the controlled element is connected to a specific program output there is a lot of block and with the first input of the fifth OR element, the output of the last is connected to the first input of the ninth AND element, in the switching and computing unit, the first inputs of the third and fourth elements AND of the AND-OR element are respectively connected to certain outputs of the first decoder, and the second inputs are connected accordingly, with the output of the controlled element And with the inverse output of the second counting trigger of the last logical channel in the multi-channel operating unit, the inputs of the first and second decoders are connected to the command buses software unit, an output of second OR of the first logic channel is connected to a second input of the second AND gate of the second logical channel, the second time the output of the second OR logical channel connected to a second input of the second element and the third logical channel etc. to the last logical channel, the second input of the second AND element of the first logical channel is connected to the output of the second OR element of the multi-channel operating unit, where the inverse output of the managed memory cell is connected to the corresponding input of the output unit, the second input of the fifth OR element is connected to one of the common buses of the communication system, transmitting the first bit of the code word, the second input of the ninth element AND is connected to the output of the sixth element OR, the inputs of the eighth element AND are connected to the corresponding outputs of the first decoder and a synchronization block, and the output is connected to the first input of the fourth OR element, the output of the last is connected to the reset inputs of the second counting triggers of all logical channels at “0”, the inputs of the fifth AND element are connected to certain outputs of the program block and synchronization block, and the output is connected to the second the input of the fourth OR element and with the reset inputs to "0 ^{" the} first countable triggers of all logical channels, also a communication system that covers the corresponding blocks and contains the first and second electronic keys, common buses, logical element ent, in the multi-channel operating unit there are sixth and seventh OR elements, a NOT element and an electronic switch, and in each logical channel there is a fourth AND element, a bit shift module / MCP / and a logic function implementation module / MPF /, MCP1 modules are available in all channels in addition to the first and the last, they realize the logical functions (1) and (2), have six inputs and two outputs, of which the first inputs of the MCP1 modules of all logical channels, except the first and last, are combined and connected to the output of the NOT multi-channel operational element about the block, the rest of the inputs of the MCP1 modules are connected respectively to two specific outputs of the program block, with the outputs of the first two counting triggers of this and subsequent channels, and the outputs of the MCP1 module are connected respectively to the third and fourth inputs of the first OR elements of this and subsequent channel, the MCP2 module of the first channel has six inputs, three outputs, implements Boolean functions (3), (4), (5), two outputs of the MCP2 module are connected respectively to the third and fourth inputs of the first OR element of the first channel, and the third output of the module MCP2 is connected to the fourth input of the first OR element of the second logical channel, the inputs of the MCP2 module are connected respectively to the output of the element NOT a multi-channel operating unit, to two specific outputs of the program unit and to the outputs of the first two countable triggers of the first and second logical channels, the MCP3 module of the last logical channel has one output, four inputs, implements a Boolean function (6), the output of the MCP3 module is connected to the third input of the first OR element of the last channel, and the inputs of the MCP3 are connected respectively to the output m of an element of a NOT multi-channel operating unit, with one of the outputs of the program unit and with the output of the first counting trigger of the last logical channel, the MRF modules in each logical channel implement the same Boolean functions (7), the inputs of the MRF module in each logical channel are connected respectively to the outputs of the first and the second counting flip-flops inside each logical channel and to two specific outputs of the program block, and the outputs of the MRF modules are the outputs of the corresponding logical channels and are connected in multi-channel an operating unit with inputs of a controlled element and information inputs of an electronic switch, the control input of which is combined with the input of the element NOT and connected to the output of the seventh OR element, two inputs of which and two inputs of the sixth OR element are connected to the corresponding four outputs of the first decoder, the output of the ninth element And connected to the first inputs of the fourth elements AND in each logical channel, the second inputs of the fourth elements AND of each logical channel together with the information outputs of the electronic switch The multichannel operating unit is connected to the common buses of the communication system, and the outputs of the fourth AND elements in each logical channel are connected to the first inputs of the EXCLUSIVE OR elements, the common buses are also connected to the outputs of the first and second electronic keys of the communication system, and to certain inputs of the RAM block and output block, the inputs of the first and second electronic keys are connected to the multi-bit outputs of the input block and the RAM block, the control inputs of the first and second electronic keys, the opera block the real memory and the output block are connected to the corresponding outputs of the logic element, the three inputs of which are combined with the corresponding three inputs of the first decoder of the multichannel operational block and are connected to the specific outputs of the program block, the sixth inputs of the MCP1 and MCP2 modules and the fourth input of the MCP3 module are combined and connected to a specific output the first decoder of the multichannel operational unit, an additional two control buses emerging from the program unit, a conditional branch unit containing second and second buses, pulse counters, for example one, several rows of memory cells, for example two rows, the corresponding number of electronic keys, for example four, a control module having, for example, nine inputs and eight outputs, the first buses being connected to the address buses of the program unit , with the corresponding inputs of the pulse counter, the first and second rows of memory cells, with the inputs of the fourth electronic key and with three inputs of the control module, the second buses in the conditional transition block are connected to the corresponding outputs four electronic keys and with certain inputs that determine the addresses of sources and receivers of information in the input block, the RAM block and the output block, the fourth and third inputs of the control module are connected to the corresponding command buses of the software block, two more inputs of the control module are connected respectively with two additional control buses , the eighth and ninth inputs of the control module are connected to the corresponding outputs of the switching and computing unit and the synchronization unit, in the conditional transition unit three outputs of the control module are connected to the control inputs for writing binary code, respectively, of the pulse counter, the first and second rows of memory cells, the fourth, fifth, and sixth outputs of the control module are connected to the input inputs of three electronic keys, the seventh output of the control unit of the conditional transition unit is connected to the counting by the input of the pulse counter of the conditional transition block, the second and first additional control buses of the software block are connected to the blocking input of the second multi-channel decoder unit and with the control input of the fourth electronic key in the existing conditional transition block and the second buses in the conditional transition block, connected to the corresponding inputs of the electronic key in the program block counter, a subprogram block containing the first and second electronic keys, a binary pulse counter, the first and the second elements And, a controlled trigger, the third element And, a memory module, and the information inputs of the first electronic key are connected to the corresponding address outputs / buses / software block, the first electronic switch control input coupled to the output of the first AND gate whose inputs are connected to the additional bus and the program block to a specific output of the synchronization block, the outputs of the first electronic switch coupled to inputs of mounting a pulse counter; a counting input, which is connected with the output of the second element And, the inputs of the latter are connected to the output of the synchronization block and to the direct output of the controlled trigger, the inverse output of the latter is connected to the control input of the electronic key of the program unit and to the first input of the third element And, the second input of which is connected with the corresponding the output of the synchronization block, the output of the third element And is connected to the counting input of the pulse counter of the software block, the outputs of the binary pulse counter are connected to the inputs of the memory module, the outputs are connected to the information inputs of the controlled trigger and the second electronic key, the control input of the latter is connected to the direct output of the controlled trigger, the control input of which is connected to the corresponding output of the synchronization block, the outputs of the second electronic key of the block of subprograms are connected to the corresponding command and address outputs / buses / electronic key of the software unit, an AND-NOT element and a sixth AND element are inserted into the switching and computing unit, and I enter we have a second key, AND and OR elements, also an interrupt block containing an H element, triggers for receiving interrupts, an interrupt sequence selection module that implements Boolean functions

входами модуля выбора очередности прерываний, выходы которого

связаны с входами шифратора, выходы последнего подключены к входам элемента ИЛИ и к входам ПЗУ, выходы которого соединены с информационными входами электронного ключа, вход управления последнего связан с выходом элемента И, первый и второй входы которого связаны с выходом элемента ИЛИ и с соответствующим выходом блока синхронизации, третий вход элемента И связан с выходом элемента НЕ, вход которого соединен с введенной шиной, многоразрядная ячейка памяти и многоразрядный электронный ключ, а в программный блок введены еще две шины управления, при этом информационные и управляющий входы многоразрядной ячейки памяти соединены соответственно с общими шинами и с первой из двух введенных шин управления, а выходы многоразрядной ячейки памяти подключены к информационным входам многоразрядного электронного ключа, вход управления которого соединен через вторую введенную шину с определенным выходом программного блока и с вторым входом управления электронным ключом программного блока, выходы многоразрядного электронного ключа связаны с адресными шинам.are the input and output signals received at the corresponding inputs and outputs of the interrupt sequence selection module, an encoder, read-only memory ROM, an electronic key, logical elements AND and OR, and the information and control inputs of triggers for receiving interrupt signals receive, respectively, request signals for interruption from certain sensors and a signal from the corresponding output of the synchronization unit, and the outputs of these triggers are connected to

the inputs of the interrupt sequence selection module, whose outputs

are connected to the inputs of the encoder, the outputs of the latter are connected to the inputs of the OR element and to the inputs of the ROM, the outputs of which are connected to the information inputs of the electronic key, the control input of the latter is connected to the output of the AND element, the first and second inputs of which are connected to the output of the OR element and to the corresponding block output synchronization, the third input of the AND element is connected to the output of the NOT element, the input of which is connected to the entered bus, a multi-bit memory cell and a multi-bit electronic key, and two more control buses are introduced into the program unit In this case, the information and control inputs of a multi-bit memory cell are connected respectively to common buses and to the first of two entered control buses, and the outputs of a multi-bit memory cell are connected to information inputs of a multi-bit electronic key, the control input of which is connected via a second input bus with a specific program output block and with the second input of the electronic key control of the software block, the outputs of the multi-bit electronic key are connected to the address buses.

выходы элементов 8, 9. Управляемый элемент 16 реализует функции ИЛИ, либо исключающее ИЛИ.The device consists of the input unit 1 shown in FIG. 1, one group of inputs of which is connected to discrete sensors and sources of binary code / not shown on the diagram / X1 ... X _R , and the second group of inputs is connected to address speakers C12 ... C _j associated with the switching and computing unit 2 connected to the RAM unit 3, the output unit 4, the program unit 5, the synchronization unit 6, the output of which is connected to the multi-channel operation unit 7 containing the first and second decoders 8 and 9, the latter being connected with first entry first AND element 10, connected by the second input to the output of the third element OR 11, connected by its input to the first input of the second element AND 12, connected by the second input, through the second element OR 13 to the third element AND 14, and the output to the first element OR 15, the output of which associated with the corresponding inputs of all logical channels from "n", the fifth element OR 107, the managed element 16, the managed memory location 17, the sixth element And 18, the seventh element And 19, the fourth element And 20, the fifth element And 21, the fourth element OR 22 , eighth 72 and ninth 73 elements And, w the stop element OR 74, the seventh element OR 75, the element NOT 76, the electronic switch 77 and the common buses 80 shown in FIG. 10, the logic element / decoder / 81, the two outputs of which are connected to the first electronic key 82 and the second electronic key 83 and control their work, and the other two outputs of the logic element 81 are connected to the corresponding inputs of the RAM block and the output block, block conditional transitions 86, block routines 97, e1 ... e7, D1 ... D3,

the outputs of the elements 8, 9. The controlled element 16 implements the function of OR, or exclusive OR.

Two outputs of the element 81 associated with the inputs of the keys 82 and 83 are indicated by e1 and e2, respectively, and two other outputs of the element 81 associated with blocks 3 and 4 are indicated by e3 and e4, respectively. The values of the signals e1 ... e4 at the output of the element 81 are similar to the values of the signals e1 ... e4 at the outputs of the decoder 8 in block 7, respectively. Only one signal is activated at a time.

- командные сигналы /шины/ на выходах блока 5, управляющие блоками 2, 7, 86, 97. c'₁₂...c'_j - адресные команды /шины/, определяющие адреса источников и приемников информации в блоках 1, 3, 4, идут с выходов блока 86.An electronic switch 77 in block 7, keys 82 and 83, element 81 and common buses 80 are introduced for organizing the exchange of information on common buses 80, between blocks 1, 3, 4 and block 7 on both sides. When the signal e1 is activated, respectively, at the outputs of element 81 and decoder 8 of block 7, key 82 passes the value of the code Q1 ... Qn from the outputs of input block 1 to the inputs of logical channels in block 7 by common dyns 80. At the same time, the outputs / signals / e2 .. .e4 are not activated, the switch 77 in block 7 and the key 83 are closed and there is a high resistance impedance at their outputs. In the case of activation of the signal / outputs / e2, the key 83 passes the code P1 ... Pn from the outputs of block 3 to the inputs of the logical channels in block 7 via shared buses 80. At the same time, key 82 and switch 77 in block 7 are closed and there is a high impedance of resistance. When e3 or e4 is activated, the output of the OR element 75 is activated and the switch 77 in block 7 passes the value of the code B1 ... B _n from the outputs of the logical channels to the rows of memory cells respectively in block 3 or in block 4, and at the outputs of the keys 82 and 83 high impedance of resistance.

- command signals / buses / outputs on unit 5, the control unit 2, 7, 86, 97. c _'12, ... c' _j - address command / tires / determining the source address and data receivers in blocks 1, 3, 4 come from the outputs of block 86.

X _{k + 1} ... X _R - discrete input signals from sensors / buttons, directional switches, etc. /. B1 ... B _n - outputs of logical channels.

X1 ... X _n , ..., X _m ... X _k - multi-bit binary codes / signals /, for example from analog-to-digital converters, where the left bits are the least significant, T1 ... T _{n + 1} - information data on shared tires 80.

The inputs of blocks, channels, and elements are indicated by incoming arrows. Figure 2 shows the structure of the logical channels included in the multi-channel operating unit 7. Each of the "n" logical channels consists of a fourth AND 23 element connected by an output to the first input of an EXCLUSIVE OR 24 element, the output of which is connected to the first input of the first OR 25 element , the second input of the latter is connected to the first input of the first element And 26 to the output of the second element And 27, and the output is connected to the input of the third element And 28, the output of which is connected to the counting input of the first counting trigger 29, the input of which is connected to the counting input of the second counting trigger 30, the first input of the second OR element 31 is connected to the output of the last one, the second input of this element is connected to the output of the And element 26, the bit shift module MCP2 for the first channel, the shift module MCP3 for the last channel and the shift modules MCP1 for the remaining channels, the module of the implemented MRF function for calculating various logical functions bitwise from two or three codes, alternately fed to the inputs of the logical channels.

An example of an input unit 1 is shown in FIG. 3 and contains a number of electronic keys 32, the inputs of which are supplied with bits of binary codes X1 ... X _n ... Xm ... X _k , and which, in turn, by the corresponding signal of the first decoder 33, they pass a specific binary code to the outputs Q1 ... Qn depending on the values of the address commands C12 ... C _e , elements and 34, the first inputs of which receive bits of information signals X _{k + 1} ... X _{R, the} second inputs of the elements And34 are connected to the outputs of the second decoder 35 and depending on the values of the address commands C _{e + 1} ... C _j , using sight of a specific output of the decoder 35, the corresponding bit of information appears at the output of the OR element 36.

An example of a switching and computing unit 2 is shown in Fig. 4, it consists of a decoder 37 connected by inputs to the program block 5, the first two outputs the decoder 37 connected to the inputs of the first and second elements And 38 and And 39, and the second two outputs to the inputs of the element 2-2-2-2I-4 OR 40, the output of which is connected to the input of the EXCLUSIVE OR 41 element, the output of the latter is connected to the input of the third element I42, connected by the output to the control input of the memory cell 43, the information input of which is connected to the output of the OR element 44, first entry of this email ment connected to the output of the fourth AND gate 45, a second input connected to the output of the fifth AND gate 46 having a first input connected to the output of NOT 47, AND-NO element 106, the sixth AND gate 108, with their connections.

An example of a random access memory unit 3 is shown in Fig. 5 and it contains rows of memory cells 48, in one of these rows of memory cells are written the values of the binary code T1 ... T _n coming from the outputs, modules of the RFM, through a switch 77 of block 7, by pulse d2 and command e3 received at the inputs of the first element And 70 from blocks 6 and 7 and the output of element 81, forming a pulse of permission to write to the rows of memory cells 48. The binary code is read from the outputs of one of the rows of memory cells 48 by electronic keys 50 to the command with the output of the decoder 49, depending on the beginning of addresses C'12 ... C'e, a series of single-bit memory cells 51, where the results of intermediate calculations of Boolean functions in block 2 are written, by the command from block 2 and at the address determined by the output of the second decoder 52 in accordance with the address commands C ′ _{е + 1} ... С ′ _j , reading from memory cells 51 occurs through AND 53 elements and OR 54, at the address determined by the output of the second decoder 52. Writing and reading takes place at different clock cycles.

An example of the structure of the output unit 4 is shown in Fig.6, it consists of rows of memory cells 55, where the values of binary codes from the outputs of the modules of the RFM of the logical channels are written, through the switch 77 of the unit 7, by command from the output of the And 71 element, to the input of which the signals d2 and e4 from block 6 and element 81 and to the addresses determined by the outputs of the decoder 56, the values of B′1 ... B ′ _n at the outputs of the rows of memory cells 55 can go to the inputs of digital-to-analog converters and then in the form of analog signals, for example, inputs of electrical actuators MOV, from a number of memory cells 57, into which the results of calculations of steering functions are written in the form of bits of information from block 2 by command F2, also from block 2 and at the address determined by the output of the second decoder 58, depending on the values of C _{e + 1} . ..C ′ _j .

и адресные с₁₂...с_j шины и связаны с выходом ключа 105 блока 97. Счетчик импульсов 59 содержит счетные триггеры 84, связанные в многоразрядный двоичный счетчик, их прямые выходы являются выходами счетчика 59, счетный вход первого триггера 84 служит счетным входом счетчика 59, a R и S входы счетных триггеров 84 подключены к выходам электронного ключа 85, входящего как и элементы ИЛИ 110 и И 109 в состав счетчика 59. Информационные входы ключа 85 связаны с вторыми шинами блока условных переходов 86 и, через второй ключ 111, с общими шинами 80, а вход включения ключа 85 соединен, через элемент И 109 и элемент ИЛИ 110 с выходом модуля управления 96 блока 86 и с выходом шестого элемента И 108 блока 2, Взаимосвязь входов С′12...С′_j, электронного ключа 85 с его выходами представлена ниже:The program unit 5 (Fig. 7/) contains a pulse counter 59, the counting input of which receives signals from the output of block 97, a read-only memory with memory cells / ROM / 60, for recording the program and its reading to the addresses at the outputs of the counter 59 associated with the inputs of the ROM 60, the program is read from the outputs of the ROM 60 connected to the inputs of the electronic key 61, the outputs of which are the outputs of block 5, contain command / control /

and address lines ₁₂ ... with _j buses and are connected to the output of the key 105 of block 97. The pulse counter 59 contains counting triggers 84 connected to a multi-bit binary counter, their direct outputs are the outputs of the counter 59, the counting input of the first trigger 84 serves as the counting input of the counter 59, a R and S the inputs of the counting flip-flops 84 are connected to the outputs of the electronic key 85, which, like the OR 110 and AND 109 elements, are part of the counter 59. The information inputs of the key 85 are connected to the second buses of the conditional transition block 86 and, through the second key 111, with shared buses 80, and key enable input 85 connected through the element And 109 and the element OR 110 with the output of the control module 96 of the block 86 and with the output of the sixth element And 108 of the block 2, The relationship of the inputs C′12 ... C ′ _j , the electronic key 85 with its outputs is presented below:

where R ′ ₁ ... R ′ _j and S ′ ₁ ... S ′ _{j are the} electronic key outputs associated with the R and S inputs of the counting triggers 84, respectively;

C ′ ₁₂ ... C ′ _j code values on the second dyne 90, block 86;

значение выхода модуля управления 96, блока 86;

the output value of the control module 96, block 86;

является инверсией С. Счетчик импульсов 59 представлен схемой на фиг.11.

is inversion C. The pulse counter 59 is represented by the circuit in FIG. 11.

An example of a synchronization block 6 is shown in Fig. 8, it contains a first counting trigger 62 connected by a direct output to the And 63 element, and an inverse output to the first inputs of the And 64 and And 65 elements, the second input of the last connected to the output of the And 66 element, whose inputs are connected with the direct output of the second counting trigger 67 and with the output of the inverter 68, the input of the latter together with the input of the trigger 62 are connected to the rectangular pulse generator 69. The operation of block 6 is illustrated by diagrams in Fig.9.

The conditional transition block 86 is shown in FIG. 12 and consists of a pulse counter 87 having installation inputs connected to the first buses 88, a third electronic key 89 connected by inputs to the outputs of the pulse counter, and outputs with second buses 90 of the first and second rows of memory cells 91 and 92, connected by inputs to the first buses, and outputs to the inputs of the first and second rows of electronic keys 93 and 94, the outputs of the latter are connected to the second buses, the fourth electronic key 95, connected by the inputs to the first buses, and the outputs with second buses of block 86, control module 96, inputs connected to two additional control buses coming from block 5, a ′ ₁ and a ₁ , as well as with two command buses C7, C8, three address buses C12, C13, C14 and c the outputs of blocks 2, 6, the outputs of module 96 are connected to the control inputs of the counter 87, with two rows of memory cells 91, 92, with three electronic keys 89, 93, 94 and through the elements OR 110 and OR 109, with the input of the key 85.

In block 7, the lower output of the decoder 9, there is an inversion of the output D2. We make a reservation that all triggers and memory cells are triggered on the trailing edge of the pulses arriving at their control or counting inputs and are reset to "0" before the device starts.

The principle of operation of block 2 is known; it consists in implementing the Boolean functions AND, OR, NOT, with C3 = 0, and the function EXCLUSIVE OR, with C3 = 1, sequentially in clock cycles, as well as in controlling the corresponding processes in blocks 3 and 4. Under activation of an output or signal implies the appearance of a logical "1".

In the above examples of the operation of the device without block 86, it was assumed that the electronic key 95 is open and the values of the codes C12 ... C _j and C 12 ... C _j coincide with a ₁ = 1.

The structure of control module 96 is a memoryless machine and its analytic interpretation in the form of Boolean functions connecting its inputs a ′ ₁ , a ₁ ... a ₆ , α and Z with its outputs Y ′ ′ ₁ ... Y ′ ′ ₈ given below:

where a ′ ₁ is the input signal coming from the first additional bus from block 5 to the input of module 96,

and ₁ is the input signal coming through the second additional bus from block 5 to the input of module 96,

a ₂ , a ₃ - input signals received via the command buses C7, C8 during operation of the module 96 in the mode of recording information in the pulse counter 87, or in the memory cells 91, 92,

and ₄ , a ₅ - input signals arriving through the bus 88, through the address bus, for example C12, C13, in the read mode of information about the outputs of the pulse counter 87, memory cells 91, 92, through electronic keys 89, 93, 94,

and ₆ - the input signal coming through the address bus, for example C14, and defining one of the conditions for recording / adding / "1" to the counter 87,

α is the input signal coming from the output of the trigger 43 of block 2,

Z is the input signal coming from the output of element 63 of block 6,

Y ′ ′ ₁ , Y ′ ′ ₂ , Y ′ ′ ₃ - output signals supplied to the recording control inputs respectively to counter 87 and to memory cells 91, 92,

Y ′ ′ ₄ , Y ′ ′ ₅ , Y ′ ′ ₆ - output signals received at the inputs of the inclusion of electronic keys 89, 93, 94 in the mode of reading information from the outputs of the counter 87 and memory cells 91, 92,

Y ′ ′ ₇ - output signal supplied to the counting input of the counter 87

Y ′ ′ ₈ is the output signal coming through the elements, OR 110 and AND 109, to the input of the inclusion of the electronic key 85, the information inputs of which are connected to the buses 90, and the outputs with the installation inputs of the counting triggers 84.

At the same time, i.e. on one cycle, only one of the outputs Y ′ ′ ₁ ... Y ′ ′ _{6 is} activated, taking the value of logical “1”.

Note that the electronic key 95 in block 86 is controlled by a signal passing through an additional control bus a ′ ₁ , which is connected to the control input of the fourth electronic key 95 and block 5.

на входе элемента 16, связанного с выходом блока 5, определяет реализуемую элементом 16 функцию, при

реализуется функция ИЛИ.With a single signal value on the second additional control bus a ₁ at the outputs D ₁ , D ₂ , D _{3 of the} decoder 9 of block 7 there are logical zeros. Value

at the input of element 16, associated with the output of block 5, determines the function realized by element 16, when

the OR function is implemented.

блока 5, к инверсному выходу триггера 102, и к определенному выходу блока синхронизации, на котором появляется импульс в третьей четверти такта, выходы первого электронного ключа 98 соединены с установочными входами счетчика импульсов 100, счетный вход которого связан с выходом второго элемента И 101, входы последнего подключены к выходу блока синхронизации 6 и прямому выходу триггера 102, инверсный выход которого соединен с первым входом элемента И 103, второй вход последнего связан с соответствующим выходом блока синхронизации 6, выход третьего элемента И подключен к счетному входу счетчика импульсов 59 программного блока 5, выходы двоичного счетчика импульсов 100 соединены с входами модуля памяти 104, выходы которого связаны соответственно с информационными входами второго электронного ключа 105, управляющий вход последнего подключен к прямому выходу управляемого триггера 102 блока подпрограмм 97, инверсный выход управляемого триггера соединен и с управляющим входом электронного ключа 61 программного блока 5, управляющий и информационный входы управляемого триггера 102 связаны соответственно с выходами блока синхронизации 6 и с выходом модуля памяти 104, выходы второго электронного ключа 105 блока подпрограмм подключены к соответствующим выходам /шинам/ электронного ключа 61 блока 5. В отключенном состоянии ключи 61 и 105 имеют высокий импеданс сопротивления на своих выходах.The block of routines 97, represented by the circuit in Fig. 13, contains a first electronic key 98, a binary pulse counter 100, first and second elements AND 99 AND 101, a controlled trigger 102, a third element And 103, a memory module 104, a second electronic key 105, the information inputs of the first electronic key 98 are connected about the corresponding address outputs / buses / program unit 5, the control input of the first electronic key 98 is connected to the output of the first element And 99, the inputs of which are connected to the additional bus

unit 5, to the inverse output of the trigger 102, and to a specific output of the synchronization unit, on which a pulse appears in the third quarter of the clock cycle, the outputs of the first electronic key 98 are connected to the installation inputs of the pulse counter 100, the counting input of which is connected to the output of the second element And 101, the inputs the latter are connected to the output of the synchronization unit 6 and the direct output of the trigger 102, the inverse output of which is connected to the first input of the AND element 103, the second input of the latter is connected to the corresponding output of the synchronization unit 6, the output of the third element And is connected to the counting input of the pulse counter 59 of the program unit 5, the outputs of the binary pulse counter 100 are connected to the inputs of the memory module 104, the outputs of which are connected respectively to the information inputs of the second electronic key 105, the control input of the latter is connected to the direct output of the controlled trigger 102 of the block of subprograms 97 , the inverse output of the controlled trigger is connected to the control input of the electronic key 61 of the program unit 5, the control and information inputs of the controlled trigger 102 are connected respectively -retarded with outputs the synchronization unit 6 and from the output of the storage unit 104, outputs the second electronic switch unit 105 routines are connected to corresponding outputs / buses / electronic key 61 block 5. In the open position the keys 61 and 105 have high resistance impedance at its outputs.

The interrupt block 115 is shown in Fig. 14 and contains triggers for receiving interrupt signals 116, the outputs of which are connected to the inputs of the interrupt sequence selector 117, connected by the outputs to the inputs of the encoder 118, connected by its outputs to the inputs of the OR element 119 and to the inputs of the read-only memory, then ROM 120 connected to the outputs of the electronic key 121, the control input of which is connected to the output of the AND element 122, the four inputs of the latter are connected to the output of the element NOT 123, the input of which is connected to the input bus and the corresponding input to the AND elements 99, to the output of the OR element 119, to the corresponding output of the synchronization block and to the inverse output of the controlled trigger 102 of the block of subprograms 97, the control inputs of the triggers 116 are connected to a specific output of the synchronization block, the outputs of the electronic key 121 are connected to the setting inputs of the pulse counter 100 block of routines.

Module 117 is a memoryless machine and implements Boolean functions.

- входные сигналы, поступающие с выходов триггеров 116 на соответствующие входы модуля 117,

- сигналы формирующиеся на соответствующих выходах модуля 117.Where

- input signals coming from the outputs of the triggers 116 to the corresponding inputs of the module 117,

- signals generated at the respective outputs of module 117.

The information inputs of triggers 116 receive request signals to interrupt the main program recorded in block 5 from, for example, emergency sensors, a control panel, etc.

A multi-bit memory cell 124 and a multi-bit electronic key 125 are shown in FIG. 10, while the information and control inputs of the cell 124 are connected to common buses T1 ... T _n and to the first of the two control buses entered, and the outputs are connected to the information inputs of the key 125 the control input of which is connected to the second control bus entered, and the outputs to the address buses at the output of the key 61 of block 5.

The operation of the device consists in calculating Boolean functions by bits in block 2, with simultaneous implementation of operations with multi-bit binary codes in block 7 and, if necessary, the device ensures the joint operation of blocks 2 and 7, for example, in case of comparing two binary codes. The device operates on the clocks generated in block 5.

. Сравним два двоичных числа А1 и А2, при А1=А2 и для примера число А1 равно числу А2 и оба выражены двоичным кодом 11001011. Допустим число A1 находится в блоке 1 в виде Х1...Х_n, где n=8, а число А2 хранится в блоке оперативной памяти 3 в значениях Р1...Р_n, где n=8 и блок 7 имеет восемь логических каналов. Равенство чисел определим методом алгебраического сложения числа А1 и отрицательного числа А2, представленного в дополнительном коде, т.е. инвертировав его и прибавив "1" к младшему разряду. Примем, что А2 является инверсией А2, а С′=1 и С′′=1.We explain the operation of the device with a few examples. We assume that

. Compare the two binary numbers A1 and A2, with A1 = A2 and for example, the number A1 is equal to the number A2 and both are expressed in binary code 11001011. Suppose the number A1 is in block 1 in the form X1 ... X _n , where n = 8, and the number A2 is stored in the RAM block 3 in the values P1 ... P _n , where n = 8 and block 7 has eight logical channels. The equality of numbers is determined by the method of algebraic addition of the number A1 and the negative number A2, presented in the additional code, i.e. by inverting it and adding “1” to the low order. We assume that A2 is the inverse of A2, and C ′ = 1 and C ′ ′ = 1.

At the first clock cycle, the values X1 ... X8, with the corresponding values C4 ... Ce, and e1 = 1, will arrive in the form of Q1 ... Q8 at the inputs T1 ... Tn of the elements 23 of all channels, from block 1 to block 7, where, under the action of the commands C9 ... C11, the decoder 8 of block 7 activates the output e1 and the number A1, through the elements 23 of all channels, when the output of the OR element 74 is activated, it will go to the inputs of the elements 24 and with D1 = 0, e2 = 0, d1 = 1, the value of the number A1 is written to the counting triggers 29, because K1 = 0 and K2 = 0, and ′ ₁ = 1.

, при этом на выходах триггеров 29 всех каналов устанавливаются единичные значения.On the second, also, with the corresponding signals C4 ... Ce and e2 = 1 in block 3, the upper output of the decoder 49 and the number A2 in the form of values P1 ... P _{n are} activated, from the output of the electronic key 50 goes to the inputs of the element 23 of all channels of the block 7 and for e2 = 1, D1 = 1, e1 = 0, K1 = 0 and K2 = 0, the value of the inversion of the number A2 goes to the counting inputs of the counting triggers 29 of all channels in the third quarter of a clock cycle with d1 = 1 and the EXCLUSIVE OR bitwise function is implemented for numbers A1 and

, while the outputs of the triggers 29 of all channels are set to single values.

On the third step, to complete the translation of the number A2 into the additional code, the C1 ... C11 commands activate output D1 and output e5 of decoders 9 and 8 of block 7 and logical "1" from the output of element 14 through the elements OR 13 and AND 27 of the first the channel will go to the second and first inputs of the elements OR 25 and AND 26, the second input of the last receives "1" from the output of the trigger 29, while the logical "1" from the output of the AND 26 element, through the OR element 31 of the first channel, appears at the input of the element And 27 of the second channel and further, through the elements And 27, And 26 and OR 31 of the subsequent channels, the specified logs the logical “1” will appear at the outputs of the OR elements 31 of all channels of block 7 and in the third quarter of the clock cycle with a pulse d1, all the counting triggers 29 of all channels will switch to the logical “0” state at the output, i.e. we got the result of the difference of two equal numbers, while the triggers 30 of all channels switched to state "1", information was recorded from the output of the trigger 30 of the last channel to the memory cell 17, according to the signal from the output of the And element 20 of block 7.

, логический "0" с выхода элемента ИЛИ16, при соответствующих сигналах С9...С11 по команде е6 с выхода дешифратора 8 блока7, поступает, через элемент 40 на вход элемента 41 блока 2, где инвертируется при С1=1 и затем в третьей четверти такта, когда d1=1 и С2=1, а С3=0 единичное значение сигнала с выхода элемента ИЛИ 44 запишется в ячейку памяти 43 по команде с выхода элемента И 42.At the fourth measure, with

, logical "0" from the output of the OR16 element, with the corresponding signals C9 ... C11 by the command e6 from the output of the decoder 8 of the block7, it enters, through the element 40, the input of the element 41 of the block 2, where it is inverted at C1 = 1 and then in the third quarter clock cycle, when d1 = 1 and C2 = 1, and C3 = 0, a single signal value from the output of the OR element 44 is written to the memory cell 43 by a command from the output of the And 42 element.

On the fifth step, the logical "1" from the output of cell 43 with certain commands C4 ... C6, activating the lower output of the decoder 37 of block 2 and the output of the I39 element, at the moment d2 = 1, will be written to the value determined by the values С _{е + 1} ... С _j memory location 57 of the output unit 4, as information that A1 = A2.

дешифратора 9 связан с входом И 20, блока 7.Consider the second example, when A1 <A2 and A1 = 11001011, and A2 is 10011011. Consider the output

the decoder 9 is connected to the input And 20, block 7.

At the first beat, by analogy with the first example, the number A1 is recorded in the counting flip-flops 29 by bits in each channel of block 7.

меняют состояние счетных триггеров 29 на противоположное и на выходе триггеров 29 появляется результат, равный

, т.е. 10101111, при этом в втором канале счетный триггер 29 за два такта дважды поменял свое состояние с "0" в "1" и снова в "0", что привело к изменению состояния второго счетного триггера 30 с нулевого в единичное и фактически произошла фиксация факта образования переноса из второго разряда в третий разряд ИЛИ из второго канала в третий, с этой целью и были введены счетные триггеры 30 во все каналы блока 7.At the second step, with e1 = 1, D1 = 1, the inversion of the number A2, i.e. 01100100 arrives at the inputs of the elements And 28 and the pulse and d1 = 1, in the third quarter of the cycle, the unit values of the digits of the number

change the state of the counting triggers 29 to the opposite and at the output of the triggers 29 a result equal to

, i.e. 10101111, while in the second channel, the counting trigger 29 twice changed its state from “0” to “1” and again to “0” in two steps, which led to a change in the state of the second counting trigger 30 from zero to one and fact was fixed the formation of transfer from the second discharge to the third discharge OR from the second channel to the third, for this purpose counting triggers 30 were introduced into all channels of block 7.

On the third step, according to the signals D1 and e5, the logical "1" through the elements AND 14, OR 13 and AND 27 of the first channel is fed to the second and first inputs of the elements OR 25 and AND 26 of the first channel and from the output of the last element And 26 through the element OR 31 logical "1" goes to the input of element 27 of the second channel and then to the inputs of the elements OR 25 and AND 26, from the output of the element OR 31 logical "1", as a result of the transfer, which was mentioned above / on the second clock / entered the input of the element And 27 of the third channel and further to the inputs of the elements And 28 and And 26, with the output of the last element logical "1", h Through the OR element 31 it enters the input of the And element 27 of the fourth channel and then to the inputs And 26 and And 28, then the transfer does not pass, at the outputs of triggers 29 and 30, logical zeros. Thus, the And 26 to OR 31 elements provide end-to-end transfer from the channel / discharge / to the channel / discharge /, when there is transfer, then in the third quarter of the clock cycle with d1 = 1, the states of the triggers 29 in the first four channels and at the outputs of all the triggers 29 of all channels, the result of the algebraic sum A1 +/- A2 / is set in the additional code 01011111, at the same time, the signal from the output of element 20 will record information / 0 / from the output of the trigger 30 of the last channel, through the OR element 31 to the memory cell 17 of block 7, while value o yes trigger 30 indicates that A1 <A2, and obtained a result of the algebraic sum +/- A1 A2 / twos complement. At the same beat in block 2, with C1 = 1, C2 = 1, C3 ... C6 equal to "0", through the elements 46 and OR 44, the logic 1 passes to the information input of cell 43, which at zero outputs of the decoder 37 is recorded in cell 43 by the signal from the output of element 41, through element And 42 to the control input of cell 43, with d1 = 1.

At the fourth step, according to the signal from the output of the decoder 8 of block 7, е7 = 1, the value L2 = 1, from the inverse output of the trigger 30 of the last channel, it goes to the output of element 40 of block 2 and then, when C1 = 1, the output of element 41 is "0" and cell 43 does not change, remaining "1".

значение L1=1 с выхода элемента ИЛИ16, при е6=1 поступит, через элемент 40, на вход элемента 41 и при С1=1 на выходе последнего будет "0" и единичное значение ячейки 43 не изменится, мы получили результат вычисления функции L2·L1, подтверждающий, что А1<А2.At the fifth measure with

the value L1 = 1 from the output of the element OR16, for e6 = 1 it will go through element 40 to the input of the element 41 and for C1 = 1 the output of the last will be “0” and the unit value of cell 43 will not change, we got the result of the calculation of the function L2 · L1, confirming that A1 <A2.

At the sixth step, the result of computing the function L2 · L1 from the output of cell 43 of block 2 with the corresponding command from the output of decoder 37 and with d2 = 1, i.e. in the second quarter of the clock, on command from the output of the I39 element, it will be written to the output unit 4, in one of the memory cells at the address C _{e + 1} ... C _j .

и если бы А1>А2, то функция L1·

равнялась "1".Next, we should calculate the function L1

and if A1> A2, then the function L1

equal to "1".

Let us return to the third step, when we received the result of the algebraic sum of the numbers A1 and -A2, in the additional code and continue for a new example, performing operations to solve the problem of determining the final result of calculating the sum A1 +/- A2 /.

To do this, on the fourth clock in block 7, the result obtained from the outputs of flip-flops 29 of all channels with C ′ = 1 is written to the RAM block 3 by a signal from the output of element And 70 with e3 = 1 and d2 = 1, in a series of memory cells defined by the values C12 ... C _e and the output of the decoder 49. Simultaneously, under the action of the signal q1 = 1 from the output of the I21 element, all the countable triggers of all channels are reset to "0", while the output of the OR element 22 has a logical "1" in the form of a pulse, because C ′ ′ ′ = 1.

On the fifth step, the information recorded at the previous step from block 7 to block 3, in accordance with the address C12 ... С _e , is read from a number of electronic keys 50 by the signal from the output of the decoder 49 and when the output e2 of the element 81 and the decoder 8 of the block 7 is activated , this information through the elements 23 of all channels goes to the inputs of the elements 24, where all the bits are inverted by the signal from the output of the OR element 15, with D2 = 1 and received, through the elements OR 25 with K1 = 1, to the counting inputs of the triggers 29, while single bits change the state of the triggers 29, at the output Odes of which the inverse value of the specified information is set, i.e. 10 100 000.

и на инверсном выходе ячейки 17 сохранится единичное значение, означающее, что результат вычисления является отрицательным числом /знаковый разряд/.At the sixth step, the logical “1” is added to the result in the form of a code 10100000 by entering from the output of element 19, Д2 = 1 of block 7 a unit value K1, which comes from the output of element OR 13, through element And 27, with e5 = 1 at the input element And 28 and the input of element And 26, given that at the second input of element And 26 there is "1", from its output a single signal, through elements OR 31 and And 27 of the second channel will go to the input of element And 28 of the second channel in the third a quarter of a cycle with d1 = 1, at the outputs of triggers 29, the result of calculating A1 +/- A2 / appears in direct e 01100000, the state of memory cell 17, the block 7 does not change

and at the inverted output of cell 17, a single value is stored, meaning that the result of the calculation is a negative number / sign digit /.

At the seventh step, the result obtained at the previous step and the sign discharge from the outputs of the tigers 29 through the MRF module and from the inverse output of the cell 17 are recorded under the action of signals С = 1, е4 = 1 and d2 = 1 and, accordingly, the unit output of the element And 71, in a group of memory cells 55 of the output block 4.

The bit shift module MCP1 for each logical channel from "n" logical channels, except the first and last in the multi-channel operating unit 7, has two outputs U1 and y2 and inputs designated by t1, C ′, C ′ ′, b ′, b ′ ′, E6, its operation is determined by the following Boolean functions:

связан с выходом первого дешифратора 8, блока 7.where the first output Y′1 is connected to the third input of the first OR element 25 of this logical channel, the second output Y′2 is connected to the fourth input of the OR element 25 of the subsequent channel, input b ”is connected to the output of the counting trigger 29 of this logical channel, input b ′ is connected with the output of the first counting trigger 29 of the subsequent logical channel, the inputs C ′ and C ′ ′ are connected to the corresponding outputs of the program unit 5, t1 is connected to the output of the element NOT 76,

connected to the output of the first decoder 8, block 7.

The shift module MCP2 of the first logical channel of block 7 has three outputs U1, U2, U3 and six inputs, denoted by b ₁ · b ₂ · t1, c ′, c ′ ′ and e6 and its operation is determined by Boolean functions:

подключен к соответствующему выходу дешифратора 8 блока 7.where the first output Y1 is connected to the fourth input of the OR element 25 of the first logical channel, the second output Y2 is connected to the third input of the OR element 25 of the same channel, the third output Y3 is connected to the fourth input of the OR element 25 of the second logical channel, input b ₁ is connected to the output of the first counting trigger 29 of the first logical channel, input b _{2 is} connected to the output of the counting trigger 29 of the second logical channel of block 7, inputs C ′ and C ′ ′ are connected to the corresponding outputs of program block 5, input t ₁ is connected to the output of element NOT 76 and input

connected to the corresponding output of the decoder 8 block 7.

функционирует в соответствии с булевой функцией:The bit shift module MCP3 of the last logical channel has one output y ′ ′ ′ ₁ and four inputs, denoted by b _n , С ′ ′, t1 and

functions in accordance with the boolean function:

where the output y ′ ′ ′ _{1 is} connected to the third input of the OR element 25 of the last logical channel, the input b _n is connected to the output of the trigger 29 of the last channel, the input C ”is connected to the corresponding output of block 5, the input t _{1 is} connected to the output of the element NOT 76 of block 7 , the input e6 is connected to the corresponding output of the decoder unit 7.

означает инверсию сигнала е6.Recall that all triggers are triggered by the trailing edge of the pulse, for example, a signal

means inversion of the e6 signal.

The code bits are shifted down from the first to the “n” channel by the command C ′ = 1 with C ′ ′ = 0, t ₁ = 1, and e6 = 0. In this case, provided that all the counting triggers 29 contain a certain code for the MCP2 module, in accordance with functions (3) and (5), logical 1 will be established at output U1 if b ₁ = 1, and passing through the OR element 25, the logical "1" will be at the input of the element And 28 and at the end of the pulse d ₁ at the output of the trigger 29 of the first channel will be set to "0". At the same time, when the signals at the inputs b ₁ and b _{2 are} inequalized, the output U3 is activated and the logical "1" is fed to the input of the element And 28 and at the end of the pulse d1 the output of the trigger 29 of the second channel will take the opposite value, i.e. the value that was at the output of the trigger 29 of the first logical channel. At the same time, in the MCP1 modules, in accordance with function (2), in case of inequality, the value of the signals at the logical outputs of the triggers 29 of this and the subsequent channels of block 7 activates the output U'2 in all MCP1 modules and the logical "1" through the corresponding elements OR 25 will go to the inputs of the elements AND 28 of the corresponding logical channels and at the end of the pulse d ₁ at the output of the trigger 29 of each subsequent channel, the output value of the trigger 29 of this logical channel will appear, i.e. there will be a shift down the digits of the code recorded earlier in the triggers 29, starting from the third logical channel.

The shift of the digits of the code recorded in the triggers 29 up takes place in the presence of the command C ′ ′ = 1, when C ′ = 0, e6 = 0, t1 = 1, Then, in accordance with functions (1) ... (6), they can be activated the outputs U2 in the MCP2 module, Y′1 in the MCP1 module and the output Y ^''' 1 in the MCP3 module, while the output U2 is activated if the input signals b ₁ and b ₂ at the corresponding inputs of the MCP2 module are not equal, in this case, through OR element 25 logic I will enter the input of element I28 of the first logical channel and on the trailing edge of the pulse d _{1 the} trigger 29 of the first channel will take on the value of the trigger 29 of the second log channel At the same time, i.e. at the same cycle, for any MCP1 module, if the signals at its inputs b ′ and b ″ are not equal, the output U'1 and logic “1” are activated, through the OR25 element it is fed to the input of the element 28 of this channel, where the corresponding MCP1 module is located and the moment of the end of the pulse d ₁ at the output of the trigger 29 of this channel sets the output value of the trigger 29 of the subsequent logical channel. At the same time, if b _n = 1, the output y ′ ′ ′ _{1 of} the MCP3 module is activated and logical “1” appears at the input of element And 28 and, at the end of pulse d _1, trigger 29 of the last logical channel goes into state “0”. Thus, there will be a shift in the digits of the code recorded in the triggers 29 from the bottom up.

связаны с выходами соответственно триггеров 29 и 30 в каждом логическом канале, а входы C′ и С′′ соединены с соответствующими командными шинами программного блока 5. Модуль МРФ содержится в каждом логическом канале блока 7. Выход модуля МРФ является выходом соответствующего логического канала, обозначен через В_j и каждый из них подключен к определенному входу электронного выключателя 77 и соответствующему входу элемента 16 блока 7. Работа каждого модуля МРФ определяется булевой функциейEach module of the RFM bit-by-bit implementation of Boolean functions from binary codes has four inputs and one output. MPF module inputs

are connected to the outputs of triggers 29 and 30, respectively, in each logical channel, and the inputs C ′ and C ′ ′ are connected to the corresponding command buses of program block 5. The MPF module is contained in each logical channel of block 7. The output of the MPF module is the output of the corresponding logical channel, indicated through B _j and each of them is connected to a specific input of the electronic switch 77 and the corresponding input of element 16 of block 7. The operation of each module of the RFM is determined by a Boolean function

Suppose you want to determine the bitwise logical AND, bitwise OR, and bitwise EXCLUSIVE OR from three binary codes stored either in the input block or in the operational block and write the result to the output block or to the random access memory block. of all logical channels to “0”, we write / feed /, one by one, as described above, the indicated codes into countable triggers 29 of the logical channels, Then, in accordance with function (7), with the values of the commands С ^′ = 1 and С ′ ′ = 0 at the outputs MRF modules b the results of the calculation of the function EXCLUSIVE OR / bitwise / from three binary codes can be found, which can be written to block 3 by the command e ₃ = 1. Next, at the next clock with C = 1 and C ′ = 1, the results of the bitwise calculation the OR function of the three indicated codes and it can also be written to block 3 on the same clock cycle with e ₃ = 1. Then, at the third clock cycle with C ′ = 0 and C ′ ′ = 0, the results of computing the bitwise and from the same three codes will take place at the outputs of the MRF modules and can be written in block 3 with e ₃ = 1. Thus, the introduced MYFF modules allow one-by-one calculation of the indicated logical functions directly from the three codes, feeding them to the logical channels once, which increases the speed of the device when calculating the indicated functions.

программного блока 5 и с одной Т1 из общих шин 80, а выходом с первым входом элемента И 73, второй вход которого соединен с выходом элемента И 74, выход элемента И 73 подключен к первым входам всех элементов И 23 всех логических каналов, позволяет при

записывать информацию в триггеры 25 только при T1=1.The OR element 107 introduced into block 7 is connected by inputs to the corresponding output

program block 5 and with one T1 from the common buses 80, and the output with the first input of the element And 73, the second input of which is connected to the output of the element And 74, the output of the element And 73 is connected to the first inputs of all elements And 23 of all logical channels, allows

write information to triggers 25 only with T1 = 1.

A single value of the direct output of the memory cell 17 in block 7 means that there is a transfer, for example, after arithmetic addition of n bits of two binary numbers to the next n + 1 bit of the indicated numbers, the transfer value is activated when D3 = 1 at the output of the decoder 9 of block 7 and passes through the element OR 13 to the input of AND element 27 of the first logical channel of block 7.

The operation of the block conditional transitions in the proposed device will explain with examples.

Suppose that in one of the program fragments it is necessary to select odd numbers from the set of numbers represented in binary code and stored in input block 1 and place them in the memory cells of block 3 at addresses starting from code A and then in order with a difference of unit.

We will determine the odd numbers by the value of the least significant bit T1, which arrives at the information input of element 107, block 7.

, произойдет запись кода А в счетчик 87 из блока 5 по шинам С12...Сj.At the first step of the implementation of the specified program fragment at

, code A will be written to counter 87 from block 5 via buses C12 ... Сj.

=0 и значении Т1=1, указанное нечетное число на этом же такте, при определенных командах С9...С11, запишется в триггеры 29 логических каналов блока 7 и другом такте под действием команд С1...С6 логическая "1" запомнится в триггере 43 блока 2. На следующем такте при соответствующих сигналах С9...С11, С', С» и α=1,

значение первого числа с выходов модуля МРФ логических каналов блока 7 запишется в блок 3, в ячейку памяти с адресом А, который будет считан из счетчика 87 при помощи ключа 89, а в конце этого такта по окончании импульса Z, с учетом

произойдет увеличение кода А на единицу, что является кодом следующего адреса для записи следующего нечетного числа из указанного множества. Далее, на следующем такте произойдет считывание второго числа из блока 1 и, если оно нечетно, то процесс повторится, а если оно четно и Т1=0, значения сигналов

и Т1=0 обеспечат логический нуль на выходах элементов ИЛИ 107 и И 73 блока 7, по этой причине на данном такте второе число не будет записано в триггеры 29 логических каналов, которые переведены в нулевое состояние на предыдущем такте, вместе с состоянием триггера 43 блока 2 при соответствующих сигналах С′′′, С1...С6. При этом на выходе элемента 16 блока 7 имеется "0" и поэтому состояние триггера 43 не меняется α=0,

поэтому считывание кода А+1 с выходов счетчика 87 не произойдет и указанный код не увеличатся на "1", Подобный процесс будет повторятся до тех пор, пока из входного блока 1 не будет считано нечетное число, которое запишется в блок 3 в ячейку памяти по адресному коду А+1 в соответствии с процессом, описанным в начале данного примера.At the next step, according to the method described above, the first number is read from input unit 1, let's say it is odd, and then, with

= 0 and a value of T1 = 1, the indicated odd number on the same clock, with certain commands C9 ... C11, is written to the triggers 29 of the logical channels of block 7 and another clock under the action of the C1 ... C6 commands, the logical "1" will be remembered in trigger 43 of block 2. At the next clock with the corresponding signals C9 ... C11, C ', C "and α = 1,

the value of the first number from the outputs of the MRF module of the logical channels of block 7 is recorded in block 3, in the memory cell with address A, which will be read from counter 87 using key 89, and at the end of this clock cycle at the end of pulse Z, taking into account

code A will increase by one, which is the code for the next address for writing the next odd number from the specified set. Further, on the next clock, the second number will be read from block 1 and, if it is odd, the process will be repeated, and if it is even and T1 = 0, the signal values

and T1 = 0 will provide a logic zero at the outputs of the elements OR 107 and AND 73 of block 7, for this reason the second number will not be written to the triggers 29 of the logical channels that are set to zero on the previous clock, together with the state of the trigger 43 of the block 2 with the corresponding signals C ′ ′ ′, C1 ... C6. Moreover, at the output of element 16 of block 7 there is “0” and therefore the state of trigger 43 does not change α = 0,

therefore, reading code A + 1 from the outputs of counter 87 will not occur and the indicated code will not increase by "1". A similar process will be repeated until an odd number is read from input block 1, which is written to block 3 in the memory cell by address code A + 1 in accordance with the process described at the beginning of this example.

With the introduction of block 86, it became possible to select and record information with certain attributes among a variety of different information, which extends the functionality of the proposed device compared to the prototype.

Another example. Suppose we should, for a certain value / sense / code word from the "M" of the available code words in block 1, go to program code A1, which would enable the signal device connected to the output of the corresponding memory cell of output block 4 and then go to program code A2.

записывается программный код А1, поступающий по шинам С12...С_j из программного блока 5. На следующем такте программный код А2 при,

записывается в ячейку памяти 92.At the corresponding cycle in the memory cell 91 of the block 86 at

program code A1 is written down via the buses C12 ... C _j from program block 5. At the next clock, program code A2 at,

recorded in memory 92.

происходит считывание из ячеек памяти 91 программного кода А1 и установка счетных триггеров 84, счетчика 59 блока 5 в состояние А1. На следующем такте реализуется программный код А1 и при соответствующих сигналах С1...С_j и a′₁=1 происходит запись "1" в соответствующую ячейку памяти выходного блока 4, куда подключено сигнальное устройство по условиям примера. На следующем такте под действием сигналов α=1,

и

через ключ 94, происходит считывание программного кода А2 из ячеек памяти 92 и его запись, через ключ 85, в триггеры 84 блока 5. Далее реализуется программа в соответствии с программным кодом А2, т.к. сравнивать следующие коды из "М" кодов нет смысла и таким образом сокращается число тактов при решении задачи, в зависимости от результатов сравнения кодовых слов. При этом повышается быстродействие устройства и появляется возможность решать смысловые задачи, расширяя сферу использования устройства.Suppose that a certain codeword value is stored in block 3 and at the next clock with the corresponding signals C1 ... C _j a ′ ₁ = 1, this code is counted from the outputs of block 3 and recorded in triggers 29 of the logical channels. At the next beat, one code from the “M” codes, under the action of the command and address signals C1 ... C _j and a ′ ₁ = 1, will be received at the inputs of triggers 29 of the logical channels and compared with the code previously recorded there, and if the codes match, then at the output of element 16 of block 7, “0” appears and at the next clock, with the corresponding signals C1 ... C6, “1” is written to trigger 43 of block 2. At the next step, under the action of signals α = 1,

the program code A1 is read from the memory cells 91 and the counting flip-flops 84, counter 59 of block 5 are set to state A1. At the next clock, program code A1 is implemented and, with the corresponding signals C1 ... C _j and a ′ ₁ = 1, “1” is written to the corresponding memory cell of the output unit 4, where the signal device is connected according to the conditions of the example. At the next step, under the action of signals α = 1,

and

through the key 94, the program code A2 is read from the memory cells 92 and written, through the key 85, into the triggers 84 of block 5. Next, the program is implemented in accordance with the program code A2, because it makes no sense to compare the following codes from the "M" codes, and thus the number of ticks in solving the problem is reduced, depending on the results of comparing the code words. This increases the speed of the device and it becomes possible to solve semantic tasks, expanding the scope of use of the device.

The number of pulse counters, rows of memory cells and the corresponding number of electronic keys in the block of conditional transitions can be any, and their communication and principle of operation are similar to those selected in the proposed device. The inclusion of a block of subprograms 97 in this device allows you to implement repeatedly repeating multi-cycle operations by accessing the same subprograms recorded in the memory module 104 of block 97. When an atom receives the address of the first clock of this subprogram and the call instruction to block 97 are recorded in the main program stored in program block 5.

и в третьей четверти такта по сигналу с выхода элемента И 99, двоичный код с адресных шин С12...С_q, где C_q≤C_j через открытый ключ 98 появится в третьей четверти такта на установочных входах счетчика импульсов 100 и установит его в положение при котором на выходах модуля памяти 104 появится программный код, соответствующий указанному выше 4 такту работы устройства и состояние "1" примет выход, связанный с входом управляемого триггера 102. На четвертом такте, в первой его четверти по сигналу из блока синхронизации 6, произойдет изменение состояния триггера 102, активизируется его прямой выход и подключит, через элемент И 101, соответствующий выход блока синхронизации к счетному входу счетчика импульсов 100 и отключит этот же выход, через элемент И 103, от счетного входа счетчика импульсов 59 блока 5. Одновременно по сигналам с прямого выхода триггера 102 закроется электронный ключ 61 блока 5 и откроется второй электронный ключ 105. Начиная с четвертого такта, соответствующие командные и адресные сигналы будут поступать на определенные входы всех блоков устройства из модуля памяти 104, через ключ 105.Let us explain the above with an example. Let us return to the third measure of the second example, when the result of the sum of the numbers A1 and -A2 in the additional code was obtained. In continuation of the example, starting at the end of page 20, on steps 4, 5, 6 and 7, operations were performed to finally determine the result of the algebraic sum A1 +/- A2 /, according to the program written in block 5, and a similar program should be written in block 5 at each subtraction with other numbers. In the case of using a block of subprograms 97, this part of the program as a subprogram can be written to the memory module 104 of block 97 once and accessed it each time the subtraction process is implemented with different numbers. Once again, back to the third measure indicated above, on which the entered bus is activated

and in the third quarter of the clock cycle from the output of the And 99 element, the binary code from the address lines is C12 ... C _q , where C _q ≤C _j through the public key 98 will appear in the third quarter of the clock at the installation inputs of the pulse counter 100 and set it to the position at which the program code appears on the outputs of the memory module 104 corresponding to the clock cycle of the device indicated above 4 and the state “1” will take the output associated with the input of the controlled trigger 102. At the fourth cycle, in the first quarter, according to the signal from synchronization block 6, trig state change Era 102, its direct output is activated and connects, through the And 101 element, the corresponding output of the synchronization block to the counting input of the pulse counter 100 and disconnects the same output, through the And 103 element, from the counting input of the pulse counter 59 of block 5. Simultaneously by signals from the direct of the output of trigger 102, the electronic key 61 of block 5 is closed and the second electronic key 105 is opened. Starting from the fourth clock, the corresponding command and address signals will be supplied to the specific inputs of all blocks of the device from the memory module 104, through the key 105.

At 5, 6 and 7 clocks, the device operates according to a subroutine recorded in the memory module of block 97. At 8 clock cycles, the output of the memory module 104 associated with the information input of the controlled trigger 102 takes the value “0”, the values of the outputs of the trigger 102 change in the first a quarter of the eighth cycle, through the I101 and I103 elements, the counting input of the pulse counter 100 is disconnected from the corresponding output of the synchronization block and this output is connected to the counting input of the pulse counter 59 of block 5 and at the same time the electronic key 105 is turned off and The next operation of the device is in accordance with the program recorded in program block 5. It is obvious from the above that any repeating subprograms can be written once to the memory module 104 of the block of subprograms 97 and can be accessed repeatedly. This reduces the programming process and reduces the total number of memory cells required to store the program, compared with the prototype.

Introduction to the switching and computing unit 2 of the AND-NOT 106 element, in which the inputs are connected respectively to the fifth output of the decoder 37 and to the output of the memory cell 43, and the output is connected to certain inputs of the elements 23, 70, and 71 in blocks 7, 3 and 4, allows you to feed or block the supply of binary code through the And 23 elements in the logical channels of block 7, and also record or not record the results of operations on binary codes in blocks 3 and 4, depending on the output signal of cell 43, which extends the functionality when processing e codes device compared to the prototype, for example, when performing the operation of arithmetic division or logical choice between binary codes, etc. When block 97 is operating, the signal on bus a ′ ₁ is “1”.

The introduction of communication between the buses 80 of the communication system, designated through T ₁ ... T _n and through the second key 111 and the electronic key 85, the installation inputs of the counting triggers of the program unit 5, allows you to implement the program of work of the proposed device depending on the results of data analysis at the outputs of the modules MRF of all logical channels of block 7, carried out, at certain values of the commands C4 ... C6, in block 2, because commands to control the operation of keys 111 and 85 come from the output of element And 108 of block 2, which extends the functionality of the proposed device.

Block interrupt 115 operates as follows. When interrupt requests appear at the inputs of triggers 116, by a signal from the output of element 63 of block 6, these requests are recorded in triggers 116 and fed to inputs X1 ... X _{n of} module 117, where the most priority request is determined from the received requests. priority request signal appears on one of the outputs Y1 ... Y _n block 117, then it is encoded into a binary code in the encoder 118, and then the resulting binary code in ROM 120 reads out a previously recorded to the desired binary code for the start of the subroutine called priority of the millet and the desired binary code according to the signal from the output of the AND element 122, with single signals at the outputs of the elements 119 and 123, through the key 121, in the second quarter of the clock it will be installed in the counter 100, block 97 and then appears at the inputs of the memory module 104. At the output of the module 104 a logical “1” will appear, which is fed to the information input of a controlled trigger 102 and the last one, upon a signal from the output of element 68 of block 6, will establish a logical “1” on the entire direct output and from the output of element And 101 impulses begin to arrive at the counting input of the counter 100. binary code output counter Ika 100 reads the program from the memory module 104, previously written there for the implementation of the priority request, and this program through the electronic key 105 with K = 1 arrives at the command and address buses, while the key 61 closes, blocking the main program recorded in the program block 5 .

, поступающего по первой введенной шине управления, записывать двоичный, код с общих шин в ячейку 124 и затем при определенном сигнале

на второй введенной шине, связанной с управляющем входом ключа 125 и вторым входом управления электронным ключом 61 программного блока 5, указанный двоичный код с выходов ячейки памяти 124 поступает на адресные шины С12...Сj, выходящие из ключа 61 программного блока.The introduction of a multi-bit memory cell 124 and an electronic key 125 into the device allows the signal

entering via the first control bus entered, write binary code from common buses to cell 124 and then, with a certain signal

on the second bus entered, associated with the control input of the key 125 and the second control input of the electronic key 61 of the program unit 5, the specified binary code from the outputs of the memory cell 124 is supplied to the address lines C12 ... Cj coming out of the key 61 of the program unit.

а сигнал, поступающий на второй вход управления ключом 61 обозначим через

, так же как и вторую введенную шину управления. При

ключ 61 закрыт и на его выходах имеется высоки импеданс сопротивления, независимо от значения сигнала

. Если

и

то ключ 61 открыт для управляющих сигналов, идущих по управляющим шинам и закрыт для адресных сигналов, т.е. на выходах С12...С_j, ключа 61 имеется высокий импеданс сопротивления. В случае, когда K^′=1, а

ключ 61 открыт для всех сигналов, идущих по командным /управляющим/ шинам и по адресным шинам.The electronic key 61 operates as follows. Denote the signal received at the control input of the key 61 through

and the signal arriving at the second key control input 61 is denoted by

, as well as the second control bus entered. At

key 61 is closed and at its outputs there is a high impedance of resistance, regardless of the signal value

. If

and

then the key 61 is open for control signals going through the control buses and is closed for address signals, i.e. at the outputs C12 ... C _j , key 61 there is a high impedance of resistance. In the case when K ^′ = 1, and

key 61 is open for all signals traveling on command / control / bus and address bus.

The technical and economic effect of the present invention consists in expanding the functionality by organizing priority interruption of the main program and determining the address code depending on the value of the data on the shared buses, as well as reducing the volume of the main program when solving computational problems in comparison with the prototype.

Literature

1. Patent for the invention No. 2154852 from 08.20.2000

2. Patent for the invention No. 2174700 from 10.10.2001,

Claims (1)

A device for constructing programmable digital microprocessor systems, containing an input unit that receives signals from sensors and generates a specific code at its output, an output unit for recording the values of codes coming from all logical channels to memory cells and transmitting them through digital-to-analog converters to electrical actuating mechanisms , program unit, RAM unit, synchronization unit and switching and computing unit, consisting of an AND-OR element, an EXCLUSIVE OR element, five elements comrade AND, memory cells, elements OR and NOT, the first inputs of two AND elements AND-OR are connected respectively to the third and fourth outputs of the decoder, and the second inputs are connected to the output of the input unit connected by the first and second groups of inputs to the group of information outputs of the control object and with a group of address outputs of the program block, as well as to the output of the RAM block, the output of the AND-OR element is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to a specific output of the program block, the output is This EXCLUSIVE OR is connected to the first input of the third AND element connected to the second input with the corresponding output of the synchronization unit, and the output to the control input of the memory cell, and its information input is connected to the output of the OR element, the second input of which is connected to the output of the fifth AND element, the second input the latter is connected to a specific bus of the program unit, the first input of the fifth AND element is connected to the output of the element NOT, and the input of the last is connected to the second input of the fourth element And and with the corresponding bus of the program unit, the first input of the fourth AND element is connected to the inverse output of the memory cell, and its output is connected to the first input of the OR element, the direct output of the memory cell is connected to the information inputs of the output block and the RAM block, the first inputs of the first and second elements AND are connected to the first and second outputs the decoder, their second inputs are combined and connected to the corresponding output of the synchronization block, and the outputs are connected to the corresponding inputs of the output block and the RAM block to control the recording of information, many a per-channel operating unit containing a controlled element, nine AND elements, seven OR elements, the first and second decoders, a controlled memory cell and “n” parallel logical channels having the same structure, each of which contains an EXCLUSIVE OR element inside itself, the first one the second and third AND elements, the first and second OR elements, the first and second counting triggers, while in each logical channel of the multichannel operational block the output of the EXCLUSIVE OR logic element is connected to the first input m of the first OR element, the second input of which is connected to the first input of the first And element and to the output of the second And element, and the output is connected to the first input of the third And element, the output of the last is connected to the counting input of the first counting trigger, the output of which is connected to the second input of the first element And to the counting input of the second counting trigger, the output of the latter is connected to the first input of the second OR element, the second input of which is connected to the output of the first AND element, while the output of the first ele The OR element is connected to the second inputs of the elements EXCLUSIVE OR logical channels, the first and second inputs of the first OR element are connected respectively to the outputs of the first and second elements AND, and the two inputs of the first element AND are connected to one of the outputs of the second decoder and the output of the third OR element, the inputs of which connected to two corresponding outputs of the first decoder, the first input of the second AND element is connected to one of the inputs of the third OR element and with a specific output of the first decoder, the second input of the second element connected to the output of the seventh AND element, the first and second inputs of the second OR element are connected to the outputs of the sixth and seventh AND elements, and the third input to the output of the third AND element, the inputs of which are connected to the corresponding output of the second decoder and from logic “1”, the first inputs of the sixth and the seventh AND element is connected to the corresponding outputs of the second decoder, and the second inputs, respectively, to the direct and inverse outputs of the memory cell, the information input of which is connected to the output of the second OR element of the last logical nal, and the control input of the controlled memory cell is connected to the output of the fourth element And, the first input of which is connected, together with the first inputs of the second elements AND of all logical channels, to the corresponding output of the first decoder, the second input of the fourth element And, together with the second inputs of the third elements AND of all logical channels connected to a specific output of the synchronization unit, and the third input of the fourth AND element is connected to a specific output of the second decoder, in the multi-channel operation unit, the control input is The element being connected is connected to a specific output of the program unit and to the first input of the fifth OR element, the output of the last is connected to the first input of the ninth AND element, in the switching and computing unit, the first inputs of the third and fourth elements AND of the AND-OR element are respectively connected to the specific outputs of the first decoder and the second inputs are connected respectively with the output of the controlled element and with the inverse output of the second counting trigger of the last logical channel in the multi-channel operation unit, in the moves of the first and second decoders are connected to the command buses of the program unit, the output of the second OR element of the first logical channel is connected to the second input of the second AND element of the second logical channel, the output of the second OR element of the second logical channel is connected to the second input of the second AND element of the third logical channel, etc. d. to the last logical channel, the second input of the second AND element of the first logical channel is connected to the output of the second OR element of the multi-channel operating unit, where the inverse output of the managed memory cell is connected to the corresponding input of the output unit, the second input of the fifth OR element is connected to one of the common buses of the communication system, transmitting the first bit of the code word, the second input of the ninth element AND is connected to the output of the sixth element OR, the inputs of the eighth element AND are connected to the corresponding outputs of the first decoder and synchronization block, and the output is connected to the first input of the fourth OR element, the output of the last is connected to the reset inputs at “0” of the second counting triggers of all logical channels, the inputs of the fifth AND element are connected to certain outputs of the program block and synchronization block, and the output is connected to the second the input of the fourth OR element and with the reset inputs to "0" the first countable triggers of all logical channels, also a communication system that covers the corresponding blocks and contains the first and second electronic keys, common buses, logical ele The signal generating element at its outputs is similar to the signals at the first four outputs of the first decoder of the multichannel operating unit, into which the sixth and seventh OR elements, the NOT element and the electronic switch are inserted, and each logical channel is supplemented by the fourth AND element, the discharge shift module (MCP), and module for the implementation of logical functions (MYFF), module MCP1 introduced in all channels except the first and last, and implements logical functions

and

, where Y'1 and Y'2 are the signals at the outputs of the MCP1 module, the signals b ', b ", s'c'', t ₁ , e ₆ are input to the MCP1 module, with b' and b '' respectively from the outputs of the first countable triggers of this and subsequent logical channels, s and c come from certain outputs of the program unit, t ₁ , e ₆ come respectively from the output of the element NOT and the output of the first decoder of the multi-channel operation unit, and the outputs of module MCP1 are connected to the third and the fourth inputs of the first OR element of this and subsequent logical channels, the MCP2 module in the first ogicheskom channel implements the Boolean functions

and

where the signals U ₁ , U ₂ and U ₃ from the outputs of the MCP2 module are supplied respectively to the third, fourth inputs of the first OR element of the first logical channel and to the fourth input of the first OR element of the second logical channel, signals b ₁ , b ₂ , s', s " , t ₁ , e ₆ go to the inputs of the MCP2 module, respectively, from the outputs of the first counting triggers of the first and second logical channels, from the two outputs of the program block, the output of the element NOT and from the output of the first decoder of the multichannel operational block, the MCP3 module implements a Boolean function

where the signal Y ' ₁ comes from the output of the MCP3 module to the third input of the first OR element of the last logical channel, the signals b _n , c'', t ₁ , e ₆ come to the inputs of the MCP3 module, respectively, from the outputs of the first counting trigger of the last logical channel, from the output a program block, from the output of the element NOT and from the output of the first decoder of the multi-channel operational block, the MRF modules in each logical channel implement a Boolean function

where the signals a ₁ , a ₂ , c ', c''are fed to the inputs of the МРФ modules, respectively, from the outputs of the first and second counting triggers of a given logical channel and from the two outputs of the program unit, and the output signals В _i , of the МРФ modules are received in a multi-channel operating unit to the inputs of the controlled element and the electronic switch, the control input of which is combined with the input of the element NOT and connected to the output of the seventh OR element, two inputs of which and two inputs of the sixth OR element are connected to the corresponding four outputs of the first decoder, you the course of the ninth AND element is connected to the first inputs of the fourth AND elements in each logical channel, the second inputs of the fourth AND elements of each logical channel, together with the information outputs of the electronic switch of the multichannel operational unit, are connected to the common buses of the communication system, and the outputs of the fourth I elements in each logical channel are connected with the first inputs of the elements EXCLUSIVE OR, the common buses are also connected to the outputs of the first and second electronic keys of the communication system and to the multi-bit inputs of the operating unit the main memory and the output block, the inputs of the first and second electronic keys are connected to the multi-bit outputs of the input block and the RAM block, the control inputs of the first and second electronic keys, the RAM block and the output block are connected to the corresponding outputs of the logic element, the three inputs of which are combined with the corresponding three inputs of the first decoder of the multichannel operational unit and with specific outputs of the program unit, an additional two control buses emerging from the program of the second block, a conditional transition block containing the first and second buses, pulse counters, for example one, several rows of memory cells, for example two rows, the corresponding number of electronic keys, for example four, a control module having, for example, nine inputs and eight outputs, and the first buses are connected with the address buses of the program unit, with the installation inputs of the pulse counter, with the inputs of the first and second rows of memory cells, with the inputs of the fourth electronic key and with three inputs of the control module, the second buses in the conditional unit transitions are connected with the corresponding outputs of four electronic keys and with specific inputs that determine the addresses of sources and receivers of information in the input block, RAM block and output block, the fourth and third inputs of the control module are connected to the corresponding command buses of the software block, two more inputs of the control module are connected respectively, with two additional control buses, the eighth and ninth inputs of the control module are connected to the corresponding outputs of the switching and computing block and synchronization block, in the conditional transition block, the outputs of the pulse counter are connected to the inputs of the third electronic key, the outputs of the first and second rows of memory cells are connected to the inputs of the first and second rows of electronic keys, the three outputs of the control module are connected to the inputs for controlling the binary code recording, respectively, of the pulse counter , the first and second rows of memory cells, the fourth, fifth, and sixth outputs of the control module are connected to the inputs of the inclusion of three electronic keys, the seventh output of the control module the conditional transitions are connected to the counting input of the pulse counter of the conditional transition unit, the second and first additional control bus of the program unit are connected to the blocking input of the second decoder of the multichannel operational unit and to the control input of the fourth electronic key in the existing conditional transition unit and the second buses of which are connected to information inputs the electronic key in the counter of the program unit, the control module implements Boolean functions

where a ' ₁ , a ₁ , a ₂ , a ₃ , a ₄ , a ₅ , a ₆ are the input signals supplied to the inputs of the control module, while the signals a' ₁ , a ₁ come from the outputs of the program unit, respectively, according to the first and the second bus entered, signals a ₂ , ₃ , a ₄ , a ₅ , and ₆ are received respectively by two command and three address buses from the outputs of the program unit, signal α is received from the output of the memory cell of the switching and computing unit, signal z is received from the corresponding output of the synchronization unit, Y " ₁ , Y" ₂ , Y " ₃ , Y" ₄ , Y " ₅ , Y" ₆ , Y " ₇ and Y" ₈ are the output signal lams and are formed at the outputs of the control module, while inside the conditional transition block, signals U " ₁ and Y" ₇ are fed to two control inputs of the pulse counter, signals Y " ₂ and Y" ₃ are fed to the control inputs of the first and second rows of memory cells , the signals Y " ₄ , Y" ₅ and Y " ₆ are fed to the input inputs, respectively, of the first, second and third electronic keys, the signal Y" _{8 is} fed, through the elements OR and AND to the input of the electronic key in the pulse counter of the program unit, by the fact that a block of subprograms is introduced into it, containing the first and second electronic keys, a binary pulse counter, the first and second AND elements, a controlled trigger, the third AND element, a memory module, wherein the information inputs of the first electronic key are connected to the corresponding address buses of the program unit, the control input of the first electronic key is connected to the output of the first element And, the inputs of which are connected to the input bus of the program unit and to a specific output of the synchronization unit, the outputs of the first electronic key are connected to the installation inputs of the binary count a pulse sensor, the counting input of which is connected to the output of the second AND element, the inputs of the latter are connected to the output of the synchronization unit and to the direct output of the controlled trigger, the inverse output of the latter is connected to the control input of the electronic key of the program unit and to the first input of the third AND element, the second input of which is connected with the corresponding output of the synchronization block, the output of the third element AND is connected to the counting input of the pulse counter of the software block, the outputs of the binary pulse counter are connected to the inputs of the module memory, the outputs of which are connected respectively with the information inputs of the controlled trigger and the second electronic key, the control input of the latter is connected to the direct output of the controlled trigger, the control input of which is connected with the corresponding output of the synchronization block, the outputs of the second electronic key of the subprogram block are connected to the corresponding command and address buses of the electronic key of the software unit, an AND-NOT element is inserted into the switching and computing unit, and the inputs of the AND-NOT element are connected to the fifth the course of the decoder and with the direct output of the memory cell, and the output of the AND element is NOT connected with the third inputs of the fourth elements AND of all logical channels of the multichannel operational block, with the third input of the first element AND of the RAM block and with the third input of the element AND of the output block, the sixth element AND connected by the inputs to the sixth output of the decoder and the direct output of the memory cell, the second key is entered into the pulse counter of the program unit, the AND and OR elements, and the information inputs of the second key are connected to the system common buses we are connected, and the outputs of the second key are connected to the information inputs of the electronic key in the pulse counter of the program unit, the control input of the second key is connected to the output of the sixth element AND of the switching and computing unit and to the first input of the OR element, the second input of which is connected to a specific output of the control unit conditional transitions, the output of the OR element is connected to the first input of the And element, the second input of which is connected to the output of the synchronization unit, and the output is connected to the input of the electronic key switch pulses of the program block, the controlled element in the multi-channel operational block implements the function OR or EXCLUSIVE OR, depending on the value of the signal at its control input, the interrupt block containing the element NOT, triggers for receiving interrupts, an interrupt sequence selection module that implements Boolean functions

where X'1 ... X ' _n and

are the input and output signals received at the corresponding inputs and outputs of the interrupt sequence selection module, an encoder, read-only memory (ROM), an electronic key, logical elements AND and OR, and the information and control inputs of triggers for receiving interrupt signals respectively receive request signals for interruption of certain sensors and the signal output from the corresponding sync block, and outputs of said flip-flops are connected to the X'1 ... X _'n input sequence selection module interrupts in which moves

connected to the inputs of the encoder, the outputs of the latter are connected to the inputs of the OR element and to the inputs of the ROM, the outputs of which are connected to the information inputs of the electronic key, the control input of the latter is connected to the output of the AND element, the first and second inputs of which are connected to the output of the OR element and to the corresponding output of the block synchronization, the third and fourth inputs of the AND element are connected respectively with the inverse output of the controlled trigger of the block of subprograms and with the output of the element NOT, the input of which is connected to the entered bus, multi-bit cell and the memory and multi-bit electronic key, and two more control buses are introduced into the program unit, while the information and control inputs of the multi-bit memory cell are connected respectively to common buses and to the first of the two entered control buses, and the outputs of the multi-bit memory cell are connected to the multi-bit information inputs an electronic key, the control input of which is connected via a second input bus with a specific output of the program unit and with the second input of the electronic key control of the program unit, the outputs of the multi-bit electronic key are connected to the address buses at the output of the program unit, the outputs of the electronic key of the interrupt unit are connected to the installation inputs of the pulse counter of the program unit, the third input of the first element AND of the subprogram unit is connected to the inverse output of the controlled trigger of the subprogram unit.

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