SU1019455A1 - Device for table implementation of polyadic logic functions - Google Patents

Description

the input of which is connected to the input of the unit, and the output - with the address input of the microprogram memory unit, the control input of which is connected to the first output of the clock generator, the second output of which is connected to the control input of the microinstructions register, the information input of which is connected to the output of the microprogram memory block , the second group of outputs of the register of micro-commands is connected to the second output of the block, the third output of the clock generator is connected to the first inputs of the first, second, third, fourth and fifth elements And, th Werth output clock generator is connected to a first input of a sixth AND gate, whose output is connected to the fourth output block, a third group of microinstructions register outputs connected to second inputs of the first, second, third, fourth, fifth and

of the sixth elements And, the outputs of the third fourth and fifth elements And

connected to the first, third and fifth outputs of the unit respectively.

The invention relates to computing and control technology. Mini and micro computers are widely used in process control systems and industrial installations. In this case, the main converters are executed in an arithmetic logic unit adapted to perform double arithmetic operations. multi-variable variables, as well as two-place bitwise logical operations. However, the implementation of control algorithms often involves the task of performing multi-place logical functions and systems of functions of several binary variables, packed in one word and forming a vector of binary variables. These functions can be very diverse and vary both in appearance and in the number of arguments from task to task. Therefore, the use of combinational circuits with rigid structured programmable logic arrays or functional based transducers. ROM is ineffective. A data processor is known that contains a processing ROM and a stack for storing intermediate results, which contains a ROM for logic processing 1. Its disadvantage is the need to use a relatively expensive additional block of ROM with a frame, which reduces the cost-effectiveness of the device. In addition, programming a ROM for setting it up for solving various tasks is a more laborious operation than programming a RAM. A device for storing and transforming information is known, which provides a table implementation of binary double logic functions in RAM 2 memory. However, to implement multi-seat logical functions from a vector of binary variables using this device, a program method based on conditional jump commands is also required, the lack of which is complexity programming, a large amount of programs and constants necessary for extracting variables and calculating logical functions and low n performance In order to eliminate these drawbacks, it is proposed: to use a device that provides implementation of multi-place logical functions from a vector of binary variables based on tables stored in a memory storage unit. This contributes to economic efficiency, since the basis is made up of the cheapest, most reliable and technologically advanced elements - the storage elements of a single memory block used for other purposes (storing programs, data constants). In addition, storing tables in a storage unit makes them easy to manage. Changing tables is less time consuming than changing programs with software implementation of logical functions. The proposed device provides the implementation of functions with the help of a single command, which is performed in two accesses to the memory unit, which significantly improves performance compared to software. The purpose of the invention is to improve the performance of the device. The goal is achieved by the fact that the device for a tabular implementation of multi-seat logical functions, containing a memory block whose output is connected to the information inputs of the operand register and command register, I1 is connected to the first input of the device, and the address input to the output switch of the address switch, The first information input of which is connected to the second input of the device, the second info input input - to the output address of the first operand of the command register, the third and fourth information inputs of the address switch connected to the output of the address of the second operand of the command register and the third input of the device, respectively, the outputs of the digital bits of the register of the operand are connected to the fifth information input of the address switch, the sixth information input of which is connected to the output of the segment number of the command register, additionally contains a firmware control block, the OR elements, the switch of the data bits and the result trigger, the output of the Kofia command register operations connected to the input of the microprogram block of the multi-station: first, Vr11 “ti Ti, the fourth and fifth outputs of which are connected respectively to the control inputs of the command register, the address switch, the register operand of the memory block and the result trigger, the output of which is connected to the output / device, and the setup input to the output switch of the data bits whose information input with the output of the memory block, the output of the higher bits of the register of the operand is connected to the first inputs of the elements of the OR group, the second inputs of which are connected to the output of the address of the table in the segment, the outputs of the elements of the OR group are connected to the information onnomu input switch addresses, discharge instruction register output connected to a control input of the switch data bit rows. The microprogram control block contains the microprogram memory block, the MICROCOM5G.ND register, the microinstructor address register, the clock pulse generator and six AND elements, the outputs of the first and second AND elements are connected to the first and second microcontrol addresses register, the first group of register outputs microinstructions connected to the first information input of the register of the microinstructions address, the second information input of which is connected to the input of the block, and the output to the address input of the microprogram memory unit that controls the input of which is connected to the first output of the clock pulse generator, the second output of which is connected to the control input of the micro-register register, whose information input is connected to the output of the microprogram memory unit, the second group of outputs of the micro-register register is connected to the second output of the block, the third output of the clock generator is connected to the first inputs of the first, second, third, fourth and fifth elements And, the fourth output of the generator of clock pulses connected to the first input of the sixth element And, the output of which connected to the fourth output b of the current, the third group of outputs of the register of microcommands is connected to the second inputs of the first, second, third, fourth, fifth and sixth elements AND the outputs of the third, fourth and fifth elements AND are connected respectively to the first, third and fifth block outputs. Figure 1 shows the functional diagram of the proposed device; FIG. 12 shows an example of the implementation of an aUE) RES switch; 3 shows an example implementation of a data bits switch; in fig. - .functional circuit of the clock pulse generator; figure 5 is a temporary diagram of the operation of the device; 6, transformations associated with Address Formation. The device contains a memory J with output 2, address input 3, control input 4 and information input 5t register 6 operand output 7 lower bits, output 8 high bits, information input 9 and control input 10, register 11 commands with output 12 of the operation code, output 13 of the address of the first operand, output 1k of the bit number, output 15 of the segment number, output 16 of the address of the table in the segment, information input 17 of the control input 18 and output 19 of the address of the second operand, including the outputs Y 16, the switch 20 addresses with information and inputs 21-23 and input 2k, including information inputs 25-28, control input 29 and output 30, a group of elements OR 31 with outputs 32, an output 33 of the device, a switch 3 of the bit data with information input 33, a control input ST and information output 37- Result trigger 38 with control input 39, microprogram control block kQ, containing the microinstructor address register C with information inputs k2 and 43, control input kk, microprogram memory block with address input control input 47 , register of 48 microinstructions with information input 9, control input 50, first group of outputs 51, second and third groups of outputs 52 and 53, first, second, third, fourth, fifth and sixth elements And 54-59. 60 clock pulse generator with 61-b outputs. The switch 20 (FIG. 2) contains: a group of Multiplexers B5, a switch 3 (FIG. 3) multiplexers 66-68, a generator 60 (FIG.) Contains a generator B9 of pulses, a delay element 70 with an input 71 and outputs 72-7, and elements AND 75 and 7b. The operation of the device is synchronized with pulse signals at the outputs 616 of the generator 60 clock pulses. The timing diagram of the cycle T of the device operation (Fig. 5) depends on the features of memory block 1, kS memory of firmware, and delays used. zyuyh elements. The work cycle can be divided, for example, into 4 clock cycles (1, t, f, T): 1 clock cycle — reading the microcommand from block 5 of the microprogram memory; T clock - writing the micro-command code to the micro-command register, generating the address code at the input 3 of the 1 memory block; llj tact — reading from memory block 1; 1U clock - recording of the code 55, read from memory block 1 ;, into one of the registers. Accordingly, the signal at output 61 corresponds to the T-th and I-th cycles, at output 62 - 1 to the U-th cycle, at the output 63-W-th and 1-th clock, output 6 - | U th cycle. Output 61 of the generator 60 clock pulses are connected to control input 7 of the kS memory of the firmware, output 62 to control input 50 of the re-. gistra t8 microinstructions, output 63 - to the second input of the element And 59, output b - to the second inputs of the elements and. The device works as follows. From the command counter (not shown, input 21 receives the code of the command address for implementing the function f (x, X2, x). The command is read from memory block 1 at the address supplied to input 3 through switch 20 from input 21, "is written to register 11 commands. The address code of the 1st firmware implementation of multi-seat logic functions is written to the register at input k2. An address (vector .1) is read from the address coming from the output 3 of the register 11 commands 11, and stored in memory 6 of the operand. the microinstructor address register at input k3 is written to the address of the nth micro Commands. In accordance with the connections given in FIG. 1, the code at input 2 of the Switch 20 address consists of kx parts: X, & H C2gCvHig: f3oXi, i: w2. OX2 i: Vyii6-.43o) where C gt ze- F ROW code supplied to. INPUT 28; Xj. ,, i., HD g V jgCHii -.ll, (t. Bb t 63-Y, fetMi 6-43,8 CvMeM, (# 4 101 g); i3-Yiitim- ,: 13, SkitI1.) , de - code on the i-th input; V: - code J, 1f - position numbers e fig1; o is the sign of concatenation. The numbers of bits for the selected groups of variables must be chosen from the following conditions: Oeog, NC} D - ° ea s -. e l TMOKc, 1- “a5 i- ,, where Ы, n is the number of meek and the number of bits in memory block 1; af is an integer satisfying the as3att Q4 i tmax mmi inequalities of the maximum and minimum number of bits in the binary variable vector for which the logic function can be calculated in tabular fashion. Consider an example of choosing numbers of bits. Let N 2 ijK cells, m 3, n; 32. Then we get: m 3eog-Nt-n KU) r5 1 L Wg-5 h. The need to calculate different “multiplace logical functions from more than 8 variables in control tasks arises relatively rarely. The tables at 8 become cumbersome and allocating RAM segments for their storage is economically unjustified. If necessary, in those cases when the number of arguments is 40 8, logic functions can be implemented using a program-tabular method. Using the selection of variables and conditional jump instructions by their values, the task can be reduced to calculating several eight-place functions. Double functions can be implemented programmatically or use a redundant representation in the form: U ,, xi) (x - ,, Xa (records of tables of implemented functions use one or more segments of the memory block 1 memory containing N 2-Gmok cells). ., 8, N, 256, the table of the eight-place function is thrown in memory elements belonging to one bit of a Segmot of 256 cells. The address of a cell in one 1 8 cops corresponds to the set of binary variables on which the function is defined, In one bit of the same segments can be placed 2 tons seven-place tables, k-tables are six-seat, 8.-p tables, 1b quadruple tables, and 32 tables of triple functions. In total, the following number of tables can be written: KgisG + k ne k К К. ,,, where Kc - the number of tables — local functions, f 3-8; The maximum number of segments of the storage unit of memory 1, which can be used to record the tables of implemented functions, is determined odomis, and 2, In the considered example, the DEVICE can execute the command to implement a multi-seat logical function from the binary variable vector . In this case, the following farmat command is used, having 5 fields according to the number of outputs in the register of 11 commands. The exit field 12 indicates the opcode; in output field 13 - the address of the operand; in output field 1, the number of the bit number in which the table of the implemented function is written; in exit field 15, the number of the required segment of the accumulator: 1 out of the tables allocated for storage; in the output field 1b, the address of the table within the segment with the number of arguments about T coin Code: 1 1 At BS5: The HS of the address of the table within the segment specified in the command format is defined as follows. With the number of arguments t., 8: Y-16 5-H QOO QPri Pd 7: Y eL5: lD, about 256 (0.1. In one bit of the RAM segment of 256 cells, two tables of seven-seater functions can be written. Senior bit The 2-Y code determines the position of the required ablitz in the selected 9th segment. The segment is knocked out by the code ° 27 3. pry1% .43-2524000, Wa l5Z425 (OA-f a5: fl6t5H3-j with WvQ-i-4ibt5: 43-25Z4Z Z , 3, Z, Z5i4 aZiGM8, the latter case, the Y | code can indicate the position of one of the 32 tables of a triple logic function. Thus, the code in the command format and a group of 31 elements OR provide for the addressing of the function tables from different variables when packing these tables in a segment of 256 cells. It should be noted that if over 8 - m bits in the register 6 of the operand contains zeros. And in the code Y. (5: t) only those bits can be different from zero, which correspond to the binary high-order binary variables absent in register B. The operation of the device when executing the command to implement a multi-place logical function is considered using the illustration of transformations associated with the formation of an address and dividing the bit of a read word from a table segment, represented by an example shown in FIG. Let it be required to implement a triple function: 1 XiCBV-i Let the vector code x., X,) store, with the cell with the address A1. Assume that memory block .. 1 has a capacity of N. K and for storing the tables of the functions implemented, the last segment containing 256 cells with binary addresses is used: (111.100.000.000 .. (ri1.111.111.111). The table of the implemented function takes 8 cells. Assume that the 17th bit of the selected segment is used to store it.This bit is 256 bits and other tables can be placed. Let 8 cells with the following table be allocated to the table of the function to be implemented: (11. 000), ... (11 .111). .6 diagram 55 is a diagram of the position of the table in the memory of memory block 1. In the field g of the command, the address code of the table of the realized function f in the selected segment of 256 cells must be specified. The code for the segment number of 256 cells, which is used to store tables, can be specified in the field of the command doc.Please specify different segments for the number of digits of this field. Since the last segment with the number 11 is used to write the table of the function f, then Y (2: 1) 11. The command field indicates the code of the position number in which the table is recorded. In our example, this is the 17th bit code: 10001. Since it was assumed that the end of the accumulated body was set aside for storing the tables, then the fixed code at input 28: C2.g2: 1 P. This code defines the memory area in an example with a capacity tK, in which segments of 256 cells can be allocated for storing tables. Consider the effect of increasing productivity. In the program (in the first method of implementation, the calculation of the function of 6 arguments will require at least 6 instructions to unpack the arguments, each of which will require at least 3 RAM calls, and at least 6 conditional branch instructions will be required when calculating the FUN.KTsI each of which requires at least 2 calls to the RAM. Thus, the calculation time of the six-place function can be represented as follows: (U – Oro, where Td is the cycle time for accessing the RAM. In the proposed device, the command to implement the six-place logical function, Key selection commands require.

The average time T to perform an operation in a known device;

T Pit- c - U-POt

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where R. is the probability of the appearance in programs of the task of calculating multiplace logical functions;

t is the average execution time

P single operation. Take t (-p, R, 0.01. We get T 0.01-30 h- (1-0.01) c TO it, 26 V

Similarly, in the proposed device

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Claims (2)

1. DEVICE FOR TABLE IMPLEMENTATION OF LOCAL LOGIC FUNCTIONS, containing a memory block, the output of which is connected to the information inputs of the operand register and the command register, the information input is connected to the first input of the device, and the address input is to the output of the address switch, the first information input of which is connected to the second the input of the device, the second information input - to the output address of the first operand of the command register, the third and fourth information inputs of the address switch are connected to the output address of the second operand and the instruction register · and the third input of the device, respectively, the outputs of the least significant bits of the operand register are connected to the fifth information input of the address switch, the sixth information input of which is connected to the output of the register segment number, which means that, in order to increase the productivity of the device, it additionally contains a microprogram control unit, a group of OR elements, a switch for data bits and a result trigger, and the output of the operation register of the instruction register is connected to the input of the microprogram unit rammnogo control, first, second, third, fourth, fifth th outputs of which are connected respectively to the control inputs of the instruction register, the switch address, an operand register of the storage unit and the trigger result, the output of which is connected to the output device, and installation c input - to the output of the switch of bits of data, the information input of which is connected to the output of the memory block, the outputs of the upper bits of the one ® rand register are connected to the first inputs of the elements OR groups, the second inputs of which are connected to the output of the table address in the segment, the outputs of the elements OR groups are connected to the seventh information input of the address switch, the output of the discharge number of the instruction register is connected to the control input of the data discharge switch. 2. Device No. 1, wherein the microprogram control unit comprises a microprogram memory block, a micro-command register, a micro-command address register, a clock pulse generator and six AND elements, the outputs of the first and second AND elements being connected to the first and to the second control inputs of the micro-command address register, the first group of micro-command register outputs is connected to the first information input of the micro-command address register, the second information input of which is connected to the unit input, and the output to the address input b the microprogram memory eye, the control input of which is connected to the first output of the clock generator, the second output of which is connected to the control input of the micro-command register, the information input of which is connected to the output of the micro-program memory block, the second group of micro-register register outputs is connected to the second output of the block, and the third output of the clock generator pulses connected to the first inputs of the first, second, third, fourth and fifth elements And, the fourth output of the clock generator is connected to the first input at the sixth element And, the output of which is connected to the fourth output of the block, the third group of outputs of the microcommand register is connected to the second inputs of the first, second, third, fourth, fifth and sixth elements And the outputs of the third, fourth and fifth elements And are connected respectively to the first, third and the fifth outputs of the block.