SU1120340A1 - Control vector computer system - Google Patents

Abstract

1. CONTROL VECTOR COMPUTING SYSTEM containing a vector arithmetic logic unit, three blocks of buffer registers, a block of decoders, two blocks of microprogram memory, a block of system registers, a block of priority interrupts, a block of transceivers, random access memory, and a microprogram control device, with the input and the output of the decoder unit are connected respectively to the first output of the first microprogram memory unit and the input of the operation code of the vector arithmetic logic unit va, input data and output data which are respectively connected to the exit and entry per-. the first block of buffer registers, the data input of the random access memory is connected to the inputs of the first, second and third blocks of the buffer registers and the input of the transceiver unit, the output of which is connected to the address inputs of the system registers and random memory blocks, the outputs of the first, second and third blocks of buffer registers and the external interrupt input of the priority interrupt block, the external interrupt output and the current interrupt block input of the priority interrupt are connected respectively with the input of the transceiver unit and the interrupt output of the microprogram control device, | address output, control output (About writing to registers, command writing control output, command input and operation code input of which are connected respectively to the address input of the second microprogram memory block, the data input of the system register block, the input of the second block of buffer registers, the first data output of iloc the system registers and the first output of the second firmware memory block, and the second data output of the system register block is connected to the input of the second buffer register block, characterized in that, in order to increase performance, it contains a block of accelerated interrupt processing, a scalar arithmetic logic unit and a vector command generation unit, including a register of request attributes, four micro-operations decoder, a vector length counter, a priority encoder, a group of AND elements, a register of signs of an operation, a group of triggers

Description

availability, multiplexer, cycle counter group of delay elements command register and firmware control node, read enable input, address input, command input, sign input, interrupt output, address output and sign output of which are connected respectively to the group delay elements moves, The output of the first microprogram memory block, the output of the command register, the multiplexer output, the first input of the priority encoder, the address input of the first microprogram memory block, and the syntax of the feature register The operations, data input, synchronous input and output of the request attribute register are connected respectively to the output of the request signs of the firmware control device, the output of the first micro-operation decoder and the first inputs of the AND group elements, the second inputs and outputs of which are connected respectively to the output of the first micro-operation decoder and inputs of the group readiness trigger, the outputs of which are connected to the inputs of the group delay elements, the input of the command register is connected to the output of the second block of buffer registers, the inputs of the first, The third, third, and fourth decoders of micro-operations are connected to the second output of the first microprogram memory block, the input and output of the vector length counter are connected respectively to the output of the first block of the buffer registers and the first input of the register of features of the operation, the second input of the permission and the output which are connected, respectively, with the output of the signs of the operation of the vector arithmetic logic unit, the output of the first decoder of the micro-operations torus and the input of the first block of buffer registers, the output of the second the micro-operation decoder is connected to the loop counter input, the second and third inputs and the priority encoder output are connected respectively to the output of the vector length counter, the third micro-operations decoder output and the microprogram control device data request input, and the control input, the first, second and third multiplexer data inputs connected, respectively, to the output of the fourth decoder of microoperations, the output is sign 40 of the vector arithmetic-ddgy device, the output of the register of signs of the operation and in The output of the loop counter, micro-op input, data input and scalar arithmetic logic unit are connected respectively with the second output of the second microprogram memory unit, the output and the input of the second block of buffer registers, and the accelerated interrupt processing unit includes a switch, a micro-decoder, a register features, a group of system registers, a multiplexer, a super-fast memory node, a firmware control node, an adder and a fixed memory node, an address input, the first and second outputs of which They are connected respectively to the address output and the address input of the microprocess control node and the micro-operation decoder input, the first, second, third and fourth outputs of which are connected respectively to the synchronous input of the register of attributes, the input of the adder operation code, the controlling input of the superfast memory node and the synchronous input of the system registers of the group data inputs, the first and second outputs of which are connected respectively to the output of the third block of buffer registers, the first input of the multiplexer and the input of the third b the buffer register locations, the control input, the first and second data inputs and the switch output are connected respectively to the first output of the micro-operation decoder, the output of the state of the microprogram control device, the output of the sludge memory node and the input of the data of the register of attributes, the output of which is connected to the second input of the multiplexer, the data input and the output of the adder are connected respectively to the output of the super-operative memory node and the input of the attributes of the microprogram control node, and the enable input to find out, in commands input characteristics, yield and yield interrupt microprogram control node attributes are respectively connected to the output of the current interrupting unit priority interrupt, the output of the multiplexer, the outputs of the second group of system registers, entry poll interrupt priority interrupt and block entry a switching control device firmware tasks.

2. Pop. 1 system, characterized in that the firmware control node contains a trigger, command register, trigger group, address multiplexer, microcommand address register, feature register and output address register, data input, sync input and output of which are connected respectively to the output the microcommand address register, the node enable input input and the node output address, the first, second, third, fourth, and fifth data inputs, the control input first.

and the second outputs of the address multiplexer are connected respectively to the address input of the node, the output of the command register, the input of the node commands, the trigger output, the output of group triggers, the output and input of the microcommand address register and the output of the node interrupt, the input of the command register is connected to the input of the node commands, input and output the trigger is connected respectively to the input of the node attributes and the data inputs of the trigger group, the synchronous inputs of which are connected to the input of the characteristics of the node, and the data input, the synchronous input and the output of the register of attributes are connected respectively to odes triggers group entry node attributes and output node attribute.

3. The system according to claim 1, characterized in that the itoKponporpaMMHoro control device contains four micro-operations decoder, two sets of triggers,

Three multiplexers, an output decryptor, a microprogram control node and a switch, the data input and the first output of which are connected respectively to the sign output of the microprogram control and the device status output, the data input and the sync input of the first trigger block are connected respectively to the device data request input and the first output of the first micro-operation decoder, the input and the second output of which are connected respectively to the input of the operation code of the device and the synchronous input of the second trigger block, the input is given which are connected to the second output of the switch, the inputs of the second and third micro-operations decoders are connected to the input of the operation code of the device, the first, second and third data inputs, the control input and output of the first multiplexer are connected respectively to the switching input of the device tasks, the output of the first trigger block, the output of the second block of triggers, the first output of the fourth micro-operation decoder, and the input of features of the firmware control node, the read enable input and the address input of which are connected to The device operation code input, command input, interrupt output and address output of the firmware control node are connected respectively to the command input, interrupt output and device address output, the input and the second output of the fourth micro-operation decoder are connected respectively to the input of the operation code of the device and the control input of the switch, the inputs the data of the second and third multiplexers are connected to the input of the device commands, and the control inputs of the second and third multiplexers are connected to the outputs, respectively the first and second inputs, the first and second outputs of the decoder are connected respectively to the outputs of the second and third multiplexers, the write control code to the registers and the control code to record the device commands, and the output of the second trigger unit is connected to the output of device request attributes.

one

 The invention relates to computing and relates to the architecture of computing systems designed to solve real-time control tasks and various kinds of computing tasks.  Computer systems are known that contain vector processors and use the conveyor principle of data processing and C2}.  One of the drawbacks of Cl is the large amount of response time to interrupt with respect to command execution time. When the second C21 system is running, there is also a decrease in speed due to the fact that it is not possible to combine the processes of retrieving information from the memory and processing it.  Closest to the proposed system is a small controlling computing system containing a vector arithmetic logic unit, three blocks of buffer registers, a block of decoders, two microprogram memory blocks, a system register block, a priority interrupt block, a transceiver block, a random access memory and a microprogram unit. control, while the input and output of the decoder unit are connected, respectively, with the first output of the first memory block of the firmware. - and the input of the operation code of the vector arithmetic unit, the data input and data output of which are connected respectively to the output and input of the first block of buffer registers, the data output of the random access memory is connected to the inputs of the first, second and third blocks of the buffer registers and the input of the transceiver unit whose output connected to the address inputs of the system register block and the random access memory, the output of the first, second and third blocks of the buffer registers and the input of the external interrupt REPRESENTATIONS block priority interrupts, output interrupts and external interrupts the current input block priority interrupt s respectively connected to the input reception unit and output transmitters interrupt microprogram control unit, an address output, audio output control record in the registers vkod councils lazy write command input. commands and input of the operation code of which are connected respectively to the address input of the second microprogram memory unit, the data input of the system registers block, the input of the second block of buffer registers, the first data output of the system registers block and the first output of the second microprogram memory block, and the second data output block of system registers connected to the input of the second block of buffer registers 3J.  The disadvantages of the known system are the large amount of response time to interrupt and low speed in the processing of scalar values, low utilization of equipment.  The purpose of the invention is to improve the performance of the vector computing system filler.  This goal is achieved by the fact that the control vector computing system contains a vector arithmetic logic unit, three blocks of buffer registers, a block of decoders, two blocks of memory of microprograms, a block of system regs. the gistrov, the priority interrupt block, the transceiver block, the random access memory and the firmware control device, the input and output of the decoder block respectively connected with the first output of the first firmware memory block and the operation code input of the vector arithmetic unit, the data input and data output of which are connected respectively to the output and input of the first block of buffer registers, the data input of the random access memory is connected to the inputs of the first, second and three of the buffer register blocks and the input of the transceiver unit, the output of which is connected to the system block and random access memory block inputs, the output of the first, second and third buffer register blocks and the external interrupt input of the priority interrupt block, the external interrupt output and the current interrupt block input connected respectively to the input of the transceiver unit and the interrupt output of the firmware control device, the address output, the control output A register entry, a command record control output, a command input and an operation code input of which are connected respectively to the address input of the second microprogram memory block, the data input of the system register block, the second block of the buffer register registers, the first code of the system register data and the first code of the second register of the firmware memory block, and the second output of the data of the system register block is connected to the input of the second block bu. Fir registers, additionally contains a block of accelerated interrupt processing, a scalar arithmetic unit and a vector command generation unit, including a register of request attributes, four micro-operations decoder, a vector length counter, a priority encoder, a group of AND elements, a register of operation signs, a ready trajectory group, a multiplexer , cycle counter, group of elements of the delay, command register and micro program control node, read permission input, address input, command input, feature input , the output of the alarm, the address output and the sign code of which are connected respectively to the outputs of the delay elements of the group, the second output of the first microprogram memory unit, the output of the command register, the output. the multiplexer, the first input of the priority encoder, the address input of the first microprogram memory block, and the synchro-input of the feature register; the input, the sync input and the output of the request feature register are connected respectively to the output of the request attributes of the microprogram control device, the output of the first decoder of the micro-operations and the first inputs of the AND group, the second inputs and outputs of which are connected respectively to the output of the first decoder of micro-operations and the inputs of the group readiness triggers, the outputs of which They are connected to the inputs of the group delay elements, the coma register input is connected to the output of the second block of the buffer registers, the inputs of the first, second, third and fourth decoders of microoperations are connected to the second output of the first microprogram memory block, the input and output of the vector length counter are connected respectively to output of the first block of buffer registers and the first resolution enable input of the operation feature register, the data input, the second permission input and the output of which are connected respectively to the output of the operation attributes the arithmetic logic unit, the output of the first micro-operation decoder and the input of the first block of buffer registers; the output of the second micro-operation decoder is connected to the input of the cycle counter, the second and third inputs and the output of the priority encoder are respectively connected to the output of the vector length counter, the output of the third micro-operation decoder and the data request input MicroparaNfMHoro control devices, and the control input, the first, second, and third multiplexer data inputs, respectively, are connected to the fourth output micro-operation decoder, feature output vector arithmetic logic unit, operation feature register output and cycle counter output, micro-operation input, data input and scalar arithmetic logic unit output are connected to the second output of the second microprogram memory memory, output and input of the second buffer block, respectively registers, the accelerated interrupt handling unit includes a switch, a micro-operation decoder, a register of features, a group of system registers, a multiplexer, a node of super-op ram memory, microprogram control node, adder and permanent memory node, address input, the first and second outputs of which are connected respectively to the address output and the address input of the microprogram control node and the micro-operations decoder input, the first, second, third and fourth outputs of which are connected respectively, with the synchro-input of the register of features, the input of the operation code of the adder, the control input of the super-operative memory node and the synchronous input of the system registers of the group, the data inputs, the first and second outputs Which are connected respectively to the output of the third block of buffer registers, the first input of the multiplexer and the input of the third block. The buffer registers, the control input, the first and second data inputs, and the switch output are connected respectively to the first output of the micro-operation decoder, the output of the state of the microprogram control device, the output of the super-memory memory node, and the input of the data of the register of attributes, the output of which is connected to the second the multiplexer input, the data input and the output of the adder are connected respectively to the output of the super-fast memory node and the input of the microprogram control node features, and the read enable input NIN, input A team, input characteristics, yield and yield interrupt microprogram control unit connected respectively to the signs of the current interrupting unit vkodu priority interrupt, the output of the multiplexer, the outputs of the second group of system registers, entry poll interrupt priority interrupt and block entry a switching control device firmware tasks.  At that, the firmware control node contains a trigger, a command register, a trigger group, an address multiplex, a microcommand address register, a feature register and an output address register, a data input, a synchronous input and an output of which are connected to the microcommand address register output, the node read register input and the address output the node, the first, second, third, fourth and fifth data inputs, control inputs, the first and second outputs of the address multiplexer are connected to the address input of the node, output register command commands, node command input, trigger output, group trigger outputs, output and microinstruction address register input and node pending output, command register input is connected to the node command input, trigger input and output are connected to the node trigger input and data inputs of group triggers The sync inputs and outputs of the register of attributes are connected respectively to the outputs of the group triggers, the input of the characteristics of the node and the output of the characteristic of the node.  Moreover, the firmware control device contains four micro-operations decoder, two trigger blocks, three multiplexers, an output decoder, a microprogram control node and a switch, data input and the first output of which are connected respectively to the output of the microprogram control node sign and the output of the device state. , the data input and the synchronous input of the first block of triggers are connected respectively to the input of the device data request and the first output of the first micro-operation decoder, the input and the second output of which It is connected respectively to the input of the operation code of the device and the synchronous input of the second trigger unit, the data input of which is connected to the second output of the switch. , the inputs of the second and third micro-operations decoders are connected to the input of the operation code of the device, the first, second and third data inputs controlling the input and output of the first multiplexer are connected respectively to the input switching device tasks, the output of the first trigger block, the output of the second trigger block, the first the output of the fourth micro-operation decoder and the input of the signs of the firmware control node, the read enable input and the address input of which are connected to the input of the operation code of the device, the input of commands, output The interrupt and address output of the firmware control node are connected respectively to the command input, the interrupt output and the device's address output, the input and the second output of the fourth micro-operation decoder are connected respectively to the input of the operation code of the device and the control input of the switch, the data inputs of the second and third multiplexers are connected to the input the device commands, and the control inputs of the second and third multiplexers are connected to the outputs of the second and third microoperations, respectively, and The first and second inputs, the first and second outputs of the decoder are connected respectively to the outputs of the second and third multiplexers, the write control output to the registers and the device control write output, and the output of the second trigger unit is connected to the output feature of the device requests.  FIG. 1 shows the flowchart of the control vector computing system; Fig. 2 is a block diagram of the formation of vector commands; in fig. H - diagram of the firmware control unit; in fig. 4 - diagram of the device firmware control. neHHHj in FIG. 5 is a block diagram of the accelerated interrupt handling unit; in FIG. 6 - command formats; Fig. 7 is a timing diagram of the service of requests. The vector control computer per system (Fig. 1) contains a vector arithmetic logic unit (RABE) 1, the first block 2 of the buffer registers, the block 3 forming vector commands, the block 4 decoders, the first block 5 of the firmware memory, the device 6 of the microprogram control, the block 7 of the system register the second block 8 of the memory These microprograms, scalar arithmetic logic unit (SALU) 9, second block 10 buffer registers, accelerated processing of interruptions, third block 12 buffer registers, block 13 priority interrupt, block 14 transceivers, random access memory (RAM) 15.  Blocks 1-5 form a vector processor (VP), blocks 6-10 are a scalar processor (SP).  The VP and the SP taken together constitute the central processing unit (CPU), blocks 11–13 form the control processor (UE).  The vector command generation unit 3 (FIG. 2) contains the register 16 of request attributes, the first decoder 17 microoperations, the counter 18 vector length, the priority encoder 19, the group 20 of elements AND, the register 21 signs of operations, the second decoder 22 microoperations, the third decoder 23 micro-operations, a group of 24 readiness triggers, a mule type 25, a counter of 26 cycles, a group of 27 delay elements, a register of 28 commands, a fourth decoder of 29 micro-operations, detected: the microprogram has many controls, the inputs of block 3 are marked 31-35, and its outputs are .  36-38, Microprogram control unit 30 (FIG. 3) contains a trigger 39, a command register 40, a group 41 of the address multiplexer 42, a micro-command address register 43 ,. register 44 with nakov, output register 45 addresses.  The inputs of block 30 are labeled 46-49, and its outputs are 50-52.  The microprogram control device 6 (FIG. 4) contains the first micro-operation decoder 53, the first trigger unit 54, the second trigger unit 55, the second (micro-operation decoder 56, the third micro-operation decoder 57, the first multiplexer 58, the fourth micro-operation decoder 59, the second multiplexer 60, the third multiplexer 61, microprogram control unit 62, output decoder 63, switch 64, Control device inputs 6 are labeled 65-68, and its outputs are 69-74, Interrupt processing unit 11 (FIG. 5) contains a switch 75, a decoder 76 micro-operations, register 77 of signs, group 78 of system registers, multiplexer 79, super-operative memory node 80, microprogram control node 81, adder 82, permanent memory node 83.  The inputs of block 11 are designated 84-86, and its outputs are 87-89. The vector command generation unit 3 (FIG. 2) is designed to control the shaft of 1 using the microprograms stored in the first microprogram memory unit 5.  The input 31 receives the parameters of the vector command, which is entered into the register of 28 commands.  Microcommands from the first block 5 of the microprogram memory arrive at input 32 and then to the decoders 17,22,23 and 29 microoperations.  At the input 33, signs of the execution of requests are supplied, and at the entrance 34 - signs from the BA. PU 1, the latter being entered into the register of 21 signs of operations and through the multiplexer 25 arrive at the node 30 of the firmware control.  Data from the first block 2 buffer re-.  through the input 35 of the vector command generation unit 3, the vector length counter 18 is received. From the microprogram control unit 30, through the address output 36, the first microprogram memory unit 5 is received.  From the output 37 of the vector command generation unit 3, information is fed to the first block 2 of the buffer registers, and from output 38, data requests are transmitted to the microprogram control device 6.  The firmware control node 30 (62) (FIG. 3) determines the sequence of control signals (micro-commands) and is intended to perform two functions: determining the address of the next micro-command under the control of the micro-operation code and receiving, storing and transmitting information defining some external conditions.  Typically, such ambient conditions are carry signals.  The memory cell in which the information about the feature is placed is also determined in accordance with the code of the corresponding micro-operation received from the first block 5 of the memory of the micro commands.  A feature of the firmware control unit 30 is the presence of two micro-operation systems, the codes of which are received via two spatially separated main lines.  A set of micro-operations consists of two systems: a system of micro-operations for determining the next address of a micro-command and a system of micro-operations, which receive, store and issue information about the signs.  The content of the first micro-operation system is determined by the address input 47, the second - by the state of the input 49 characters.  Firmware control unit 30 (FIG. H) works as follows.  Some time after the arrival of the synchronization pulse, at the address input 47 a micro-operable transition code is received, which comes from the first block 5 of the microprogram memory.  Further, in the multiplexer 42 of the microinstruction addresses, the code of the required address is sampled.  The specified code is loaded into the micro-instruction address register 43.  If as a result of the multiplexer operation 42 a.  Resa microinstructions set address.  element of the matrix of the first microprogram memory block 5, located at the intersection of the zero row and the 15th column, then a strobe enable pulse is output to the interrupt output 50.  Similarly, micro-operations are performed by recording information about signs in trigger 39 and a group of 41 triggers.  The information is recorded in the trigger 39, then, in accordance with the micro-operations code, the contents of the trigger 39 are loaded into the group 41 triggers at the input of the group of 41 triggers.  The increment of the contents of the group 41 of triggers is determined by the operation code set at the input of the register of 44 indications.  Microprogram control device 6 (FIG. 4) designed to control the SALA 9 when executing scalar commands, as well as when working with descriptors when executing vector commands to generate instructions for RABU 1 for accelerated processing of preggs.  Information from the accelerated interrupt processing unit 11 is input to the switch 65 of the tasks of the device b of the bc-gpro-program control, from the system registers block 7 to the 66 command input, from the second microprogram memory block 8 to the input 68 of the operation command code.  The data request from the vector command generation unit 3 is fed to the data request input 67, the outputs 69 and 71 of the interrupts and addresses are connected to the priority interrupt unit 13 and the accelerated interrupt processing unit 11, respectively.  The request is sent from output 72 to vector command generation unit 3, the address from address output 70 goes to second microprogram memory block 8, and outputs 73 and 74 are connected to system register block 7 and second buffer register block 10, respectively.  Block 11 accelerated interrupt handling (FIG. 5) designed to handle interruptions without pausing the execution of an application program and for scheduling application programs.  The DB input is connected to the 13-priority interrupt unit, input 85 — to the firmware control device 6, input 86 — to the output of the third block 12 of the buffer registers.  The output 87 of the accelerated interrupt handling unit 11 is connected to the priority interrupt unit 13, the output 88 is connected to the firmware control device 6, the information from the output 89 goes to the third block 12 of the buffer registers.  The interrupt handling microprograms are stored in the fixed memory node 83.  SALA 9 is designed to handle scalar operands and calculate addresses.  Block 13 priority breaks for reception. interrupt request signals from block 11 of accelerated interrogation processing and transceiver block 14 and generating, under certain conditions, a signal to transition to an interrupt processing subprogram, and asynchronous reception and storage of interrupt request signals, the interrupt request level code of the interrupt request signal, reception and storing the level code of the processed interrupt and signaling that there is a request for interrupting a higher priority as compared to the processed RAM 15 is intended for storing programs, intermediate results and constants.  The basic unit of addressing is words (sixteen bits).  It is possible to select at the same address a double word located in adjacent memory cells.  The addressing of the program and data is relative, divided into segments of variable length (from sixty-four to sixteen K words corresponding to the natural structural units of the program.  The absolute addresses of the beginning segments are multiples of 64, while storing them in sixteen-bit memory cells, the younger six bits are discarded, since they are equal to zero.  When forming the executive address, these low-order bits are filled with zeroes.  The executive address (thirty-two bits in length) of this or command is formed by adding the base address of the beginning of the data segment (absolute address) to the relative address (fourteen bits in length) contained in the command (direct addressing) or in the memory cell (indirect addressing).  At the same time, the relative address is compared with the length of the segment, and if this address goes beyond the boundaries of the segment, the memory is not sampled / written, and a memory violation violation signal is generated.  The unit for developing and implementing system and application programs is a module.  The program and local data of each module are hardware protected from all other modules, they are divided into tasks, subroutines and drivers.  A module consists of a code segment and a main data segment; commands and data are addressed relative to the beginning of the segment.  Thus, the program and the local data of the module are relocatable.  The module can also address common data located in the zero segment (whose starting address is zero), as well as (indirectly addressing through the zero segment) data in any other data segment.  The module is addressed by the module number, which is the entry number in the task table, two hundred and fifty-six words located in the zero segment.  This table contains the base (absolute) addresses of all modules contained in RAM 15.  The base address of the module is the absolute address of the main data segment of this module.  At the beginning of the main data segment there is a task block containing information about the state of the module and about its connections with other modules.  There is a storage area containing the absolute addresses of the code segment and the additional data segment of this module.  In RAM 15, direct, register, direct and indirect data addressing is used.  The processing unit at the level of machine commands can be either an elementary data (scalar) or a data structure.  The data type combines two characteristics of the data: the element type (scalar type) and the structure type.  The scalar type defines the semantics and format of the elementary data.  A structural type describes the relationships between elements within a single structure.  The scalar (elementary) types are defined: logical data (sixteen bits of a word) character (byte-half-word), integer (word); semaphore (word) and a floating point number (two. adjacent words) A specific range of values is associated with each scalar type.  If the value is outside this range during data processing, an interrupt signal is triggered.  In addition to clearly defined types, they are used implicitly, the output of which is outside the permissible range of which is not controlled by the apparatus.  These include: relative address (word), absolute address (word), index (word) and descriptor (four adjacent words).  The latter contains the structures of the data and is used by the equipment in the execution of vector commands for selecting the elements of the data structure for processing.  The following data types are defined: array; vector; matrix and exchanger (the queue Data structure consists of a set of (possibly empty) scalar data of the same elementary type.  The address of a structured data element is the address of a descriptor describing the parameters of the data structure, in particular the address of the first element of the data structure (the address of the beginning of the data structure).  An array is a continuous area of memory (not exceeding one segment) described by an array descriptor.  The array descriptor contains the initial address of the array (the address of the first element) and the number of elements (the length of the array).  Above an array it is possible to define several regular data structures (vectors or matrices), but all the elements of these structures must belong to the same array.  Regular data structure - the ratio of the order above the array, serves to determine the sample order for processing the elements of the array. The array itself is considered a vector with a length equal to the length of the array, and a step equal to one.  Vector. - a sequence of elements, each of which is assigned an index (from 1 to M, where M is the length of the vector).  The elements of the vector are the elements of a single array, spaced apart by a distance - step fixed for this vector.  The vector is described with the information in the descriptor — the starting address, the number of elements, the sampling step, the ending address.  The matrix is a two-dimensional regular data structure, a sequence of vectors of the same length and pitch.  The matrix is placed in memory along the lines.  The matrix is described by the information in the descriptor, the number of columns, the final address.  At the level of machine instructions for processing, you can select an entire array (a regular data structure), select an arbitrary element of it or.  sequence of elements (subvector) of the vector.  From the matrix, you can select an arbitrary column.  Vector options. or the matrices may dynamically change within the memory region described by the array.  Data type - a queue (exchanger) sets the hard order of elements as a type of queue, the first to come first to go.  The element entered into the queue is automatically considered the last, always the first element is selected from the queue.  Access to an arbitrary element of the queue is not allowed. The queue is characterized by the maximum length (the maximum possible number of elements in the queue) and the current length (the number of elements in the queue at the time of access).  The queue descriptor contains;: the starting address of the memory area allocated for the queue, the index of the first (logical) element in the queue, the index of the last element and the ending address of the memory area.  Both the descriptor and the addressable through it data structure are located in one data segment.  The command system of the control vector computing system is divided into two intersecting, but not overlapping, subsets — the UE command system (blocks 11-13) and the CPU command system (blocks 1-10).  I / O commands, only for the UE, control the physical exchange of information between the RAM 15 and the transceiver unit 14. Both word-for-word (program) exchange and data exchange without intervention of the UE is possible, the control commands identical for the CPU and UE are divided into commands processor controls, setting and removing interrupt masks, setting the operating modes of the corresponding processor for control transfer commands, for changing the sequence of command execution (this group includes both control return commands) and for commands Calls to the control system (US) are formed and queued in the Real-Time Service (USCR) applications for the performance of UCRV functions.  These commands are permissible only on the CPU and are almost always accompanied by switching tasks to 1DP, Exchange and synchronization commands (CPU and UE), serve to ensure the correct interaction and synchronization of tasks performed on

different processors or one processor separating in time. This group includes semaphore and queue teams (exchangers).

Format conversion commands that run only on the CPU convert the numeric data from business to floating point format and vice versa.

Forwarding instructions, executed on both the CPU and 5TI, define the exchange of information between the blocks of registers 2, 10 and 12 and the RAM 15, or between different memory areas. Forwarding commands can forward both individual words and data arrays.

Scalar processing instructions are executed on both the UE and the CPU, and describe logical, arithmetic operations on the scalars, as well as shift operations.

Vector bitwise commands describe the arithmetic, logical and shift operations on the scalars and distribute them into arrays (vectors and matrices). This group includes floating point commands.

Array processing commands describe the operations of transforming the structure of arrays, searching for arrays, and complex arithmetic operations that read the structure of arrays (compound operations).

When describing the command formats used: KOP - opcode; The sign of processing floating numbers, KB — the sampling code that determines the structure of the operands (scalar, vector, matrix); A is the relative address of the operands) J K is the sign of indirect addressing, B is the sign of the base, X is not used.

Combinations of features: with, - indirectly addressing the relative address of this data and data in the main data segment, indirectly addressing the relative address of this data in the zero segment. Figure 6 shows the formats of commands the format of the PP memory-memory (a), the format of the RWS memory-memory - the vector (b), the format of the WAW memory-memory-memory-vector (c) and the format of the PNPM memory Th- Immediate-Memory-Vector f g). The list of processing commands of the control vector computer system

next: scalar processing commands: shifts (logical, cyclic, arithmetic), logical operations on words (logical multiplication, addition, comparison, negation), logical operations on bytes (same logical operations as on words), on right and left ba 1 tam, arithmetic operations on integer vector bitwise processing commands: floating point arithmetic operations (binary operations of a comparison operation, unary operations of an array processing command: search operations (search in vector of floating numbers, definition of the element index, compound operations on vectors (convolution, ie the sum of all elements of a vector, scalar product of vectors, calculation of a polynomial), indexing operations (sampling of an element from a vector of floating numbers into a scalar by index - to scaling a sample of the subvector of elements from a vector of floating numbers on the vector of indices, entering the scalar into a vector on an index-scalar, entering the vector into a vector of indices floating on the vector).

Formats of vector processing commands; vector processing of elementwise processing commands — format of the KPPP; search operations and convolution - format PIV; the scalar product of vectors and the computation of a polynomial is the format of the KIPP; indexing operations format PPPV And PNPV.

The synchronization of the VP and SP is explained in FIG. 7, which shows the service phases of the request with the request fixation symbols in the AS (PPP), the address of the i-th element in RAM 15 (A-RAM calculation of the Ci + 1 address) element () , fixing the request in the DC in block 24 readiness triggers: (FSVP), the exchange between RAM 15 and the first block 2 buffer registers VP (blocks 1-5) (RAM (A) - VP) and waiting for a request from the VP (blocks 1-5 ) (OZVP). The execution of the command of the control vector computing system is carried out as follows. The command is read from the RAM 15 into the system register block 7, decrypted in the firmware control device 6 and executed either on the SALT .9 (scalar commands), or on the scalar 9 and on the vector

Iarithmetic logic devices simultaneously (vector commands).

In the latter case, SALU 9, based on the parameters of the data vectors, calculates the flow of addresses of successive elements of vectors. This stream is fed to the RAM 15 for sampling the data forming the stream to BALLOT, 1, which, having processed them, feeds a stream of data to the RAM 15 simultaneously with the stream of results addresses generated by SALU 9. Device b of the microprogram control using asynchronous signals generated by arithmetic logic devices and 9 and RAM 15, coordinates data flows and addresses.

When an external interrupt occurs from transceiver unit 14 requiring processing, this process occurs in two stages. First, information independently of the firmware control device 6 is read from the transceiver unit 14 and through the priority interrupt unit 13 using the block

The accelerated interrupt handling I1 is entered into the RAM 15. Next, the accelerated interrupt handling unit 11 compares the interrupt priority with the external interrupt mask, if this interrupt is enabled, then the priority of the current task is compared

with the priority of processing the received interrupt. If the latter is higher, then an internal interrupt signal is sent to the firmware control device 6. After receiving it, the firmware control device 6 determines the number of the corresponding processing task and, by the end of the current command, stops the execution of the current task, saves its state, and starts the processing task of the arising external interrupt. Further work takes place in the usual manner.

The vector control computer system can multitask in real time. The maximum number of tasks is 256. Tasks are divided into two groups: application tasks and interrupt processing (maintenance) tasks that can be performed in parallel.

On UE a real-time control system is implemented, consisting of a dispatcher, processing programs

interrupts, internal and external (drivers), and bootloader. Application programs (tasks and procedures) are executed on the CPU. The UE forms priority queues of finished tasks (sixteen priority levels), from which the CPU loads the highest priority task for execution. Drivers are executed on the UE, run on demand, or interrupt. The internal interrupt handling programs Sch1 are started by the control system on the UE when a corresponding request is received from the CPU. On the UE there are eight levels of interrupts, and the appearance of a higher priority signal causes the state of the current program to remain in its local storage area and save the program number. The handle of processing requests from application tasks has the lowest priority.

Depending on the nature of the exchange, the passive device drivers, the initiative device drivers and the passive initiative device driver (the main type) are distinguished. The driver is two-section, i.e. It consists of a start section, a continuation section and is designed as one task with two inputs.

In any moment of time, each user task is in one of the following states: passive, ready, active, blocked (waiting for some event). Tasks are generated (go to the ready state and from the passive state): when loaded into the system (initiative tasks), at the request of other executable tasks. Priority is assigned to the task when planning the main resource of the task of the central processing unit CPU,

Planning discipline: the processor receives the finished task with the highest, the priority is the task with the longest waiting time for the processor. In the active state, the task goes to the locked state, if an I / O request is issued — the task goes to the idle state end of the I / O operation, if the time for suspending the task is set, the task goes to the idle state for the specified time interval, in the case of processing individual situations, when an active interrupt is generated for the internal interruption task, if the task is active, referring to the standard program found that the semaphore is closed, and is in the ready state and sets. At the end of the priority queue, if a higher priority task appears in the ready task queue compared to a task that is in the active state.

In the event of a lock, the blocked task forms a request to the control system and the cause of the interruption, puts it into the system exchanger and goes into the waiting state to handle this situation, the corresponding processing program.

The CPU, after saving the state of the blocked task, immediately loads the next task from the queue of ready tasks of the highest priority.

The proposed control vector computing system in comparison with the known ones has a higher speed and a higher equipment utilization ratio. High performance is provided by reducing the time for interrupting and speeding up the processing of vector information. In the proposed system, this is achieved by separating the processing into the perception of the interrupt signal and storing all the information associated with it in buffers located in RAM and processing this information by processing tasks. The twofold utilization of equipment is achieved by calculating the addresses of the operands of the data elements selected for processing in the HRAM. This is achieved by introducing SALU, which not only performs operations on scalar quantities, but also participates in the execution of vector commands.

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Claims (3)

1. CONTROLLING VECTOR COMPUTING SYSTEM, containing a vector arithmetic logic unit, three blocks of buffer registers, a block of decoders, two blocks of memory of microprograms, a block of system registers, a block of priority interrupts, a block of transceivers, random access memory and a device for microprogram control, while the input and the output of the decoder unit is connected respectively to the first output of the first memory block of the microprograms and the input of the operation code of the vector arithmetic-logic device, input data and output data which are respectively connected to the exit and entry per-. of the buffer register block, the data input of the random access memory is connected to the inputs of the first, second and third buffer register blocks and the input of the transceiver block, the output of which is connected to the address inputs of the system register block and random access memory, the outputs of the first, second and third blocks are buffer; registers and the input of external interrupts of the priority interrupt block, the output of the external interrupt and the input of the current interrupt of the priority interrupt block are connected! respectively, with the input of the transceiver unit and the interrupt output of the microprogram control device, the address output, the write control output of the registers, the command write control output, the command input and the operation code input of which are connected respectively to the address input of the second microprogram memory block, the data register block input, the second input block of buffer registers, the first output of data of 5 block of system registers and the first output of the second block of memory of microprograms, and the second output of data of the block of system registers connected to the input of the second block of buffer registers, characterized in that, in order to improve performance, it contains an accelerated interrupt processing unit, a scalar arithmetic-logic device and a vector command generating unit, including a query feature register, four microoperation decoders, a vector length counter, priority encoder, group of AND elements, register of operation signs, group of triggers SU. „, 1120340 ready, multiplexer, cycle counter” group of delay elements command register and microprogram control unit, read enable input, address input, command input, feature input, interrupt output, address output and feature output of which are connected respectively to the outputs of the delay elements groups, the second output of the first microprogramme memory block, the output of the command register, the multiplexer output, the first input of the priority encoder, the address input of the first microprogramme memory block, and the register clock operation signs, data input, sync input and output of the request feature register are connected respectively to the output of the request feature of the microprogram control device, the output of the first microoperator decoder and the first inputs of the elements AND groups, the second inputs and outputs of which are connected respectively to the output of the first microoperator decoder and the inputs of the group readiness triggers the outputs of which are connected to the inputs of the delay elements of the group, the input of the command register is connected to the output of the second block of buffer registers, the inputs of the first of the second, third, and fourth microdecoding decoders are connected to the second output of the first microprogram memory block, the input and output of the vector length counter are connected respectively to the output of the first block of buffer registers and the first input of the resolution of the operation attribute register, the data input, the second permission input and output of which are connected accordingly, with the output of the signs of the operation of a vector arithmetic-logic device, the output of the first micro-operations decoder and the input of the first 'block of buffer registers, the output is second the microoperation decoder is connected to the input of the loop counter, the second and third inputs and the priority encoder output are connected respectively to the output of the vector length counter, the output of the third microoperation decoder and the data request input of the microprogram control device, and the control input, the first, second and third inputs of the multiplexer data are connected accordingly, to the output of the fourth decoder of microoperations, the output of the signs of the vector arithmetic-logical device, the output of the register of signs of the operation and exit at the cycle counter, the input of microoperations, the data input and output of the scalar arithmetic-logic device are connected respectively to the second output of the second microprogramme memory block, the output and input of the second buffer register block, and the accelerated interrupt processing unit includes a switch, microoperation decoder, feature register, system group registers, multiplexer, super-operative memory unit, microprogram control unit, adder and read-only memory unit, address input, the first and second outputs of which are sub are connected respectively to the address output and address input of the microprogram control unit and the input of the microoperation decoder, the first, second, third and fourth outputs of which are connected respectively to the sync input of the feature register, the input of the adder operation code, the control input of the superoperative memory node and the sync input of the system registers of the group, data inputs the first and second outputs of which are connected respectively to the output of the third block of buffer registers, the first input of the multiplexer and the input of the third block of buffer x registers, the control input, the first and second data inputs and the output of the switch are connected respectively to the first output of the microoperation decoder, the status output of the microprogram control device, the output of the super-memory unit and the input of the characteristics register data, the output of which is connected to the second input of the multiplexer, data input and output the adder are connected respectively to the output of the super-operative memory node and the input of the signs of the microprogram control node, and the read permission input, command input, input when characters, the interrupt output and the output of the characteristics of the firmware control node are connected respectively to the output of the current interrupt of the priority interrupt block, the output of the multiplexer, the second outputs of the system registers of the group, the interrupt polling input of the priority interrupt block, and the task switching input of the firmware control device. 2. The system according to claim 1, characterized in that the microprogram control node comprises a trigger, a command register, a trigger group, an address multiplexer, a microcommand address register, a feature register and an output address register, a data input, a clock input and an output of which are connected respectively to the output micro-command address register, node read permission input and node address output, first, second, third, fourth and fifth data inputs, control input, first. and the second outputs of the address multiplexer are connected respectively to the node's address input, command register output, node command input, trigger output, group trigger outputs, micro-command address register input and output, and node interrupt output, the command register input is connected to the node command input, input and output the trigger are connected respectively to the input of the characteristics of the node and the data inputs of the triggers of the group, the sync inputs of which are connected to the input of the characteristics of the node, and the data input, clock input and the output of the register of signs are connected respectively to the output Am triggers group entry and exit signs node feature node. 3. The system according to claim 1, 'characterized in that the microprogram control device contains four microoperation decoders, two trigger units, three multiplexers, an output decoder, a microprogram control unit and a switch, the data input and the first output of which are connected respectively to the output of the sign of the microprogram control unit and the output of the device status, the data input and the sync input of the first trigger block are connected respectively to the input of the device data request and the first output of the first microopera decoder of the input and the second output of which are connected respectively to the input of the device operation code and the sync input of the second trigger block, the data input of which is connected to the second output of the switch, the inputs of the second and third microoperation decoders are connected to the input of the device operation code, the first, second and third data inputs, the control input and output of the first multiplexer are respectively connected to the task switching input of the device, the output of the first block of triggers, the output of the second block of triggers, the first output of the fourth decoder microoperation indicator and the feature input of the microprogram control unit, the read permission input and address input of which are connected to the device operation code input, the command input, the interrupt output and the address output of the microprogram control unit are connected respectively to the command input, interrupt output and address output of the device, input and second output the fourth microoperator decoder are connected respectively to the input of the device operation code and the control input of the switch, the data inputs of the second and third multiplex the ditch is connected to the input of the device commands, and the control inputs of the second and third multiplexers are connected to the outputs of the second and third microdecoding devices, respectively, and the first and second inputs, the first and second outputs of the decoder are connected respectively to the outputs of the second and third multiplexers, the output of register control and the output of the control recording the commands of the device, and the output of the second block of triggers is connected to the output of the signs of the device requests.