SU742939A1 - Address shaping device - Google Patents

Description

one

The invention relates to computing and can be used to enter telemetry information into a computer.

Devices are known for generating an information channel address comprising memory, registers, and switches that perform the function of selecting a channel and generating its address fl3.

The disadvantage of these devices is low speed.

The closest to the proposed technical entity is a device for selecting information channels and interfacing a channel with a computer, which contains a block of RAM, the output of which is connected to the number register input, a channel pulse counter connected to the channel and marker inputs of the device, and a decoding matrix in which RAM is used as the decoding matrix, the first output of which is connected to the reference element through the phase register, and the second is the device output, the device marker input and additionally connected to the installation inputs of the phase register and the counter

address of the selected channel, the output of which is connected to the RAM address, the output of the channel pulse counter is connected to the second input of the comparison element, and the output of the comparison tape is connected to the control RAM input and the counting input of the counter of the selected channel 2 j.

The disadvantage of this device lies in the low speed and large memory capacity when servicing the information channels of the address structure.

The purpose of the invention is to increase the speed of action.

The goal is achieved by the fact that the device containing the memory block connected by the control input to the control input of the device and the information output to the input of the number register are entered into the address register, two decoders, an adder, two groups of And elements, and a switch, information and management

The 25 inputs of the number register are connected respectively to the address and control inputs of the device, the outputs of the high-order group are connected to the address input of the memory unit, and the outputs of the low-order bits group are connected to the corresponding inputs of the first switch group and the corresponding inputs of the first decoder, the outputs of which connected to the first inputs of the corresponding elements AND of the first group, the second inputs of which are connected to the corresponding outputs of the group of lower races | rDDov number register, and the outputs - through the second decoder to the corresponding p I will give the first input of the adder,; the bits of the second input of which are connected with the corresponding outputs ijpynrai of the upper bits of the register, and the outputs with the first inputs of co-corresponding elements of the second group, the outputs of which are the corresponding outputs of the device and the | high inputs connected to - to the corresponding outputs of the switch, the inputs of the Btdpoti group of which are connected to the corresponding outputs of the group of small numbers; The drawing shows the block diagram of the device. The device contains a block of 1 memory, a register 2 numbers, a register 3 addresses, a cofluter 4, decoders 5 and b, a sum of op 7, elements 8 and 9 of the first and the second groups, and a direct input 10 of the device , controls the input 11 of the device and the output 12 of the device. : The device works as follows. ; Suppose that you want to select and form the address of the channel with the number 45 (101101). When compiling a program, the total number of information channels 64 is divided into 4 groups of 16 channels. The CAPA group of information channels is recorded in one line of block 1 (16 channels for the channel number and 6 cells for W | o (), a regular address). All 64 channels are allocated in 4 lines of block 1: channels 0–15 in the first line, 16–31 in the second, 32–47 in the third, and 48–63 in the fourth. Suppose, for example, that the following information channel, 2,5,6,7,10,12,13,14,33,36,37,42,43,44,45,46, must be selected and formed most of all, with the address of the second Kdnala is the number 1, n of that -f 2, sixth - 3, ..., fourteenth 8, thirty-third - 9, ..., forty n of that, 15, forty-sixth - 16. Pre this choice and sending addresses to Channels whose numbers are not indicated are prohibited. A sign of their selection is the unit recorded in the cells of block 1, which correspond to the listed channels. The initial secondary address in the first line is assigned to channel 2. The formation of secondary addresses for other channels located in this line occurs by summing the initial address G by the number of units located on the left side of the line from the attribute and check. For example, if the second address is assigned to the second channel 000000 (all zeros), then the fifth channel will be assigned the address 100000, and the 14th kaal - 111000 (here and below are the left digits). When writing a program to form secondary addresses of channels intended for selection and located in the 2nd, 3rd or 4th lines of block 1, it is necessary to take into account the number of secondary addresses assigned in the previous lines. For the information channels of the first line to be selected, eight secondary addresses 000000 111000 are formed, therefore in the third line the initial secondary address must be more than eight secondary addresses of the first line (000100). This initial secondary address is assigned to the 33rd information channel. The secondary addresses of the following information channels to be selected are formed similarly to the channels of the first row of block 1. The six-bit address word is sent to register 3. The output information of register 3 is divided into four. The least significant bits (1011) and the two most significant ones (01), the latter are the maximum reading of block 1. At this address, the information of the 3rd line is read, rewritten into register 2. The lower bits go to the decoder 5, at the output of which a unitary code is generated , with a number of units equal to the number represented by the lower bits in the binary code. In this case, this number is 13 and, accordingly, at the output of the decoder 5, a unitary code of 13 units is formed, which controls the operation of elements 8 AND, to the other inputs of which information comes from register 2. Since the unitary code has 13 units, which allows the work of only 13 elements of 8 AND, then to the input of the decoder 6 comes only. 13 least significant bits (left) of register 2, containing 6 units. The decoder 6 converts this information to binary code (IT). To form the secondary information address, obtained from the output of the decoder 6, is added on the adder 7 with the initial secondary address located in register 2. The secondary address formed on the adder 7 is fed to the inputs of the elements 9 And, to the other inputs of which the feature for selecting this channel is received. Switch 4 is set to the position indicated by the lower bits of register 3 (in this case, the 13 position) and switches the corresponding digit of the number contained in register 2 to its output. If the state of the bit at this position is one, then elements 9 of the AND are opened and the number contained in the adder 7 enters the output 12 of the device. If the number at the given position of the number is zero, then the AND elements are blocked until the new address is entered in register 3. In the example in question, the three digit number in register 2 is a single character, therefore the output of code 12 is the number 15 (01110).

Thus, the device provides the choice of cunsch and the formation of its c1dres with a relatively small amount of memory and high speed ..

Claims (2)

Invention Formula A device for generating an address containing memory fleas, connected by a control input to the control input of the device, and an information output to the number register input, characterized in that, in order to increase speed, an address register, two decoders, an adder, two the groups of elements And and the switch, and the information and control inputs of the number register are connected respectively to the address and control input of the device, the outputs of the group older bits to the address input of the memory unit, and the outputs of the group of lower bits to the corresponding inputs of the first switchboard group and the corresponding inputs of the first decoder, whose outputs are connected to the first inputs of the corresponding elements AND of the first group, the second inputs of which are connected to the corresponding outputs the groups of the lower 0 bits of the register are numbers, and the outputs through the second decoder to the corresponding bits of the first input of the adder, the bits of the second input of which are connected to the corresponding outputs of the group Tarsch bit number register rows, and the outputs - the first with corresponding vhodaASh elel eHTOB and second groups, outputs Kogoro are relevant vyhotsami device and second inputs 0 are connected to the corresponding output switch, the inputs of the second group of which are connected to the corresponding output groups of the lower-order ioB register of the number. Sources of information that are considered in the examination1. USSR author's certificate №463968, cl. G06 F 9/20 1973. 0 2. USSR author's certificate 489232, cl. H 04 J 3/00, 1974 prototype t R M eleven