RU2726497C1 - Device for constructing programmable digital microprocessor systems - Google Patents

Abstract

FIELD: software control system.SUBSTANCE: device for constructing programmable digital microprocessor systems comprises an input unit connected by inputs to discrete or digital sensors of a control object, respectively, and by outputs through electronic switches, connected to commutation-computing unit (CCU) and with multichannel operational unit (MOU), calculating arithmetic and logic functions with multi-bit codes, random-access memory unit, output unit (OU), inputs connected to outputs of CCU, MOU units. OU unit is connected to control object by outputs. Device also includes a second memory unit (PROM) with an AND element, inputs associated with the inverse emergency signal and a certain output of the instruction distribution module (IDM), and the output with the input of reading information in the PROM. Information outputs PROM are connected to corresponding inputs of electronic switch of pulse scaler (PS) of program block (PB). PS of the PB unit includes NOT elements, first and second AND elements and an OR element. CCU includes a fourth counting trigger, fourteenth, fifteenth and sixteenth AND elements, a fourth OR element with corresponding links.EFFECT: technical result is broader functional capabilities and faster operation of the device.1 cl, 15 dwg

Description

The proposed device is used to build programmable controllers, systems of logic and program control and regulation of technological objects in various industries, in transport, as well as individual machines and devices, and to create diagnostic and emergency systems capable of simultaneously conducting logical analysis of multi-bit and single-bit discrete signals, coming from the appropriate sensors, followed by the adoption of optimal control decisions, for example, in electrical distribution systems, machines and devices. The device is able to solve problems using propositional and predicate calculi and effectively implement finite state machines sequentially in clock cycles.

A device is known that contains an input unit that receives signals from sensors and generates a certain code at its output, an output unit for storing the results obtained from a multichannel operational and commutation-computing unit, a program unit where the program of the device is stored, a block of random access memory for storing intermediate calculation results, synchronization block, logical channels with functionally changeable triggers, fast transfer block (1).

The disadvantage of this device is limited functionality due to the impossibility of calculating nonlinear functions in the switching computing unit, relatively low speed, a large number of memory cells in the program unit and the RAM unit, a large amount of programming due to the large number of clock cycles and intermediate results in the calculation logical functions containing one-bit and multi-bit variables.

The closest is a device containing an input unit that receives single-bit and multi-bit binary signals from a control object and transmits these signals for conversion to a switching-computing unit and a multichannel operating unit, a random access memory unit where intermediate calculations are stored, a fast transfer unit during arithmetic operations , a module for converting pulses that follow sequentially into a parallel binary code, a program block that controls the operation of all blocks and modules, a synchronization block that ensures the dynamic stability of the device (2).

The disadvantage of this device is the inability to implement nonlinear algorithms by "jumping" during program execution, which is sometimes necessary to shorten the program implementation time and, accordingly, reduce the time lag between the appearance of signals from the sensors of the control object and the action of the controllers and actuators of the control object to an acceptable value. another drawback of this device is the impossibility of the switching-computing unit, regardless of the operation of the multichannel operating unit, to calculate nonlinear algorithms, which narrows the functionality of the device and its performance when calculating nonlinear algorithms

The task is to create a device with enhanced functionality and increased performance.

, C⁰=C24•C22•t1•b`, где С24 и С22 являются входами логического модуля ЛМ и связаны с соответствующими выходами модуля МРК, t1 поступает с выхода элемента НЕ блока 7, b` подключен к выходу шестого элемента И коммутационно-вычислительного блока, а С`, С``, С<sup>0</sup>, С``` это выходы логического модуля ЛМ и соединены выходом С``` с первым входом шестого элемента ИЛИ многоканального операционного блока, а другими выходами с входами соответствующих модулей сдвига разрядов МСР1, МСР2 и МСР3 в каждом логическом канале, причем модуль сдвига разрядов МСР1 находится во всех логических каналах, кроме первого и последнего и реализует логические функции У`1=(b`⊕ b``)•С``, У`2 = (b`⊕ b``)•С`, где У`1 и У`2 являются выходами модуля МСР1 и связаны с третьим и четвертым входами элемента ИЛИ данного и последующего логических каналов, переменные b`, b``, С`, С`` являются входными сигналами для МСР1, причем b`, b`` поступают с выходов первых счетных триггеров данного и последующего логических каналов, С` и С`` поступают с выходов логического модуля ЛМ, модуль МСР2 в первом логическом канале реализует логические функции

, У2=(b1 ⊕ b2) • С`` и У3 = (b1⊕ b2)•С`, где У1, У2 и У3 служат выходами модуля МСР2 и связаны с третьим и четвертым входами элемента ИЛИ первого логического канала и с четвертым входом первого элемента ИЛИ второго логического канала, b1, b2, bn, С`, С`, С⁰ являются входами модуля МСР2 и соединены с выходами первых счетных триггеров первого, второго, последнего логических каналов и тремя выходами логического модуля ЛМ, модуль МСР3 вычисляет логическую функцию

, где сигнал У1``` поступает с выхода модуля МСР3 на третий вход первого элемента ИЛИ последнего логического канала, сигналы b1, bn, С``, С15 поступают на входы модуля МСР3 соответственно с выходов первых счетных триггеров первого и последнего логических каналов, с выхода логического модуля ЛМ и определенного выхода модуля МРК, в многоканальном операционном блоке, где первый вход четвертого элемента И связан с определенным выходом модуля МРК, второй вход соединен с соответствующим выходом блока синхронизации, третий вход подключен к выходу элемента ИЛИ-НЕ, а четвертый вход связан с выходом шестого элемента И коммутационно-вычислительного блока, управляющий вход электронного выключателя связан с определенным выходом первого дешифратора, выход девятого элемента И соединен с первыми входами первых элементов И в каждом логическом канале, вторые входы первых элементов И каждого логического канала, вместе с информационными выходами электронного выключателя многоканального операционного блока связаны с общими шинами системы связи, а выходы первых элементов И в каждом логическом канале соединены с первыми входами элементов ИСКЛЮЧАЮЩЕЕ ИЛИ, общие шины также подключены к выходам первого и второго электронных ключей системы связи и к соответствующим входам блока оперативной памяти и выходного блока, входы первого и второго электронных ключей связаны с определенными выходами входного блока и блока оперативной памяти, управляющие входы первого и второго электронных ключей, блока оперативной памяти и выходного блока соединены с соответствующими выходами дешифратора системы связи, три входа которого связаны с тремя соответствующими выходами a1, a2 и а3 программного блока, второй вход элемента И счетчика импульсов связан с соответствующим выходом блока синхронизации, а выход подключен к управляющему входу электронного ключа счетчика импульсов блока программ, прямые выходы всех первых счетных триггеров связаны с определенными входами модулей сдвига разрядов МСР1, МСР2 и МСР3 в соответствующих логических каналах, восьмой элемент ИЛИ первым и вторым входами связан с вторым и третьим выходами второго дешифратора, а выходом соединен с первым входом шестого элемента И, входы элемента ИСКЛЮЧАЮЩЕЕ ИЛИ подключены к определенной командной шине модуля МРК и к первой Т1 шине из числа общих шин Т1…Tn системы связи, а выход связан с вторым входом пятого элемента ИЛИ, имеется «n» одинаковых схемных фрагментов Ф1…Фn по числу логических каналов, каждый схемный фрагмент связан с соответствующим логическим каналом и содержит логические элементы ИЛИ и ИСКЛЮЧАЮЩЕЕ ИЛИ, причем второй и третий входы элемента ИЛИ связаны с выходом второго элемента И соответствующего логического канала и с соответствующим выходом модуля распределения команд МРК, а выход соединен с первым входом элемента ИСКЛЮЧАЮЩЕЕ ИЛИ, второй вход которого подключен к выходу первого счетного триггера соответствующего логического канала, а выходы элементов ИСКЛЮЧАЮЩЕЕ ИЛИ являются выходами соответствующих схемных фрагментов и соединены с информационными входами электронного выключателя и управляемого элемента многоканального операционного блока, где первый и второй входы первого элемента ИСКЛЮЧАЮЩЕЕ ИЛИ соединены соответственно с выходом шестого элемента И и с определенным выходом модуля МРК, третий управляющий вход управляемого элемента связан с определенным выходом модуля МРК и с соответствующими входами второго элемента И и элемента НЕ дискретного модуля ДМ, коммутационно - вычислительном блок содержит элемент И-НЕ, второй счетный триггер, пятый, шестой, седьмой, восьмой и девятый элементы И, элемент ИЛИ и первый по третий элементы ИЛИ, входы девятого элемента И связаны с выходом элемента ИСКЛЮЧАЮЩЕЕ ИЛИ и с выходом модуля МРК, а выход подключен к входу первого элемента ИЛИ, счетный вход второго счетного триггера соединен с выходом восьмого элемента И, а вход сброса в нуль связан с выходом седьмого элемента И, входы пятого элемента И подключены к выходам дешифратора и второго элемента ИСКЛЮЧАЮЩЕЕ ИЛИ, входы элемента ИЛИ соединены с выходом модуля МРК и с шиной Ст передачи аварийного сигнала, а выход подключен к блокировочному входу дешифратора и к соответствующим входам третьего и двенадцатого элементов И, входы шестого элемента И связаны с выходом второго счетного триггера и с выходом элемента ИЛИ, а выход d` соединен с модулем ЛМ, с входом третьего элемента И всех логических каналов, с соответствующими входами четвертого, пятого и десятого элементов И, с блокировочными входами первого и второго дешифраторов многоканального операционного блока, а также с блокировочным входом дешифратора системы связи устройства, входы восьмого элемента И подключены к выходу блока синхронизации и к выходу первого элемента ИЛИ, входы которого соединены с определенным выходом модуля МРК и с выходом пятого элемента И, выход элемента И-НЕ подключен к третьему входу третьего элемента И, первый вход элемента И-НЕ соединен с соответствующим выходом модуля МРК, два входа первого элемента ИЛИ-НЕ связаны с соответствующим выходом модуля МРК и с выходом элемента ИСКЛЮЧАЮЩЕЕ ИЛИ, а выход подключен к входу девятого элемента многоканального операционного блока, в многоканальном операционном блоке первые входы одиннадцатого и двенадцатого элементов И подключены к выходам модуля МРК, а вторые входы соединены с выходами первых счетных триггеров соответственно первого и последнего логических каналов, а выходы через третий элемент ИЛИ подключены к входу элемента ИЛИ-НЕ, второй вход десятого элемента И связан с выходом модуля МРК, а выход соединен с вторым входом шестого элемента ИЛИ, с определенным входом элемента ИЛИ-НЕ и с первыми входами вторых элементов И всех логических каналов, в каждом из них логический элемент И-НЕ своим первым входом подключен к выходу модуля МРК, а выходом соединенного с третьим входом третьего элемента И в каждом логическом канале, блок ускоренного переноса БУП имеет структуру определяемую логическими функциями (1А), модуль преобразования информации МПИ, содержащий «n» модулей памяти МП, каждый из которых имеет счетный триггер, элемент И, элемент ИСКЛЮЧАЮЩЕЕ ИЛИ, причем в первом модуле памяти имеется еще и второй элемент И, входы сброса в «0» счетных триггеров всех модулей памяти связаны с выходом второго элемента И первого модуля памяти, входы второго элемента И соединены с определенными выходами первого дешифратора многоканального операционного блока и блока синхронизации, счетные входы счетных триггеров всех модулей памяти подключены к выходу элемента И соответствующего модуля памяти, три входа последнего связаны с соответствующими выходами блока синхронизации, первого дешифратора многоканального операционного блока и элемента ИСКЛЮЧАЮЩЕЕ ИЛИ, первый и второй входы которого для всех модулей памяти кроме первого соединены соответственно с выходами счетных триггеров данного модуля памяти и предыдущего, а для первого модуля памяти второй вход элемента ИСКЛЮЧАЮЩЕЕ ИЛИ является входам модуля МПИ и связан с выходом элемента ИСКЛЮЧАЮЩЕЕ ИЛИ коммутационно-вычислительного блока, третий электронный ключ, информационные входы которого связаны с выходами счетных триггеров всех модулей МП, а выходы подключены к общим шинам системы связи, управляющий вход третьего электронного ключа соединен с соответствующим выходом модуля МРК, в каждый логический канал многоканального операционного блока, связь между вторым входом элемента И-НЕ и выходом элемента ИСКЛЮЧАЮЩЕЕ ИЛИ соответствующего схемного фрагмента Ф из набора схемных фрагментов Ф1…Фn многоканального операционного блока, в каждом схемном фрагменте Ф, элемент И входы которого подключены к соответствующему выходу модуля МРК и к выходу первого элемента ИЛИ многоканального операционного блока, а выход связан с первым входом элемента ИЛИ каждого логического фрагмента, коммутационно- вычислительный блок имеет третий триггер, десятый, одиннадцатый и двенадцатый элементы И, второй и третий элементы ИЛИ, элемент НЕ и второй элемент НЕ, причем выход второго элемента ИСКЛЮЧАЮЩЕЕ ИЛИ связан с соответствующими входами элемента И-НЕ и одиннадцатого элемента И, а через элемент НЕ с определенным входом десятого элемента И, другие входы десятого и одиннадцатого элементов И подключены к выходам d`` и S элемента ИЛИ и четвертого триггера, к прямому и инверсному выходам третьего триггера, к выходам модуля МРК и выходу блока синхронизации, а выходы связаны соответственно с входами установки в «0», через третий элемент ИЛИ, и непосредственно в «1» третьего триггера, инверсный выход третьего триггера соединен с четвертым входом третьего элемента И, входы двенадцатого элемента И подключены к определенному выходу модуля МРК, к прямому выходу третьего триггера и к выходу блока синхронизации, а выход связан с первым входом второго элемента ИЛИ, второй вход которого соединен с выходом третьего элемента И, а выход подключен к счетному входу счетного триггера, первый и второй входы третьего элемента ИЛИ связаны с выходами четвертого и десятого элементов И, а выход соединен с входом сброса в «0» третьего триггера, введены первый и второй блоки памяти БП и ППЗУ с соответствующими связями и в счетчик импульсов программного блока введены первый и второй элементы И, элементы НЕ и ИЛИ с новыми связями.To solve this problem in a device for building programmable digital microprocessor systems, containing an input unit that receives discrete signals from sensors and generates a certain binary code at its output, an output unit for recording the values of codes coming from a multichannel operational and switching-computing unit to its memory cells and their transmission, through digital-to-analog converters to electronic devices and electric drive mechanisms, a program unit connected by certain outputs with the MRK command distribution module, a random access memory unit, a synchronization unit and a switching-computing unit consisting of an AND-OR element, an element and the second EXCLUSIVE OR element, eight AND elements, two counting triggers, a decoder connected by three inputs to certain outputs of the MRK module, the first inputs of the first two AND of the AND-OR element are connected to the third and fourth outputs of the decoder, and the second inputs are connected to the output of the input block, from connected by the first and second groups of inputs with a group of information outputs of the control object and with a group of address outputs of the program unit, as well as to the output of the RAM block, the output of the AND-OR element is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to a specific module output MRK, the output of the EXCLUSIVE OR element is connected to the input of the third AND element, connected by other inputs to the outputs d` and S, the output of the synchronization unit, the inputs of the fourth AND element are connected to the output of the MRK module and to the corresponding output of the synchronization unit, and the output is connected to the input of the counter trigger to "0", the output of the second EXCLUSIVE OR element is connected to the information inputs of the output block and the RAM block, the first inputs of the first and second elements AND are connected to the first and second outputs of the decoder, their second inputs are combined and connected to the outputs of the synchronization block, and the outputs connected to the inputs of the output block and the RAM block for control recording information, a multichannel operating unit containing a controlled element, second, fourth, fifth, sixth, seventh through twelfth AND elements, first, third through sixth and eighth OR elements, first and second decoders connected by their inputs to the corresponding module outputs MRK, a controlled memory cell, a controlled trigger, an electronic switch, a NOT element, an element and the first EXCLUSIVE OR element and "n" logical channels operating in parallel, having a similar structure and each of which contains an EXCLUSIVE OR element, three AND elements, an OR element, two counting flip-flop, bit shift modules, while in each logical channel of a multichannel operating unit the output of the EXCLUSIVE OR gate is connected to the first input of the OR gate, the second input of which is connected to the output of the second AND gate, the output of the OR gate is connected to the first input of the third AND gate, the output the latter is connected to the counting input of the first counting trigger, the output to is connected to the counting input of the second counting trigger, while in the multichannel operating unit the output of the first OR element is connected to the second inputs of the EXCLUSIVE OR elements of logical channels, the first and second inputs of the first OR element are connected, respectively, to the outputs of the second decoder and the seventh AND elements, the first and second the inputs of the second AND element are connected to one of the outputs of the synchronization block and to a specific output of the first decoder, and the output is connected to the control input of the controlled flip-flop, the inputs of the OR-NOT element are connected to the corresponding output of the tenth AND element, the output of the first decoder and the output of the third OR element, the first input of the seventh element AND is connected to the corresponding output of the second decoder, the output of the OR-NOT element is connected to the third input of the LM module, the second inputs of the sixth and seventh elements AND are connected, respectively, to the direct and inverse outputs of the controlled memory cell, the information input of which is connected to the output of the second element OR d a sparkling module DM, containing the first and second logical elements AND, the element NOT, the third logical element AND and the element OR, and the inputs of the third logical element And are connected to the outputs of the first counting triggers of the penultimate and last channels, the inputs of the second element And are connected to the output of the third logical element And and with the corresponding output of the MRK module, also connected to the input of the NOT element, the output of the latter is connected to the input of the first AND element, the other input of which is connected to one of the outputs of the PCU block, and the output is connected to the first input of the OR element, the second input of which is connected to the output the second element And, the control input of the controlled memory cell is connected to the output of the fourth element And, in the multichannel operating unit, the information input of the controlled trigger is connected to the direct output of the controlled memory cell, the inverse output of the controlled trigger is connected through one of the common buses of the communication system to the output unit, three control input of the controlled element inens with three command buses of the MRK module and two of them are also connected to the first input of the fifth OR element and to the corresponding input of the first EXCLUSIVE OR element, the output of the fifth OR element is connected to the first input of the ninth AND element, in the switching-computing unit the first inputs of the third and the fourth AND elements, the AND-OR element are connected to the corresponding two outputs of the decoder, and the second inputs are connected to the output L1 of the controlled element of the multichannel operating unit and to the outputs of L2 of the discrete module DM, the inputs of the first and second decoders of the multichannel operating unit are connected to the corresponding command buses of the MRK module , certain outputs of the PCU block are connected to the second inputs of the second AND element of all logical channels, except for the first, the second input of the second AND element of the first logical channel is connected together with the corresponding input of the PCU block to the output of the first EXCLUSIVE OR element of a multichannel operating unit, where the second input of the ninth AND element is connected to a specific output of the first decoder, the inputs of the eighth AND gate are connected to the outputs of the synchronization block and the sixth OR gate, and the output is connected to the first input of the fourth OR gate, the output of which is connected to the reset inputs in "n" of the second counting triggers of all logical channels, the inputs of the fifth element AND are connected to a specific output of the MRK module, output d` and the output of the synchronization unit, and the output is connected to the second input of the fourth OR element and to the reset inputs to "0" of the first counting triggers of all logical channels, a communication system containing common buses, electronic keys , a decoder that generates control signals at its outputs, arriving at the corresponding inputs of the RAM unit, the output unit and two electronic keys, the logical module LM whose structure and its functioning are determined by the logical functions C,,, = (C24 + C22) • b` • t1 , C` = C24 • t1 • b`,

, C ⁰ = C24 • C22 • t1 • b`, where C24 and C22 are the inputs of the logic module LM and are connected to the corresponding outputs of the MRK module, t1 comes from the output of the NOT element of block 7, b` is connected to the output of the sixth element AND of the switching and computing block, and С`, С``, С <sup>0</sup> , С``, these are the outputs of the logic module LM and are connected by the output С``, with the first input of the sixth element OR of the multichannel operating unit, and other outputs with the inputs of the corresponding shift modules of the digits MCP1, MCP2 and MCP3 in each logical channel, and the bit shift module MCP1 is located in all logical channels, except for the first and the last, and implements logical functions Y`1 = (b`⊕ b``) • C``, Y`2 = (b `⊕ b``) • С`, where У`1 and У`2 are outputs of the MCP1 module and are connected to the third and fourth inputs of the OR element of this and subsequent logical channels, variables b`, b``, С`, С` `are input signals for MCP1, and b`, b`` come from the outputs of the first counting flip-flops of this and subsequent logical channels, C` and C `` come from the outputs of the logical module LM, the MCP2 module in the first logical channel implements logical functions

, У2 = (b1 ⊕ b2) • С`` and У3 = (b1⊕ b2) • С`, where У1, У2 and У3 serve as outputs of the MCP2 module and are connected to the third and fourth inputs of the OR element of the first logical channel and to the fourth input the first OR element of the second logical channel, b1, b2, bn, C`, C`, C ⁰ are the inputs of the MCP2 module and are connected to the outputs of the first counting triggers of the first, second, last logical channels and three outputs of the LM logical module, the MCP3 module calculates the logical function

, where the signal U1,,, comes from the output of the MCP3 module to the third input of the first OR element of the last logical channel, the signals b1, bn, C,,, C15 arrive at the inputs of the MCP3 module, respectively, from the outputs of the first counting triggers of the first and last logical channels, with the output of the logical module LM and a certain output of the MRK module, in a multichannel operating unit, where the first input of the fourth AND element is connected to a specific output of the MRK module, the second input is connected to the corresponding output of the synchronization unit, the third input is connected to the output of the OR-NOT element, and the fourth input is connected to the output of the sixth AND element of the switching and computing unit, the control input of the electronic switch is connected to a specific output of the first decoder, the output of the ninth AND element is connected to the first inputs of the first AND elements in each logical channel, the second inputs of the first AND elements of each logical channel, together with information outputs of the electronic switch of the multichannel operating unit connected to the common buses of the communication system, and the outputs of the first AND elements in each logical channel are connected to the first inputs of the EXCLUSIVE OR elements, the common buses are also connected to the outputs of the first and second electronic keys of the communication system and to the corresponding inputs of the random access memory and the output unit, the inputs of the first and the second electronic keys are connected to certain outputs of the input unit and the random access memory unit, the control inputs of the first and second electronic keys, the random access memory unit and the output unit are connected to the corresponding outputs of the communication system decoder, three inputs of which are connected to three corresponding outputs a1, a2 and a3 of the program unit, the second input of the AND element of the pulse counter is connected to the corresponding output of the synchronization unit, and the output is connected to the control input of the electronic key of the pulse counter of the program unit, the direct outputs of all the first counting triggers are connected to certain inputs of the shift modules MCP1, MCP2 and MCP3, respectively the eighth OR element by the first and second inputs is connected to the second and third outputs of the second decoder, and the output is connected to the first input of the sixth AND element, the EXCLUSIVE OR element inputs are connected to a specific command bus of the MRK module and to the first T1 bus from among the common buses T1 ... Tn of the communication system, and the output is connected with the second input of the fifth element OR, there are "n" identical circuit fragments F1 ... Fn by the number of logical channels, each circuit fragment is connected with the corresponding logical channel and contains logical elements OR and EXCLUSIVE OR, and the second and the third inputs of the OR element are connected to the output of the second AND element of the corresponding logical channel and to the corresponding output of the MRK command distribution module, and the output is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to the output of the first counting trigger of the corresponding logical channel, and the outputs of the EXCLUSIVE elements OR are the outputs of the corresponding circuit fragments ntov and connected to the information inputs of the electronic switch and the controlled element of the multichannel operating unit, where the first and second inputs of the first EXCLUSIVE OR element are connected respectively to the output of the sixth AND element and to a specific output of the MRK module, the third control input of the controlled element is connected to a specific output of the MRK module and with the corresponding inputs of the second AND element and the NOT element of the discrete module DM, the switching-computing unit contains the AND-NOT element, the second counting trigger, the fifth, sixth, seventh, eighth and ninth AND elements, the OR element and the first to third OR elements, the inputs of the ninth the AND elements are connected to the output of the EXCLUSIVE OR element and to the output of the MRK module, and the output is connected to the input of the first OR element, the counting input of the second counting trigger is connected to the output of the eighth AND element, and the reset input to zero is connected to the output of the seventh AND element, the inputs of the fifth element And connected to the outputs of the decoder and the second element EXCLUSIVE OR, the inputs of the OR element are connected to the output of the MRK module and to the bus St of the alarm transmission, and the output is connected to the blocking input of the decoder and to the corresponding inputs of the third and twelfth elements AND, the inputs of the sixth element AND are connected to the output of the second counting trigger and to the output of the OR element , and the output d` is connected to the LM module, to the input of the third element AND of all logical channels, with the corresponding inputs of the fourth, fifth and tenth elements AND, with the blocking inputs of the first and second decoders of the multichannel operating unit, as well as with the blocking input of the decoder of the communication system of the device , the inputs of the eighth AND element are connected to the output of the synchronization unit and to the output of the first OR element, the inputs of which are connected to a specific output of the MRK module and to the output of the fifth AND element, the output of the AND-NOT element is connected to the third input of the third AND element, the first input of the AND element is NOT connected to the corresponding output of the MRK module, two inputs of the first element OR NOT connected with the corresponding output of the MRK module and with the output of the EXCLUSIVE OR element, and the output is connected to the input of the ninth element of the multichannel operating unit, in the multichannel operating unit, the first inputs of the eleventh and twelfth elements AND are connected to the outputs of the MRK module, and the second inputs are connected to the outputs of the first counting triggers, respectively of the first and last logical channels, and the outputs through the third OR element are connected to the input of the OR-NOT element, the second input of the tenth AND element is connected to the output of the MRK module, and the output is connected to the second input of the sixth OR element, with a specific input of the OR-NOT element and with by the first inputs of the second AND elements of all logical channels, in each of them the AND-NOT logical element is connected by its first input to the output of the MRK module, and by the output of the third AND element connected to the third input in each logical channel, the block of accelerated transfer of the PCU has a structure determined by logical functions (1A), a module for converting information MPI, containing "N" memory modules MP, each of which has a counting trigger, an AND element, an EXCLUSIVE OR element, and in the first memory module there is also a second AND element, the reset inputs to "0" of the counting triggers of all memory modules are connected with the output of the second AND element of the first memory module, the inputs of the second AND element are connected to certain outputs of the first decoder of the multichannel operational unit and the synchronization unit, the counting inputs of the counting triggers of all memory modules are connected to the output of the AND element of the corresponding memory module, the three inputs of the latter are connected to the corresponding outputs of the synchronization unit, the first multichannel decoder the operating unit and the EXCLUSIVE OR element, the first and second inputs of which for all memory modules except the first are connected, respectively, to the outputs of the counting triggers of this memory module and the previous one, and for the first memory module the second input of the EXCLUSIVE OR element is the inputs of the MPI module and is connected to the output of the EXCLUSIVE element OR switching on-computing unit, the third electronic key, the information inputs of which are connected to the outputs of the counting triggers of all MP modules, and the outputs are connected to the common buses of the communication system, the control input of the third electronic key is connected to the corresponding output of the MRK module, to each logical channel of the multichannel operating unit, connection between the second input of the AND-NOT element and the output of the EXCLUSIVE OR element of the corresponding circuit fragment Ф from the set of circuit fragments Ф1 ... Фn of the multichannel operating unit, in each circuit fragment Ф, the AND elements of which are connected to the corresponding output of the MRK module and to the output of the first OR element multichannel operating unit, and the output is connected with the first input of the OR element of each logical fragment, the switching-computing unit has a third trigger, the tenth, eleventh and twelfth AND elements, the second and third OR elements, the NOT element and the second NOT element, and the output of the second EXCLUSIVE element OR associated with the corresponding The other inputs of the tenth and eleventh AND elements are connected to the d,, and S outputs of the OR element and the fourth trigger, to the direct and inverse outputs of the third flip-flop by the corresponding inputs of the AND-NOT element and the eleventh AND element, and through the NOT element with a specific input of the tenth AND element , to the outputs of the MRK module and the output of the synchronization unit, and the outputs are connected, respectively, to the inputs of the setting to "0", through the third element OR, and directly to the "1" of the third trigger, the inverse output of the third trigger is connected to the fourth input of the third element AND, the inputs of the twelfth of the AND element are connected to a specific output of the MRK module, to the direct output of the third trigger and to the output of the synchronization unit, and the output is connected to the first input of the second OR element, the second input of which is connected to the output of the third AND element, and the output is connected to the counting input of the counting trigger, the first and the second inputs of the third OR element are connected to the outputs of the fourth and tenth AND elements, and the output is connected to the reset input to "0" t the third trigger, the first and second memory blocks of the power supply unit and the EPROM with the corresponding connections are introduced, and the first and second AND elements, the NOT and OR elements with new connections are introduced into the pulse counter of the program unit.

The device consists of the devices shown in FIG. 1 of the input block 1, one group of inputs of which is connected to discrete sensors and binary code sources (not shown in the diagram) X1 ... X _R , and the second group of inputs is connected to the address buses С`1 ... C`j, connected by output i to the input switching - computing unit 2, connected to the RAM block 3, the output unit 4, the program unit 5, the synchronization unit 6, the multichannel operating unit 7, containing "n" logical channels, in the multichannel operating unit MOB 7 the first and second decoders 8 and 9, the second AND gate 12, connected by the first input to a certain output of the synchronization unit, the first OR gate 15, the output of which is connected to the corresponding inputs of all logical channels, the controlled element 16, the controlled memory cell 17, the sixth AND element 18, the seventh AND element 19, the fourth element AND 20, fifth element AND 21, fourth element OR 22, ninth, tenth, eleventh and twelfth elements AND 73, AND 76, I135 and I75, third and sixth elements OR and OR 7 4, the eighth element And 72, connected by one input to the output Z of the element I63 of block 6, electronic switch 77, the element and the first EXCLUSIVE OR element 79 and 103, the eighth OR element 101, controlled trigger 102, the fifth OR element 107, the OR-NOT element 112 and shown in FIG. 10 of a communication system having information common buses 80, a decoder 81 with its inputs connected to outputs a1, a2, a3 ... an ROM60A of the program unit 5, and outputs N1 and N2 connected to the control inputs of the first 82 and second 83 electronic keys, as well as outputs N3 and N4 to two corresponding inputs of the RAM unit and the output unit, also consists of a program unit 5, an MRK command distribution module, a LM logic module, an MPI information conversion module, a BUP accelerated transfer unit and a DM discrete module. There is also the first and second memory blocks BP and EPROM shown in FIG. 12.

The accelerated transfer unit (EPB) has a structure defined by the following logical functions:

где

Where

M1 is the signal from the output of the first EXCLUSIVE OR103 element of the multichannel operating unit 7, arriving at the input of the PCU unit;

M2 ... Mn - transfer signals coming from certain outputs of the BUP block to the corresponding inputs of the second elements I27 of all logical channels, except for the first one in block 7;

Mn + 1 - transfer signal coming from a certain output of the PCU block to the corresponding inputs of the DM module;

В1 ... Bn - signals from the outputs of the first counting flip-flops 29 of the corresponding logical channels of block 7, arriving at the corresponding inputs of the BUP block;

P1 ... Pn - signals from the outputs of all second counting triggers of 30 logical channels of block 7, arriving at the inputs of the BUP block. Signs (•) or (+) in functions mean logical operations AND and OR, respectively.

As follows from the analysis of functions 1A, the BUP block allows parallel implementation of the transfer process along all channels during arithmetic operations.

The devices operate according to the clocks formed in the synchronization block 6, each clock is divided into four pulses of one quarter of the clock, all triggers change their state at one of these pulses, i.e. conventionally in the first, second, third and fourth quarter measures (Fig. 9).

In block 7, the outputs of decoders 8 and 9 are designated respectively e1 ... e7 and D1 ... D3. The words logical element AND (OR, NOT, etc.) and an element with similar designations are the same. If necessary, the decoder 81 according to signals a4 ... an from the output of ROM60A can connect other external units not specified in the description to common buses 80.

The communication system, in our examples, serves to organize the exchange of information signals T1 ... Tn over the buses of the same name between blocks 1, 3, 4 and 7 according to the corresponding signals from the outputs of the program unit 5. When the signal N1 is activated at the outputs of the decoder 81 of the communication system, the first key 82 passes the value of the code Q1 ... Qn from the outputs of the input block 1 to the inputs of the logical channels in block 7 via common buses 80, each of which is designated by T1 ... Tn. In the case of activating the output N2 of the decoder 81, the second key 83 passes through the common buses 80 the code P1 ... Pn from the outputs of block 3 in the form of T1 ... Tn to the inputs of the AND elements 23 of all logical channels. When e3 is activated at the output of the decoder 8 in block 7, the switch 77 passes the value of the code B1 ... Bn from the outputs of the logical channels, through the circuit fragments F1 ... Фn to the common buses 80 in the form of information data T1 ... Tn and when the outputs N3 or N4 of the decoder 81 are activated, the values of T1 ... Tn are fed to the corresponding inputs of block 3 or block 4, when the output C31 is activated at the output of the MRK module, the values of T1 ... Tn from the output of the MPI module are fed through the key 136 to the common buses 80 of the communication system. The ⊕ sign means the logical operation EXCLUSIVE OR.

Through C1 ... C35 are designated command buses (signals) at the outputs of the MRK module, associated with the corresponding inputs of decoders 8,9.37 and logic elements in blocks and modules and control their operation.

Through C`1 ... C`j are designated address buses (signals) that determine the addresses of sources and receivers of information in blocks 1, 3 and 4 and coming from the outputs of program block 5.

X1 ... Xn, ..., Xm ... Xk - multi-bit binary codes (signals), arriving, for example, at the inputs of input block 1 from the outputs of analog-to-digital converters, where the left bits are least significant.

Хк + 1 ... Xr - input single-digit discrete signals from sensors (buttons, limit switches, etc.) arriving at the input block 1

J, T1 ... Tn + 1 - single-bit J and multi-bit information data (signals) at the inputs and outputs of the corresponding electronic keys, switches, blocks, as well as on common buses 80 of the communication system (Fig. 10), entering blocks 3 and 4.

Inputs of blocks, logical channels, logical elements (elements), etc. are indicated by incoming arrows, and exits are indicated by outgoing arrows.

When closed, all electronic keys and switches have high impedance impedance at the outputs.

The words logical element and element in this text and in the claims have the same meaning.

In FIG. 2 shows the structure of logical channels. Each of the "n" channels consists of the first element AND 23, connected with the output to the first input of the EXCLUSIVE OR element 24, the output of which is connected to the first input of the OR element 25, the output of this element is connected to the input of the third AND element 28, the output of which is connected to the counting input the first counting flip-flop 29, the output of which is connected, through the EXCLUSIVE OR 100 element of the corresponding circuit fragment F with the input of the NAND element 26 and directly with the counting input of the second counting trigger 30, the output connected to the corresponding input of the BUP accelerated transfer unit, from the bit shift module of the binary code MCP2 for the first channel, the bit shift module MCP3 for the last channel and bit shift modules MCP1 for the remaining channels, with appropriate connections, the second element I27, connected by the output to the input of the element OR25.

An example of an input block 1 is shown in FIG. 3 and contains a number of electronic keys 32 at the inputs of which the bits of binary codes X1 ... Xn, ..., Xm ... Xk are received and which alternately, at the signal of the first decoder 33, pass the binary code to the outputs Q1 ... Qn, depending on the values of the address commands C`1 ... .C'e coming from certain outputs of the program unit 5, elements And 34 to the first inputs of which the bits of information signals Xk + 1 ... Xr are received, the second inputs of elements And 34 are connected to the outputs of the second decoder 35 and depending on the values of the address commands on the corresponding address buses C`e + 1 ... C`j from block 5, by activating a certain output of the decoder 35, the corresponding bit of information appears at the output of the OR element 36, i.e. at the output of block 1 for one-bit variables.

The switching computing unit 2 included in the device, which implements logical operations with one-bit binary variables coming through the corresponding elements to the input of the counting trigger 43, is shown in FIG. 4 and contains the second element HE140, decoder 37, connected by three inputs to the MRK module, and the first two outputs to the first inputs of the first and second elements AND 38, And 39, and the third and fourth outputs are connected to the inputs of two elements AND of the AND-OR element ( 2-2-2-2И-4OR) 40, the output of which is connected to the first input of the EXCLUSIVE OR element 41, the second input of which is connected to the corresponding output of the MRK module, and the output is connected to the first input of the ninth element I119 and to a specific input of the third element I42, counting flip-flop 43 with one direct output, the reset input to "0" and the input of the third element OR127 are connected to the output of the fourth element I45, the first input of the latter is connected to the corresponding output of the MRK module, and the second input is connected to the output d2 of the synchronization unit 6, output C23 the MRK module is connected to the inputs of the elements HE140 and I119, and the output of the latter is connected to the input of the first element OR117, the inputs of the second element EXCLUSIVE OR 120 are connected to the output of the counting flip-flop 43 and with the output of the MRK module, and the output is connected to the information inputs of the memory cells 57 of the output block 4 and to the corresponding input of the element 51 of block 3, the second counting trigger 47, the counting input of which is connected to the output of the eighth element I116, the inputs of the latter are connected to the output of the first element OR117 and to the corresponding output of the synchronization unit 6, the inverse output of the second counting flip-flop 47 and the output d ,, of the OR element 108 are connected to two inputs of the sixth element I106, the output of which is connected to the blocking inputs of the decoder 81 of the communication system, the inputs of the element I28 of all logical channels and decoders 8, 9 , as well as with the inputs of elements I20, I21 and I76 of block 7, where the second input of element I76 is connected to the corresponding command bus of the MRK module, and the output is connected to a specific input of I27 elements of all logical channels of block 7, in the switching and computing unit the corresponding inputs of the first and the second AND gates of the AND-OR gate (2-2-2-2I-4OR) 40 are connected to the i output of the element 3 6 of block 1 and with the output f of the element 54 of block 3, the first inputs of the third and fourth elements And of the logical element 40 are connected, respectively, to the two outputs e ,, and e`7 of the decoder 37, and the second inputs are connected to the output of the controlled element 16 of block 7 and the output module DM, the second inputs of the first and second elements I38 and I39 are combined and connected to the output d1 of block 6, and the outputs are connected to the input F1 of elements 51 of block 3 and to the inputs of F2 of elements 57 of block 4, certain three inputs of the third element I42 are connected respectively to the output element OR108, with the output Z of block 6 and with the output of element I-HE44, the first and second inputs of which are connected to the output of the second element EXCLUSIVE OR 120 and to the command bus C2 at the output of the MRK module, the sixth output e6 of the decoder 8 of block 7 is connected to the first input element I111 of the block of triggers BT, the second input of the element I111 is connected to a certain output of the synchronization unit 6, the second input of the element I106 together with the blocking input of the decoder 37 of block 2 is connected to the output oome element OR108, the inputs of which are associated with a specific output of the MRK module and with an alarm St from the control object, the third flip-flop 121 with its inverse output H 1 is connected to the fourth input of the third element And 42, and its reset inputs to "1" and reset to " 0 "is connected, respectively, to the output of the eleventh element I123 and through the third element OR127 to the output of the tenth element I122, the corresponding inputs of the I123 and I122 elements are connected to the outputs C30 and C28 of the MRK module, with the output d2 of the synchronization unit 6, with inverse and direct outputs of the third trigger 121 , with the output of the EXCLUSIVE OR element 120 and with the output of the NOT element 128, the input of which is connected to the output of the EXCLUSIVE OR element 120, the twelfth AND element 125 is connected by inputs to the corresponding output of the program unit, to the direct output of the trigger 121 and to a certain output Z of the synchronization unit 6, and the output is connected to the first input of the second element OR124, the second input of which is connected to the output of the third element I42, and the output n It is connected to the counting input of trigger 43, the seventh I94 element is connected with its inputs to the corresponding outputs of the MRK module and the synchronization unit 6, and the output is connected to the reset input to "0" of the trigger 47, the fifth I46 element is connected by its inputs to the outputs of the decoder and the second EXCLUSIVE OR120 , and the output is connected to a specific input of the first OR 117.

An example of a random access memory (RAM) block 3 is shown in FIG. 5 and contains rows of memory cells 48, in some of which the information code (data) T1 ... Tn is written from the common buses 80 by command N3 and pulse d1 arriving at the inputs of the first element And 70 from the output of the decoder 81 of the communication system and block 6, the address of the row memory cells are formed on the address buses С`1 ... С`е of the program unit 5 and the outputs of the decoder 49, Reading the binary code from the output of one of the rows of memory cells 48 is carried out by the electronic key 50 according to the signals from the output of the decoder 49, depending on the values of the signals on the address buses С`1 ... С`е and by command N2, the read code goes to the common buses 80, through the key 83 of the communication system, a number of one-bit memory cells 51 where the results of calculating Boolean functions from the output of element 120 are written on the command from the output of element I 38 of block 2 and in accordance with the signals on the address buses C`e + 1 ... C`j of the program unit 5 and the outputs of the second decoder 52, which also determines the memory cell 51 from where the information bit is read through the elements And 53 and OR 54, writing and reading occurs at different clock cycles of the device.

An example of the structure of the output block 4 is shown in FIG. 6, it consists of rows of memory cells 55, where the values of binary codes T1 ... Tn are written from common buses 80, which are formed at the outputs of logical channels, through circuit fragments F1 ... Fn and switch 77 of block 7, by command from the output of element I 71, at the input of which signals N4 and d1 are received, respectively, from the output of the decoder 81 and from block 6, the addresses of the rows of memory cells are determined by signals on the address buses С`1 ... С`е, coming from the output of the program unit 5 and by activating the corresponding output of the first decoder 56, with the outputs of memory cells 55, the binary code can enter, for example, information systems, digital-to-analog converters, etc., single-bit memory cells 57 are used to record the results of calculating Boolean functions coming from the output of element 120 of block 2 by a command from the output of element And 39 block 2, the address of the memory cell 57 is determined by signals on the address buses C`e + 1 ... C`j and by activating the corresponding output of the decoder 58. Variables from the outputs of cells 57 can be received b on electric drives, alarms, etc.

An example of the diagram of the program block 5 is shown in FIG. 7, it contains three read-only memory devices PZU60A, PZU60B and PZU60S, where the program for the implementation of the task is stored, a pulse counter 59 (FIG. 11) containing elements HE152 and OR111, the first and second elements I151 and I109, an electronic key 85, which controls and the information inputs of which are connected, respectively, with the output of the OR111 element and with the information outputs T`1 ... T`m of the first and second memory blocks of the BP and EPROM, and the outputs are connected to the setting inputs of the counting flip-flops 84, realizing the counting of pulses arriving at the counting input of the first counting trigger 84 from the output of the first element I 63 of the synchronization unit 6, the signals O`1 ... O`m from the outputs of the counting flip-flops 84 are fed to the address inputs of the PROM memory unit and three programmable memories PZU60A, PZU60S and PZU60B, and at each cycle the value of the previously written to these addresses of the program code, from the outputs of ROM60V, the program command code U1 ... Uk is read, connected with the inputs of the coma distribution module nd MRK on the output buses of which, in accordance with the U1 ... Uk program code, distributed command signals (commands) C1 ... C35, entering the blocks and modules of the device and controlling their operation, are read from the outputs of the ROM60S address signals (commands) C`1 ... C`j, associated with the corresponding inputs of the RAM block 3, input and output blocks 1, 4 and determine the addresses at which the binary variables T1 ... Tn selected at this cycle are stored in blocks 1, 3, and 4 for transferring them to other blocks ... Binary signals N1, N2, N3, N4 ... Nm from the outputs of the decoder 81 of the communication system connected by inputs to the outputs a1, a2, a3 ... an ROM60A are determined and alternately connected by clock cycles to external blocks from the set "m", in our example, blocks 1, 3, 4 to the common buses 80 of the communication system (Fig. 10), the input unit 1 is connected by the N1 signal, the output unit 4 by the N4 signal, the random access memory unit 3 is connected by the signal to write N3 and the signal to read N2. MRK module, ROM60A, ROM60V and ROM60C devices are standard ROM or EPROM with the corresponding programming task.

The functional relationship between the outputs and inputs of the electronic key 85 is presented below with St = 1 and C14 = 1

Where R`1… R`m and S`1… S`m are the outputs of the electronic key 85.

T`1 ... T`m - the value of information codes at the output of the first memory block of the power supply unit and the input of the electronic key 85.

Т`1 ... T`m - values of information codes at the output of the second memory block of EPROM.

является инверсией С, знаки «точка» и «плюс» в логических функциях означают логические умножение и сложение, ⊕ знак означающий логическую операцию ИСКЛЮЧАЮЩЕЕ ИЛИ.Binary variable

is the inverse of C, the "dot" and "plus" signs in logical functions mean logical multiplication and addition, ⊕ sign means the logical operation EXCLUSIVE OR.

An example of the circuit and the principle of operation of the synchronization unit 6 are shown in FIG. 8 and FIG. 9, it constantly generates sync pulses (pulses) Z1, d2, d1, Z in every quarter of all clock cycles and contains the first counting flip-flop 62, connected with a direct output to the input of the I63 element, and an inverse output to the first inputs of I64 I115 and I65, the second input the latter is connected to the output of the element And 66, three inputs of which are connected to the direct output of the counting trigger 62, together with the input of the element I64 with the direct output of the counting trigger 67 and the output of the inverter 68, the input of the latter together with the counting input of the flip-flop 62, the inputs of the elements I63 and I64 connected to the pulse generator 69, the output of the I65 element is connected to the reset input to "0" of the trigger 67, another input of the I63 element is connected to the inverse output of the trigger 67, the I115 element is connected by the second and third inputs to the inverse output of the counting flip-flop 67 and to the output of the inverter 68 , also connected by the output to the counting input of the trigger 67, the output Z1 of the element I115 is connected to certain inputs of the element I94 of block 2 and the element I21 of block 7, the output of the Z element I63 is connected to the corresponding inputs of element 84 of block 5, element 72 of block 7 and elements I42, I125 of block 2, output d2 of element I64 is connected to the corresponding inputs of elements I45, I122, I123 of block 2, output d1 of element I66 is connected to inputs of elements 28 of all logical channels, elements I38, I39, I116 of block 2, elements I70 and I71 of blocks 3 and 4, element I12 and element I20 of block 7, The connection of clock pulses with logical elements of the device determines the possible sequence of operations when implementing the algorithm at each cycle of its operation in accordance with Fig. ... 9, flip-flop 67 is reset to zero by a single signal from the output of element I65.

Let us assume that all other triggers (memory cells) are triggered by the trailing edge of the pulses arriving at their control, reset and counting inputs. Before starting work, all triggers and memories are set to "0".

The principle of operation of block 2 (Fig. 4) consists in the sequential implementation of Boolean functions in the basis AND, OR, EXCLUSIVE OR, NOT, AND-NOT, OR-NOT conventionally presented in the form of a disjunction of conjunctions or conjunction of disjunctions in the basis AND, OR, for less than with an analogue and a prototype, the number of clock cycles without referring to the memory cells of block 3 for storing and reading intermediate results in the computation process, as well as in controlling the processes in blocks 3, 4, 5 and 7, corresponding to signals from the output of the decoder 37.

Before calculating Boolean functions, the counting flip-flop 43, by a signal from the output of the element I45, is set to the zero state, i.e. its output Tr is similar in name to the signal at its output, is equal to "0" and the third flip-flop 121 is set to zero by the same signal and its inverse output H1 = 1. Flip-flop 43 switches when a single signal is supplied from the output of element I42, passing through the element OR124 to its counting input at the end of the pulse Z, which is supplied in the fourth quarter of each cycle, the third flip-flop 121 is set to a single state i.e. at its direct output H = 1 with unit values at the inputs of the I123 element at the end of the second quarter of the cycle according to the pulse d2 arriving at each cycle and in the zero state, i.e. at its inverse output H1 = 1 in the second quarter of the cycle with unit values at the inputs of the I122 element or with a single pulse at the output of the I45 element (Fig. 9). The calculation of logical functions in the switching-computing unit 2 will be illustrated by the example of calculating the bracket function Y 1 containing the AND, OR functions.

NOT, AND-NOT, OR-NOT, EXCLUSIVE OR:

, где

where

X1 ... X9 - binary variables alternately supplied at each cycle in accordance with the values of the commands С4 ... С6, С9 ... C11, С2 and address signals С`1 ... С`е, from one of blocks 1, 3, 7 or BUP, for example from input block 1, to the input of the AND-OR40 element of block 2 and further, at a certain value of the commands C1, C2, C29, C25 and the signal H1 = 1, the next input variable from X1 ... X9 or its inversion, through the elements I41 and I42 is fed to counting input of the trigger 43 in the form of a pulse Z (Fig. 1, Fig. 4). Moreover, in the case C1 = 1, the corresponding variable from X1 ... X9 is inverted in the EXCLUSIVE OR 41 element.

равна нулю при любом значении Х2 и продолжать ее вычисление на следующем такте нет смысла. Для этого следует блокировать работу триггера 43 на втором такте работы устройства. Если Х1=0 триггер 43 не изменит своего состояния и Тр=0, а значение функции Х1+Х2 не известно и следует продолжить вычисление функции Х1+Х2 на следующем такте. Этот выбор автоматически осуществляется установкой С29=0 на втором такте работы в соответствии со значениями сигнала Тр на выходе триггера 43 и определенных командных сигналов. Выход элемента НЕ140 связан с входом элемента И42.On the first clock cycle, at C1 = 0, C2 = 1, C3 = 1, C28 = 0, C29 = 0, C30 = 1, C25 = 0 The value of X1 comes through the AND-OR elements 40, I41 and I42 to the counting input of the trigger 43 and if X1 = 1 then, after the end of the pulse Z, at the output Tr of the trigger 43 appears "1". It is obvious that in this case the subfunction

is equal to zero for any value of X2 and it makes no sense to continue calculating it on the next cycle. To do this, block the trigger 43 on the second clock cycle of the device. If X1 = 0 trigger 43 does not change its state and Tr = 0, and the value of the function X1 + X2 is not known and the calculation of the function X1 + X2 should be continued at the next cycle. This selection is automatically carried out by setting C29 = 0 at the second cycle of operation in accordance with the values of the signal Tr at the output of the trigger 43 and certain command signals. The output of the HE140 element is connected to the input of the I42 element.

, а если Х2=0, то триггер 43 не изменит своего состояния, а результат вычисления функции

и на выходе Тр триггера 43 в любом случае будет находиться инверсия результата вычисления функции

и если Тр=0, т.е. функция

, при этом вычислять функцию У2 нет смысла т.к. функция У2=1. При этих условиях работу счетного входа триггера 43 следует заблокировать с третьего такта и до конца четвертого такта, исключая поступление переменных Х3 и Х4 на счетный вход триггера 43, а также инвертировать значение сигнала на выходе Тр, чтобы он прямо соответствовал результату вычисления функции Х1+Х2 и функции У2. При необходимости такой принцип блокировки работы триггера 43 будет осуществляться и на других тактах. Если по окончанию второго такта Тр=1 (Х1+Х2=0), то следует продолжить вычисление функции У2, т.к результат вычисления функции У2 не известен.On the second cycle of operation, the command signals C1 = 0, C2 = 1, C3 = 0, C28 = 0, C29 = 0, C30 = 0, C25 = 0 are set, and at Tr = 1 (X1 = 1), the operation of the counting input of trigger 43 is blocked zero signals from the outputs of the elements I-HE44 and I42, and if Tr = 0 (X1 = 0) there is no blocking of trigger 43 and the corresponding variable X2 comes from the output of the element I-OR40, through elements I41 and I42 to the counting input of trigger 43 and at X2 = 1 trigger 43 will change its state, i.e. Tr = 1 and the result of calculating the function

, and if X2 = 0, then trigger 43 will not change its state, and the result of calculating the function

and at the output Tr of trigger 43, in any case, there will be an inversion of the result of calculating the function

and if Tr = 0, i.e. function

, and it makes no sense to calculate the function Y2 since function Y2 = 1. Under these conditions, the operation of the counting input of trigger 43 should be blocked from the third cycle to the end of the fourth cycle, excluding the arrival of variables X3 and X4 at the counting input of trigger 43, and also to invert the signal value at the output Tr so that it directly corresponds to the result of calculating the function X1 + X2 and functions U2. If necessary, this principle of blocking the operation of the flip-flop 43 will be carried out on other clock cycles. If at the end of the second cycle Tr = 1 (X1 + X2 = 0), then the calculation of the function Y2 should be continued, since the result of calculating the function Y2 is not known.

Х4 не определен и вычисление надо продолжить на четвертом такте, а если Х3=0, то триггер 43 переключится и Тр=0 и результат вычисления функции Х3

Х4 известен и равен нулю. В этом случае результат вычисления всей функции У2 равен нулю т.к. X1+Х2=0 и Х3

Х4=0. При этом работу счетного триггера 43 следует блокировать на следующем четвертом такте работы.On the third cycle, the command signals C1 = 1, C2 = 1, C3 = 0, C28 = 0, C29 = 1, C30 = 1, C25 = 1 are set and if after the second cycle Tr = 0 (Y2 = 1), then the output J of the EXCLUSIVE OR 120 element is equal to "1" and the third trigger 121, in the second quarter of the third cycle, changes its state to one (H = 1, H1 = 0)) and the trigger 43 is blocked by the zero outputs of the I42 and I45 elements and until the end of execution commands for calculating the function U2. those. the values of the variables X3 and X4 will not be able to enter the counting input of the trigger 43 and change its state, while in the fourth quarter of the third cycle, a single pulse Z, from the output of the I125 element, through the OR124 element will switch the trigger 43 into a single state i.e. Tr = 1 and at the output of the flip-flop 43 there is a result of calculating the function Y2 = 1, which is stored until the end of the execution of commands for calculating the function Y2. And if after the second cycle Tr = 1, then at the output J of the EXCLUSIVE OR 120 at the beginning of the third cycle there is a "0" and the trigger 121 will not switch to the single state, there is no blocking of the trigger 43 and the calculation of the function Y2 will continue since X1 + X2 = 0, while the inversion of the variable X3 from the output of the element I-OR40 will go through the elements I41 and I42 to the counting input of trigger 43 and if X3 = 1 then trigger 43 will not change its state and Tr = 1, while the result of calculating the function X3

X4 is not defined and the calculation must be continued on the fourth cycle, and if X3 = 0, then trigger 43 will switch and Tr = 0 and the result of calculating the function X3

X4 is known and equal to zero. In this case, the result of calculating the entire function Y2 is zero, since X1 + X2 = 0 and X3

X4 = 0. In this case, the operation of the counting trigger 43 should be blocked at the next fourth cycle of work.

и Х3•Х4=0. Из этого следует, что если в конце четвертого такта значение на выходе триггера 43 равно «0», т.е. если Тр=0, то значение функции У2=0, а если Тр=1, то значение функции У2=1, а это значит, что при Тр=0(У2=0) вычислять функцию У3 нет смысла, т.к. при этом известно значение логического произведения двух функций У2•У3=0 и работу триггера 43 надо заблокировать до конца вычисления функции У3, а при Тр=1 (У2=1) следует продолжить вычисление функцию У3 т.к. значение У2•У3 не известно.On the fourth cycle at C1 = 1, C2 = 1, C3 = 0, C28 = 0, C29 = 1, C30 = 0, C25 = 0, in the case of Tr = 0, the counting input of trigger 43 is blocked by zero signals from the outputs of the I-HE44 , elements I42 and I125 keeping the value of the entire function Y2 = 0 at the output of trigger 43, and at Tr = 1 and the zero state of trigger 121 (H1 = 1) there is no blocking of the operation of trigger 43 and the inversion of variable X4 comes from the output of the element I-OR40, through elements I41 and I42 to the counting input of trigger 43 and if X4 = 0, then trigger 43 will switch and Tr = 0, which means that the function X3 • X4 = 0 and the result of calculating the entire function Y2 = 0, since

and X3 • X4 = 0. It follows from this that if at the end of the fourth cycle the value at the output of the flip-flop 43 is equal to "0", i.e. if Tr = 0, then the value of the function Y2 = 0, and if Tr = 1, then the value of the function Y2 = 1, which means that when Tr = 0 (Y2 = 0) it makes no sense to calculate the function Y3, since in this case, the value of the logical product of two functions Y2 • Y3 = 0 is known and the operation of trigger 43 must be blocked until the end of the calculation of the function Y3, and when Tr = 1 (Y2 = 1), the calculation of the function Y3 should be continued since the value of Y2 • Y3 is not known.

On the fifth cycle, at C1 = 1, C2 = 0, C3 = 0, C28 = 1, C29 = 1, C30 = 1, C25 = 0, if at the beginning of the cycle Tr = 0, then the signal J = 1 and in the case of a zero state trigger 121 (H1 = 1) at the inputs of the I123 element there are only single signals and the single output of the I123 element will switch on the pulse d2, in the second quarter of the cycle, the trigger 121 into the single state (H1 = 0), while the signal H1 = 0 triggers the trigger 43 will be blocked by zero signals from the outputs of elements I42 and I45 until the end of the execution of commands for calculating the function U3, since in this case Y2 • Y3 = 0 if Tr = 1. then J = 0, at the output of the element HE128 there is a single signal and if the third flip-flop 121 was in a single state from the beginning of the third cycle, then at the inputs of element I122 there are only single signals and a single signal from the output of element I122 through element OR127 will switch the flip-flop 121 to the zero state (H1 = 1), this removes the blocking of the trigger 43. And if the trigger 121 was in the zero state at Tr = 1 and J = 0, then it does not change its state (H1 = 1) and there is no blocking of trigger 43 through the elements I41 and I42, the inversion of the variable X5 from the output of the AND-OR40 element is fed to the counting input of the flip-flop 43 and if X5 = 0, then the flip-flop 43 in the fourth quarter of the clock pulse d1 will change its state, i.e. output Tr = 0, and if X5 = 1, then trigger 43 will not change its state, i.e. output Tr = 1 and in any case the calculation of the function X5 ⊕X6 continues.

On the sixth cycle, for any value of C29 and with C1 = 0, C2 = 0, C3 = 0, C28 = 0, C30 = 0, C25 = 0, the value of the variable X6 comes from the output of the AND-OR40 element through the I41 and I42 elements to the counting input flip-flop 43 and if X6 = 0, then the state of flip-flop 43 will not change, and if X6 = 1, then flip-flop 43 will switch and in any case, the output of flip-flop 43 will present the result of calculating the function X5⊕ X6, i.e. at the same values of the variables X5 and X6 at the output of Tr there is "0" and at different values of X5 and X6 at the output of Tr there is a "1". Obviously, when X5 ⊕ X6 = 1 (Tr = 1), the function Y3 = 1 and there is no point in continuing to calculate it, therefore, the operation of trigger 43 should be blocked at the appropriate time periods until the end of the calculation of the function Y3, and if X5 ⊕ X6 = 0 (Tr = 0), then the calculation of the function Y3 should be continued since in this case, the result of its calculation is not known.

, а значит функция У3=1 и функция У1=У2•У3+Х9=1 не зависимо от значения Х9 и этот результат имеется на выходе Тр триггера 43. В этом случае следует блокировать работу триггера 43 до конца вычисления функции У1, а если Х7=1 то триггер 43 не изменит своего состояния и Тр=0, результат вычисления функции

не известен и работу по ее вычислению следует продолжить на следующем такте.On the seventh cycle of work with C1 = 1, C2 = 1, C3 = 0, C28 = 0, C29 = 0, C30 = 1, C25 = 0 and if after the sixth cycle Tr = 1 (X5 ⊕X6 = 1), J = 1 and in the case of the zero state of the trigger 121 (H1 = 1) in the second quarter of the seventh cycle, according to the pulse d2, it switches to the single state (H1 = 0) and until the end of the calculation of the function Y3, the operation of the trigger 43 is blocked by the signal H1 = 0 and, accordingly, zero the outputs of the elements I42 and I45, while at the output Tr of the flip-flop 43, a single result of calculating the function Y3 = 1 is stored. And if after the sixth clock cycle Tr = 0 (X5 ⊕X6 = 0), J = 0, \ and the trigger 121 is in the zero state (H1 = 1), then there is no blocking of trigger 43 and the inverse value of the variable X7 will go to the counting input of the trigger 43 and if X7 = 0, then flip-flop 43 will switch and its output Tr = 1, while the function

, which means that the function Y3 = 1 and the function Y1 = Y2 • Y3 + X9 = 1 regardless of the value of X9 and this result is available at the output Tr of trigger 43. In this case, the operation of trigger 43 should be blocked until the end of the calculation of the function Y1, and if X7 = 1 then trigger 43 will not change its state and Tr = 0, the result of calculating the function

is not known and the work on its calculation should be continued in the next cycle.

On the eighth cycle with C1 = 1, C2 = 1, C3 = 0, C28 = 0, C29 = 0, C30 = 1, C25 = 0 and if after the seventh cycle Tr = 1, J = 1 and trigger 121 is in the zero state (H1 = 1), then the trigger 121 in the second quarter of the cycle on the pulse d2 switches to the single state and the signal from its inverse output H1 = 0 blocks the operation of the trigger 43 with zero signals from the outputs of the elements I42, I45 and I125, and if after the seventh cycle Tr = 0 and trigger 121 is in the zero state (H1 = 1), then there is no blocking of trigger 43 and the inversion of the variable X8 is fed through the AND-OR elements 40, I41 and I42 to the counting input of the trigger 43. If X8 = 0, then the trigger 43 will switch into a single state, i.e. Tr = 1 and at the same time the function X7 • X8 = 1, and the function Y3 = 1 and the function Y1 = Y2 • Y3 + X9 = 1 regardless of the value of X9 and this single result is at the output Tr of trigger 43, and the trigger should be blocked 43 on the next measure since the value of the function Y1 is determined, and if X8 = 1, then the flip-flop 43 will not switch and at its output Tr there will be a zero result of calculating the function Y3 i.e. Y3 = 0 and at Tr = 0 the calculation of the function Y1 should be continued taking into account the variable X9.

Continuing the description of the above process on the eighth cycle, at the beginning of the ninth cycle at C1 = 1, C2 = 1, C3 = 0, C28 = 1, C29 = 0, C30 = 1, C25 = 0 for the entire period of the ninth cycle and in the case of Tr = 0 and at the zero state of trigger 121 (H1 = 1) there is no blocking of the counting input of trigger 43 and the inversion of the variable X9 follows from the output of the AND-OR40 element, through the I41, I42 and OR125 elements to the counting input of the trigger 43 and if X9 = 0 , then the flip-flop 43 changes its state at the end of the pulse Z in the fourth quarter of the cycle (Tr = 1) and at its output a single result of calculating the entire function Y1 = 1 is set, and if X9 = 1, then the trigger 43 does not change its state, i.e. to. the variable X9 is inverted to "0" in the EXCLUSIVE OR41 element and at the output of the trigger 43 there is a zero result of calculating the function Y1 = 0.

And if at the end of the eighth cycle, Tr = 1 is set, then at the beginning of the ninth cycle at H1 = 1, J = 1 trigger 121 is set to a single state, blocking the operation of trigger 43 with a zero signal at the inverse output H1 of trigger 121 and the value of variable X9 is not supplied to the counting input of the flip-flop 43 with zero signals at the outputs of the elements I42 and I125, and at the output Tr of the flip-flop 43 there is a single result of calculating the function Y1 = 1.

In the case when on the fifth cycle at Tr = 0 (Y2 = 0) the operation of the trigger 43 was blocked by the signal Н1 = 0, from the inverse output of the trigger 121, until the end of the calculation of the function Y3, at the ninth cycle it follows, with a single output of the element HE128 and at C28 = 1, H = 1, switching the trigger 121 to the zero state in the second quarter of the ninth cycle by pulse d2 and removing the blocking of the trigger 43 by a single signal H1 and then the arrival of the inversion of the variable X9 at the counting input of the trigger 43 and if X9 = 0, then the trigger 43 in the fourth quarter of the ninth clock by the pulse Z will change its state (Tr = 1) and at the output of trigger 43 there will be a single result of calculating the function Y1, and if X9 = 1, then trigger 43 will not change its state (Tr = 0) and its output we get the zero result of calculating the function Y1. When C23 = 1, the HE140 element blocks the operation of the trigger 43.

In the case, as described above, when operating on the seventh cycle, setting the trigger 121 to the single state (H1 = 0) in the second quarter of the seventh cycle and until the end of the calculation of the function Y1 and the corresponding blocking of the trigger 43 at the seventh cycle at Tr = 1 and H1 = 0 , the single state of the trigger 121 and the blocking of the trigger 43 will remain at the ninth cycle, because at the ninth cycle from the output of the element HE128 to the input of the element 122, a zero signal is received, and at the output Tr of the trigger 43 there will be a single result of the calculation of the function Y1. As can be seen from the example, the choice of one or another continuation in the process of calculating a given Boolean function at each cycle is realized automatically, depending on the state of triggers 43 and 121 at the previous cycle, the values of the corresponding variable X and command signals "C" at this cycle. So, for any values of the variables X1 ... X9 at the end of the ninth cycle of operation of block 2, the output of the trigger 43 will be the result of calculating the function Y1. As can be seen from the above example, the block 2 scheme allows calculating the logical function in a new way based on the analysis of the result of calculating the first conjunction equal to "1" in the disjunction of the conjunctions and then fixing this result until the end of the calculation of the entire disjunction, rightly considering that this result is known and equal to " 1 ", and when calculating the conjunction of disjunctions in the case of a zero result of the very first disjunction, this result is fixed until the end of the calculation of the entire conjunction of disjunctions, rightly assuming that the value of the entire conjunction of disjunctions, which includes the specified disjunction, is equal to" 0 ". This approach can significantly reduce the number of clock cycles when calculating logical functions. Command signals "C" are formed at the stage of programming the process of calculating a given logical function.

необходим дополнительный такт для записи Z1 в блок оперативной памяти 3 и еще один дополнительный такт для записи результата вычисления функции X3•X4=Z2 в блок 3, затем еще 3 дополнительных такта для считывания переменных Z1 и Z2 из блока 3, вычисления функции Z1+Z2=У2 и запись результата У2 в блок 3. Еще два дополнительных такта требуется для записи в блок 3 результатов промежуточных вычисления функций Х5 X6=Z3 и X7•X8=Z4 и затем еще три дополнительных такта для считывания переменных Z3 и Z4 из блока 3, вычисления функции Z3+Z4=y3 и запись У3 в блок 3, затем еще три дополнительных такта для считывания из блока 3 значений У2 и У3, вычисления функции У2•У3 и запись результата вычисления У2•У3 в блок 3 и еще один дополнительный такт для считывания функции У2•У3 и вычисление функции У1=У2•У3+Х9. Итого для вычисления в прототипе функции У1 понадобилось четырнадцать дополнительных тактов, т.е для вычисления функции У1 в прототипе всего потребовалось 23 такта работы, что существенно выше, чем в предлагаемом устройстве.Thus, in block 2, for any values of the variables X1 ... X9, the functions of the Boolean algebra are calculated, containing the above set of logical functions, in a minimum number of clock cycles equal to the number of variables included in the Boolean function, without accessing the memory cells of the RAM block 3 for storing intermediate the results of calculations and their use in the process of calculating the entire Boolean function, as required in the analog and prototype. For example, when calculating the function U1 in the prototype after calculating the function

an additional cycle is needed to write Z1 to block 3 of random access memory and another additional cycle to write the result of calculating the function X3 • X4 = Z2 to block 3, then another 3 additional cycles to read the variables Z1 and Z2 from block 3, calculate the function Z1 + Z2 = Y2 and writing the result Y2 to block 3. Two more additional clock cycles are required to write to block 3 the results of intermediate calculations of the functions X5 X6 = Z3 and X7 • X8 = Z4 and then three more additional clock cycles to read variables Z3 and Z4 from block 3, calculating the function Z3 + Z4 = y3 and writing U3 to block 3, then three additional clock cycles for reading the values of У2 and У3 from block 3, calculating the function У2 • У3 and writing the result of calculating У2 • У3 to block 3 and one additional clock cycle for reading the function Y2 • Y3 and calculating the function Y1 = Y2 • Y3 + X9. In total, it took fourteen additional clock cycles to calculate the U1 function in the prototype, i.e., to calculate the U1 function in the prototype, it took 23 work cycles, which is significantly higher than in the proposed device.

In block 7, with C15 = 1 and C20 = 0 at the control inputs of the controlled element 16, the latter implements the logical OR function, if C20 = 0 and C15 = 0, then element 16 implements the logical function EXCLUSIVE OR, if C15 = 1 and C20 = 1, then element 16 implements the EXCLUSIVE OR function of the last two bits of the binary code at the outputs of circuit fragments Ф1 ... Фn, and when C15 = 0 and C20 = 1, a signal from the output of the last logical channel appears at the output of element 16, when C15 = 0, C20 = 0 and C19 = 1 at the output of element 16 of block 7, the value of the first bit of the binary code written in the triggers 29 of the logical channels of block 7 appears.

The operation of the device consists in calculating logical functions in block 2 with the simultaneous implementation of operations on multi-bit binary codes in block 7 and, if necessary, the device ensures the joint operation of blocks 2 and 7, for example, in the case of studying the given and received (received) binary codes and making decisions based on the results logical analysis of the results. The device operates according to the clock cycles formed in block 6.

We will explain the operation of the device using several examples. Suppose that C15 = 1 and the operation of decoders 8, 9, 81 and 37 is not blocked by the input signals d` and d``.

Let's compare two binary numbers A1 and A2 and suppose that A1 = A2 and both are expressed by the binary code 11001011. Here and below, the most significant bits on the right. Suppose the number A1 is in block 1 in the form of X1 ... Xn and n = 8, and the number A2 is stored in the block of random access memory 3 in the values P1 ... Pn and n = 8, i.e. block 7 has eight logical channels. The equality of the numbers is determined by the method of algebraic addition of the numbers A1 and -A2, everywhere a negative number is represented in the reverse code, we assume that C22 = 1 and C24 = 0. At the first clock cycle, the values X1 ... X8, with the corresponding values С`1 ... С`е, С13 = 1, С24 = 0, С15 = 1 and N1 = 1, will come from block 1, through the key 82 to the common buses 80 of the communication system and then to the inputs of the fourth elements AND 23 of all logical channels of block 7, where, according to the commands C9 ... C11, the output e1 of the decoder 8 and the number A1 are activated with a single output of the element AND 73, through the elements EXCLUSIVE OR 24, OR 25, AND 28 and d1 = 1, will be written into the counting triggers 29. On the second cycle, with the corresponding signals С`1 ... С`е and N2 = 1 in block 3, the corresponding output of the decoder 49 is activated and from the output of key 50 the number A2, through key 83 and common buses 80 of the communication system to the inputs of the elements AND 23 of all logical channels and at D1 = 1 on the signal from the outputs of the elements OR 15 and EXCLUSIVE OR 24, OR 25 and AND 28, the inversion of the number A2 will go to the counting inputs of the counting triggers 29 of all logical channels and at d1 = 1 it is implemented by bit function EXCLUSIVE OR for numbers A1 and -A2, while at the outputs of counting triggers 29 of all logical channels are set to single values, the counting trigger 43 of block 2 is set to state "0" by signal C3 = 1.

On the third cycle, when C19 = 1 C21 = 1, C18 = 1, d` = l logical "1" from the output of the EXCLUSIVE OR element 103 and I27 of the first channel will go to the corresponding inputs of the OR elements 25 and the PCU block and the logical "1" from the output M2 of the PCU block will appear at the input of the AND element 27 of the second logical channel and then, in accordance with the functions (1A), by single signals M3 ... Mn from the PCU block, through the AND 27, OR 25 and AND 28 elements of subsequent channels, with a pulse d1 = 1, all counting triggers 29 will switch to the "zero" state, i.e. the result of the difference of two equal numbers A1 and A2 appeared, and all triggers 30 will switch to state "1" and a single information will be recorded from the output Mn + 1 of the PCU block at C20 = 0, through the DM module into the memory cell 17 by signal "1" with output element And 20 block 7.

On the same third cycle at C15 = 1, logical "0" from the outputs of circuit fragments F1 ... Fn, through the OR element 16 in the form of a logical "0" at the output L1, with the corresponding signals C4 ... C6 on the command e,, from the output of the decoder 37 block 2 enters, through element 40 to the input of element 41 of block 2 and at C1 = 1, C2 = 0, d1 = 1 and C3 = 0, the logical "1" enters the counting input of the trigger 43 and after the pulse Z = 1 a single signal value appears at the output of the counting flip-flop 43 and this means that A1 = A2.

On the fourth clock cycle, a logical "1" from the output of the counting trigger 43, with certain commands C4 ... C6 and activation of the corresponding output of the decoder 37 of block 2 and the output of the I element 39 with a pulse d1 = 1 coming from the output of the I element 66 of block 6, will be written to a certain values Ce ... Cj memory cell 57 of the output unit 4, as information that A1 = A2.

Consider the second example of comparing two binary numbers, when A1 <A2 and A1 = 11001011, and A2 is equal to 10011011, triggers 29, 30 and 43 are set to zero, triggers 29 and 30 in all logical channels are transferred to zero states at pulses q1 and q2 , and the flip-flop 43 is set to zero at C3 = 1.

On the first clock, by analogy with the first example, with the corresponding command and address signals, the number A1 is written into the counting triggers 29 by bits in each logical channel of block 7.

On the second cycle, when N2 = 1, similarly to the first example, when D1 = 1, the inversion of the number A2 is fed to the inputs of the elements AND 28 and at d1 = 1 the unit values of the digits of the number A2 change the state of the counting triggers 29 to the opposite and the output of triggers 29 will be the result A1 ⊕ (-A2) i.e. 10101111, while in the second logical channel the trigger 29 changed its state twice in two clock cycles, which led to a change in the state of the second counting trigger 30 on this channel from zero to one and the fact of transfer from the second bit to the third or from the second logical channel to the third in the BUP block, which occurs in similar situations in all logical channels of block 7.

On the third cycle, when D2 = 0, D3 = 0, C19 = 0, C18 = 1, d` = 1 logical zero, from the output the EXCLUSIVE OR elements 103 are fed to the corresponding inputs of the I27 element of the first logical channel and the BUP block and further in accordance with functions (1A) of the PCU block, the process of transferring to the corresponding logical channels takes place according to signals from the output of the PCU block, which are simultaneously fed to the inputs of the I27 elements of certain logical channels and at the outputs of triggers 29 of all logical channels, the image of the algebraic sum A1 + (- A2), code 10011111, is set, in the third quarter of the cycle at d1 = 1, at the same time on the signal from the output of the element I 20 at C21 = 1, the zero transfer Mn + 1 will be written from the output of the DM module, at C20 = 0, into the memory cell 17 of block 7, while the zero value on the output Mn + 1 of the BUP block shows that the absolute value A1 <A2 and the result of the algebraic sum in the reverse code is obtained. On the third clock in its fourth quarter, according to the signal e`7 = 1 from the output of the decoder 37 of block 2, the value Mn + 1 = 0 from the output of the BUP block through the DM module, at C20 = 0, is fed to the output of the AND-OR element 40 of the block 2 and when C1 = 0 at the output of the EXCLUSIVE OR element 41, a logical "0" is formed and at the output of the counting flip-flop 43, a logical "0" will remain.

On the fourth cycle, with C15 = 1, C20 = 0 and e`` = 1, the value L1 = 1 from the output of the OR element 16 of block 7 will enter, through the AND-OR element 40 to the input of the AND element 41 and with C1 = 1 at the output of the latter “0”, the value of the trigger 43 does not change and the result of the logical sum (Mn + 1) + L1 = 0, which confirms that A1 <A2.

On the fifth clock cycle, the result obtained above from the output of the counting flip-flop 43 of block 2 with the corresponding decoder command 37 and d1 = 1, in accordance with the signal at the output of the element AND 39, will be written to block 3 or 4 into one of the memory cells at the corresponding address C`e ... C`j.

If in the way described above, in block 2, with C1 = 0, the logical function L1 • (Mn + 1) and if the function L1 • (Mn + 1) = 1, then A1> A2.

Let's go back to the third step, when the image of the algebraic sum of two numbers A1 and -A2 was obtained and we continue solving the problem to determine the result of calculating the algebraic sum A1 + (- A2).

On the third clock cycle, when С``18 = 1, the transfer process, formed at the outputs of triggers 30 and then in the PCB block, will be completed, while through the elements AND 27, OR 25, AND 28 logical channels, the transfer values will go to the counting inputs of triggers 29 and at impulse d1 = 1, their outputs will display an image of the algebraic addition of the numbers A1 and -A2, if the absolute value of the number A1 is greater than the number A2, i.e. / A1 /> / A2 /, then on the fourth measure, add one to the value of A1 + (- A2) and obtain the desired result A1 + (- A2), and if / A1 / </ A2 /, the result of addition A1 + (- A2) should be inverted and then we get the desired result of addition A1 + (- A2) in the direct code with an indication of its sign.

In order to implement the above algorithm, the multichannel operational unit 7 has an eighth OR element 101 and the corresponding connections. The inputs of the OR element 101 are connected to the outputs D2 and D3 of the decoder 9, and the output is connected to a specific input of the AND element 18, the other input of which is connected to the direct output of the controlled memory cell 17, and the output of the I18 element is connected to the first input of the first EXCLUSIVE OR element 103, the output K2 which is connected to the input of the second element I27 of the first logical channel and to a certain input of the BUP block, and the output K1 of the element And 19 is connected to one of the inputs of the first element OR 15, two inputs of the element I19 are connected to the inverse output of the memory cell 17 and the input D2 of the decoder 9 of the block 7.

The proposed scheme works as follows. If / A1 /> / A2 /, then on the third cycle of operation in the memory cell 17 of block 7 at, C21 = 1 by the signal from the output of the element And 20 and at the pulse d1, a single transfer from the most significant bit is written, i.e. from the output Mn + 1 of the BUP block through the DM module at C20 = 0, and at the pulse Z = 1, all triggers 30 will be reset since O1 = 1.

On the fourth step, with C19 = 0, D2 = 1, C18 = 1, K1 = 0 and K2 = 1, to the number A1 + (- A2), with d1 = 1, a single transfer through the EXCLUSIVE OR 103, AND 27, OR elements will be added 25, And 28, and at the outputs of triggers 29, the value of the required sum A1 + (- A2) is formed with a minus in the sign bit (Mn + 1 = 1)

In our example, if / A1 / </ A2 /, then on the third cycle the value Mn + 1 = 0 from the output of the BUP, through the DM module with C20 = 0 and C21 = 1, will be written to memory cell 17.

On the fourth cycle, after resetting triggers 30 in the previous cycle with Z = 1, with C24 = 0, D2 = 1, K1 = 1 and K2 = 0 by the signal from the output of the OR element 15 after the pulse d1 = 1, in the third quarter of the cycle, the image of the code A1 + (- A2) will be inverted and the result of the algebraic sum A1 + (- A2) with a minus in the sign bit (Mn + 1 = 0) will appear at the outputs of triggers 29.

Further, the result obtained can be written to the RAM block 3 at e3 = 1 and N3 = 1 or to the output block 4 at e3 = 1 and N4 = 1 at the next fifth cycle. The algorithm proposed below and the corresponding scheme make it possible to do this on the same fourth clock cycle, reducing the total number of clock cycles for the implementation of algebraic addition and recording the result in blocks 3 or 4, with C27 = 1.

To do this, block 7 has "n" identical circuit fragments F1 ... Fn by the number of logical channels, each of which (Fig. 13) contains two elements: OR 99 and EXCLUSIVE OR 100, in each circuit fragment three inputs of OR 99 are connected, respectively with the output of the I126 element, with the output of the AND element 27 of the corresponding logical channel and the output of the MRK command distribution module, the inputs of the I126 element are connected to the corresponding output of the MRK module and to the output of the OR element 15 of block 7, and the output of the OR element 99 is connected to the first input of the EXCLUSIVE OR element 100. the second input of which is connected to the output of the trigger 29 of the corresponding logical channel, and the output is connected to certain information inputs of the electronic switch 77 and the controlled element 16 of block 7. Circuit fragments F1 ... Fn allow you to record the result obtained or its inversion (C33 = 1) with a pulse d1 = 1 into blocks 3 or 4 on the fourth cycle of computation at certain values of address and command signals, and will also reduce is the number of clock cycles in the bitwise interconnected implementation of the AND, OR functions.

Let's return to the fourth step of calculating the algebraic sum A1 + (- A2). If / A1 /> / A2 / then Mn + 1 = 1 and at C19 = 0, A1 = 1, D2 = 1, and K2 = 1 in block 7 from the output of the EXCLUSIVE OR element 103 to the input of the AND element 27 of the first logical channel logical "1" and by transferring through the BUP block, it will go to the inputs of the AND elements of 27 certain logical channels, and then from the outputs of the corresponding elements I27 to the inputs and outputs of the OR elements 99 of the corresponding circuit fragments and taking into account the signals at the outputs of the triggers 29, at the outputs elements EXCLUSIVE OR 100 of all circuit fragments F1 ... Fn, the desired value of the sum A1 + (- A2) will appear, which can be written according to certain address signals C`1 ... C`j, for example, in RAM block 3 at the same clock cycle with signal N3 = 1 from the output of the decoder 81 of the communication system. When / A1 / </ A2 / and D2 = 1, K1 = 1, at the output of the OR element 15 of block 7, a logical "1" will appear, which will come with C27 = 1 to the inputs of the OR 99 elements and then to the inputs of the EXCLUSIVE OR 100 elements of all circuit fragments, while at the outputs of the last elements the result of the sum A1 + (- A2) will appear, which can be written to the RAM block through switch 77 at N3 = 1. The introduction of circuit fragments increased the speed of the device due to the fact that at C33 = 1 by the output of the MRK module, using the circuit fragments F1 ... Fn, it is possible to invert the code at the outputs of flip-flops 29 at the same clock cycle and, at N3 = 1, C27 = 1, write this inversion according to certain address signals С`l ... C`j and N3 = 1 , for example, into the block of random access memory 3, which obviously follows from the analysis of the operation of circuit fragments F1..Fn.

A controlled trigger 102 of unit 7 connected by a control input to the output of the AND element 12 and an information input to the direct output of the memory cell 17, and the output to the Tn + 1 bus, which determines the sign of the difference between two numbers and allows this sign to be stored for any number of clock cycles of the device, when the state of the memory cell 17 can change .. The inputs of the element And 12 are connected with a specific output of the decoder 8 of block 7 and with the output of the element 66 of the synchronization unit 6. Bus Tn + 1 is connected to the corresponding input of the output block 4. Single command D1 from the output of the second decoder 9 block 7 allows to invert the value of the code written in triggers 29 on an additional clock.

The bit shift module MCP1 for each logical channel in block 7, in addition to the first and the last, has two outputs Y`1 and Y`2 and four inputs C`, C``, b`, b``, its operation is determined by Boolean functions:

where the first output Y`1 is connected to the third input of the first OR element 25 of this logical channel, the second output Y`2 is connected to the fourth input of the OR element 25 of the next channel, input b` is connected to the output of the counting trigger 29 of this logical channel, input b ,, connected to the output of the first counting flip-flop 29 of the next logical channel, inputs C` and C`` are connected to the corresponding outputs of the logic module LM.

The bit shift module MCP2 of the first logical channel has three outputs U1, U2, U3 and six inputs b1, b2, bn, C`, C ,,, C ⁰ and its operation is determined by Boolean functions:

, С⁰ = C24•C22•t1•d`, С```= (C24+C22)•t1•d`, где С24, С22 являются входными командными сигналами для логического модуля ЛМ и поступают на его входы с выходов модуля МРК, t1 является выходом элемента ИЛИ-НЕ112 блока 7, a d` является выходом элемента И106 блока 2.where the first output U1 is connected to the fourth input of the OR element 25 of the first logical channel, the second output U2 is connected to the third input of the OR element 25 of the same channel, the third output of U3 is connected to the fourth input of the OR element 25 of the second logical channel, the input b1 is connected to the output of the first counting trigger 29 of the first logical channel, inputs b2, bn are connected to the outputs of counting triggers 29 of the second and last logical channels, inputs С`, С ,, С ^{0 are} connected to the corresponding outputs of the logical module LM, in which the outputs are determined by logical functions С` = С24 • t1 • d`,

, С ⁰ = C24 • C22 • t1 • d`, С``` = (C24 + C22) • t1 • d`, where С24, С22 are the input command signals for the logic module LM and are fed to its inputs from the outputs of the MRK module , t1 is the output of the OR-HE112 element of block 7, ad` is the output of the I106 element of block 2.

и функционирует в соответствии с булевой функцией:The bit shift module MCP3 of the last logical channel has one output U1 ,,, five inputs bn, C ,,, C15, b1,

and functions according to a boolean function:

where the output U1,,, is connected to a certain input of the OR element 25 of the last logical channel, the inputs b1, bn are connected, respectively, to the outputs of triggers 29 of the first and last logical channels, input C,, is connected to the corresponding output of the logical module LM, C15 is connected to a certain output MRK module. Before the shift of the digits, triggers 30 are set to "0".

The shift of the code bits down from the first to the last logical channel is carried out by the command С` = 1, with С`` = 0, t1 = 1, С <sup>0</sup> = 0. In this case, for the MCP2 module, if b1 = 1, and there is a logical "0" at the output of the trigger 29 of the second logical channel, then, in accordance with functions (3) and (5), a logical unit will be set at the output of U1 and it will also appear on the output of the OR element 25, will enter the input of the AND element 28, and when d1 = 1, the trigger 29 of the first channel will change its state to zero. At the same time, if the signals at the inputs b1, d2 are not equal, the output U3 is activated and the logical "1" will be fed to the input of the AND element 28 and at the end of the d1 pulse the output of the trigger 29 of the second channel will take the opposite value, i.e. the value that was at the output of the flip-flop 29 of the first logical channel. At the same time, in the MCP1 modules, in accordance with function (2), if the signals at the outputs of the triggers 29 of this and subsequent logical channels are not equal, the U`2 output is activated in all MCP1 modules and the logical "1" through the corresponding elements OR 25 will go to the inputs of the AND elements 28 of the corresponding logical channels and at the output of the trigger 29 of each subsequent channel will appear the value of the output of the trigger 29 of this logical channel i.e. there will be a downward shift of the bits of the code previously recorded in triggers 29.

The upward shift of the code bits takes place in the presence of the command С`` = 1, when С` = 0, С <sup>0</sup> = 0, t1 = 1 and С15 = 0. Then, in accordance with the functions (1) ... (6), outputs U2 in the MCP2 module, Y`1 in the MCP1 module and the output U1,,, in the MCP3 module can be activated, while the U2 output is activated if the input signals b1, b2 at the inputs MCP2 modules are not equal, and in this case, through the OR element 25 to the input of the AND element 28 of the first logical channel, a logical "1" will arrive and the trigger 29 of the first channel will take the value of the trigger 29 of the second logical channel. At the same time, for any MCP1 module in case of inequality of signals b`, the output U1` and logical "1" are activated, through the OR element 25 it will enter the input of the AND element 28 of this channel, where the corresponding MCP1 module is located and the output value will be set at the output of the trigger 29 of this logical channel trigger 29 of the next logical channel. At the same time, when bn = 1, the output U1,,, of the MCP3 module is activated and a logical "1" will appear at the output of the AND element 28 and the trigger 29 of the last logical channel will go to the state "0". Thus, there will be a shift from bottom to top of the bits of the code written in triggers 29.

The presence of the LM logical module in the device made it possible to organize the cyclic shift of binary codes upward with the transfer of the least significant bit to the senior one at C15 = 1, which follows from the analysis of the logical formula (6) for the MCP3 module and downward with the transfer of the most significant bit to the least significant bit at the value C ⁰ = 1, which directly follows from the analysis of formula (3), which determines the value of Y1 in the MCP2 module.

A single value of the direct output of the controlled memory cell 17 in block 7 means the presence of a transfer, for example, after the arithmetic addition of n bits of two binary numbers, the transfer value to the next n + 1 bit is activated when D3 = 1 at the output of the decoder 9 of block 7 and will arrive through the elements I18, EXCLUSIVE OR103 and OR13 to the input of the AND element 27 of the first logical channel of block 7.

To determine even or odd numbers, the EXCLUSIVE OR element 79 was introduced into block 7, the inputs of which are connected to the first bus T1 and the command bus C21 of block 5, and the output is connected to the input of the OR element 107 of block 7, which reduced the number of ticks when determining an even number or an odd number and writing it to logical channels when C21 = 1 or C21 = 0.

The switching computing unit 2 included in the device, which implements logical operations with one-bit variables coming through the corresponding logical elements to the input of the counting trigger 43, contains a logical element I-HE44, which has a direct connection with its inputs to the corresponding output of the MRK module and the output of the second element EXCLUSIVE OR 120, and the output with the third input of the third element I42, blocking the operation of the counting flip-flop 43 with a single output of element 120 and with C2 = 1. In block 2, the second counting flip-flop 47 is connected by the counting input to the output of the eighth element I116, the reset input to "0" is connected to the output of the seventh element I94, and the inverse output through the element I106 is connected to the blocking inputs of decoders 8 and 9, also to the inputs of the tenth element I76 and the fourth and fifth elements I20 and I21 of block 7 and decoder 81, which allows blocking the operation of blocks 3, 4 and 7 with multi-bit binary codes, while block 2 can continue to work with one-bit binary codes according to its specified program with C32 = 1.

The discrete module DM (Fig. 14) contains the first, second and third elements I110, I113 and I104, elements HE114 and OR105, and the inputs of the I104 element are connected to the outputs of the first counting triggers 29 of the penultimate and last logical channels, and the output is connected together with the output C20 MRK to the inputs of the I113 element, and C20 is fed to the input of the HE114 element, the output of which is connected to the first input of the I110 element. From the L2 output of the OR element 105, the value Mn + 1 from the BUP block is written to the memory cell 17, which arrives at the second input of the I110 element with C21 = 1 and C20 = 0 to determine the negative sign or determine the overflow during arithmetic operations, and when C21 = 1 and C20 = 1 is written, through the elements I113 and OR105, the value of the logical AND function of the last two bits of the binary code written in the triggers 29 of the corresponding logical channels of block 7. In block 7, the first EXCLUSIVE OR element 103 allows you to invert the signal at the output of the AND element 18 by command C19 and forward it to the output block.

The L2 signal from the output of the DM module, at the command e`7 = 1 from the output of the decoder 37 of block 2, can be written into the counting trigger 43 with the value C23 = 0 or into the second counting trigger 47 by the commands C23 = 1 in block 2 for further use in logical operations.

The inclusion in each circuit fragment F1 ... Fn of the connection between the output of the EXCLUSIVE OR100 element, which is the output of each circuit fragment F and the input of the I26 element of block 7, as well as the introduction of the AND element connected by inputs to the corresponding outputs of the program block 5 and the OR15 element of block 7, and the output of the connected with the input of the element OR99 of each circuit fragment F1 ... Fn, allows to conduct or block the computational process in logical channels, depending on the state of the outputs of the corresponding triggers 29 and the values of the signals at the inputs of the I-HE26 element, which leads to a reduction in the number of clock cycles in the bitwise interconnected calculation of OR functions and And or vice versa AND and OR. With this in mind, we will show by examples the interconnected bitwise implementation of the OR and AND or AND OR functions in logical channels, when after the bitwise implementation of the OR function, the AND function should be calculated bitwise taking into account the result of the bitwise OR, or vice versa .. Analytically, you can write for the first case (A1 + A2 + … + An) • An + 1 • An + 2 •… • An + m, for the second case A1 • A2 •… • An + An + An + 2 +… + An + m, where A are multi-bit binary variables (binary codes). In the process of calculation at the outputs of MCP1, MCP2, MCP3 and element I27 there are zeros. Let us show the calculation process using the example of the bitwise calculation of the function (A1 + A2) • A3 • A4, where A1, A2, A3, and A4 are multi-bit binary codes stored in the RAM block 3.

On the first clock cycle in each logical channel with the corresponding commands and a single pulse, all triggers 29 are set to "0".

On the second cycle, with C26 = 0, D1 = 0 and N2 = 1 with zero output of the OR15 element of block 7 and the corresponding address and command signals, the value of the multi-bit variable A1 is supplied from the RAM block 3, through the elements I23, EXCLUSIVE OR24, OR 25 and I28 to the counting input of the flip-flop 29 and at its outputs the value of the A1 code appears after the d1 pulse. At zero values at the outputs of the trigger 29 of the corresponding bits, the calculation should be continued, since the result of the bitwise calculation of the function A1 + A2 is not yet known, and if there are logical units in the corresponding bits at the outputs of triggers 29, then the result of calculating the function A1 + A2 in these bits is known and equal to "1" and the operation of these triggers should be blocked.

On the third cycle, with the corresponding address and command signals and with C26 = 1, C27 = 0, N2 = 1 and D1 = 0, the A2 code will come from block 3 to the inputs of the I28 element and triggers 29 with single outputs are blocked by the zero output of the I-HE26 element and do not change their state, and triggers 29 with a zero output are not blocked, and when a single signal appears in the corresponding bit, the trigger 29 changes the output value to a single one. In this case, at the outputs of triggers 29 of all digits, there are the results of the bitwise calculation of the function A1 + A2. Further, those triggers 29 for which the outputs have "0" should be blocked, because the result of calculating the entire function (A1 + A2) • A3 • A4 in these digits is already known and equal to "0" and is stored until the end of the calculation.

On the fourth cycle, with the corresponding address and command signals and with C26 = 1, C27 = 0, N2 = 1 and D1 = 1 with a single output of the OR15 element, the A3 code inversion will go through the I23, EXCLUSIVE OR24 and OR25 elements to the inputs of I28 elements and triggers 29, having a zero output, are blocked by the zero outputs of the I-HE26 elements and the corresponding bits of the A3 code are not received at their counting inputs, and the inversions of the corresponding bits of the A3 code are received at the counting inputs of the triggers 29, which have single outputs, and in the case of their single value and, accordingly, zero values in the A3 code, triggers 29 change their output to zero and the outputs of triggers 29 present the result of the bitwise calculation of the function (A1 + A2) • A3.

On the fifth cycle, with the corresponding address and command signals and with C26 = 1, C27 = 0, N2 = 1, D1 = 1, the inversion of the A4 code from block 3 will come through the elements I23, EXCLUSIVE OR24, OR25 not the input of element I28 and with single outputs of triggers 29 corresponding bits, the inversion of the A4 code bits will go to the counting inputs of these triggers and in the case of single values of these inversions, triggers 29 will switch to a zero state at the output, and in those logical channels (bits) where there are logical zeros at the outputs of triggers 29 blocking of these triggers, and at the output of triggers 29 at the end of the fifth cycle there is the result of the bitwise calculation of the function (A1 + A2) • A3 • A4. This took five clock cycles of the multichannel operating unit. In the case of the bitwise implementation of this function in the prototype and analogue, an additional 1 cycle will be required to write the result of the bitwise calculation A1 + A2 = B1 into the RAM block 3, after that another 1 cycle to set all triggers 29 to the state "0" before the bitwise calculation of the function A3 • A4, another 1 clock cycle to send the result of the implementation of the function A3 • A4 = B2 to block 3, another 1 clock cycle to set all triggers 29 to "0" before calculating the function A3 • A4, 2 more clock cycles to read the obtained intermediate results from block 3 В1 and В2 and bitwise calculation of the function В1 в2 and at the outputs of triggers 29 the result of bitwise calculation of the function (А1 + А2) †A3 в2 will appear in 5 + 6 = 11 clock cycles of the device, which is significantly more than in the proposed device.

Similarly, consider an example of a bitwise calculation of the inverse function A1 • A2 + A3 + A4 in the logical channels of block 7. At the beginning, with zero outputs of the elements I 27 and all modules of the MCP and with R = 0, D1 = 1, C26 = 1, C27 = 0 and N2 = 0, set all triggers 29 to a single state. Later on the second and third clock cycles, according to the corresponding address and command signals and at R = 1, D1 = 1, C26 = 1, C27 = 0, N2 = 1, the corresponding bits of the binary codes A1 and A2 are supplied from the RAM block 3 to the counting the inputs of those triggers 29 at the outputs of which are logical "1", the remaining triggers 29 are blocked by zero signals from the output of the I26 element, and at the end of the third cycle, at the end of the d1 pulse, the outputs of triggers 29 will display the result of the bitwise calculation of the function A1 • A2. Further, with the corresponding address and command signals and with D1 = 0, R = 1, C26 = 1, C27 = 0, N2 = 1 from block 3 at the fourth and fifth clock cycles A3 and A4 codes are alternately received at the counting inputs of those triggers 29 for which the outputs have logical "0", and triggers 29 with single outputs are blocked by the zero outputs of the I26 element, and after the end of the fifth cycle, the outputs of triggers 29 will contain the result of the bitwise calculation of the function A1 • A2 + A3 + A4. When calculating this function bitwise in an analog or prototype, an additional 1 clock cycle is required to transfer the intermediate function A1 • A2 = B2 to the RAM block 3, another 1 clock cycle to set triggers 29 to "0" before the bitwise calculation of the A3 + A4 function, another 1 clock cycle to transfer the result of the calculation A3 + A4 = B1 to block 3, another 1 clock cycle for setting the triggers 29 to the zero state before the bitwise calculation of the B2 + B1 function and 2 more clock cycles for the bitwise implementation of the B2 + B1 function. In total, it took 11 clock cycles to implement the function A1 • A2 + A3 + A4, which is significantly more than in the proposed invention. This is due to the fact that in the analogue and the prototype there is no way to block the operation of the trigger 29 with a signal from the output of the AND element 26 at a zero value at the output of the trigger 29, and also it is impossible to change the state of the trigger 29 when its output is single and when C26 = 1. The proposed implementation of the bitwise calculation of the AND and OR functions by one counting trigger 29 allows in each logical channel of block 7 to reduce the number of logical elements and communication lines, which simplifies their structure while maintaining their functionality.

Elements I75, I135 are connected by the first inputs to the corresponding outputs C19 and C20 of the MRK module, and the second inputs to the outputs of the first flip-flops, respectively, of the first B1 and the last Bn of logical channels of block 7 and the element OR11 connected by inputs to the outputs of elements I75 and I135, and the output with one of the inputs of the OR-HE112 element of block 7 allow blocking the shift of the bits in the logical channels with C19 = 1 and B1 = 1 or with C20 = 1, Bn = 1. In FIG. 12 shows the introduced first memory block (PSU), containing memory cells by the number of counting triggers 84 in the pulse counter of the program unit, in which a binary code is written in advance, in any way, that ensures the start of the emergency routine, the outputs of the memory cells are the outputs of the first PSU block. When an emergency signal St = 1 appears, the binary code from the output of the memory cells of the power supply unit is fed to the inputs of the electronic key 85 of block 5 and, on the signal from the output of the element I151 at St = 1, through the element OR111 of the pulse counter 59, the binary code from the output of the power supply unit will be written to impulse d2 of block 6 into the counting triggers 84 of block 5 and the execution of the emergency subroutine will begin. The first element I151 of the pulse counter 59 of block 5 is connected by inputs to the output d2 of block 6 and the alarm signal St, and the output to the first input of the element OR111. To reduce the number of clock cycles, when implementing nonlinear algorithms using interruption (jumping), a second PROM memory block (Fig. 12) is introduced, containing a memory with reprogrammable read-only memories, an I150 element connected by inputs to the output of the command C14 of the MRK module and with the inversion of the emergency signal st i.e. with the output of the element HE152 of the impulse counter 59, the alarm signal ST is sent to the input of the element HE152. The EPROM block provides the process of changing the direction of the implementation of nonlinear algorithms, depending on the result of previous calculations. At the beginning, binary codes are written into the memory of the EPROM block at certain addresses O`1 ... O`m, at which "jumps" are possible when executing a program with the implementation of nonlinear algorithms and at St = 0 and C14 = 1 the binary code of a possible "jump" appears on information output of the EPROM memory block. Further along the pulse d2, this binary code may or may not be written at the corresponding values of d` from the output of element I108 of block 2, to triggers 84, the value of d` depends on the result of previous calculations written to trigger 47 of block 2. Depending on the results of previous calculations d`, the program can make a "jump", and can continue the sequential execution of this subroutine followed by a "jump" through an unselected subroutine, when, at the appropriate clock cycle, the value of d1 will change its state to the opposite at C12 = 1. Element I150 of the EPROM unit is connected by inputs with the command C14 of the MRK module and with the inversion of the emergency signal St, and the output is connected to the input of permission to read the binary code from the memory elements of the EPROM memory unit. The second element I109 of the pulse counter of block 5 is connected by inputs to the d2 output of the synchronization unit 6, to the d 'output of the I106 element of block 2, to the command C14 of the MRK module and to the output of the HE152 element. Element OR111 is connected by the second input to the output of element I109, and the output is connected to the control input of the key 85 of the pulse counter of block 5. The outputs of the first memory block of the PSU and the second memory block of the EPROM T`1 ... T`m are connected with information inputs of the electronic key 85 that are similar in name. block 5 (Fig. 11 and Fig. 12).

The command signal C16 coming from the output of the MRK module to the input of the OR element 108 is always equal to "1" when executing the main program and equal to "0" when executing the emergency program. In the latter case, when St = 0 at the outputs of the elements OR108 and I106, designated respectively d`` and d`, a signal d` = "0", d`` = 0 appears in block 2 and the operation of decoders 8, 9 and element I76 is blocked in block 7, as well as decoder 81 of the communication system, decoder 37 and all triggers except 47 in block 2 and the emergency subroutine is not executed. After passing all the clock cycles of the emergency program with C16 = 1, the device continues to operate. The use of the first PSU memory block, with a high impedance of resistance at the output, new elements and connections in the pulse counter of block 5, as well as elements of ILI108 and the sixth element I106 in block 2, allows to speed up the response of the device when an emergency occurs at the control object, which reduces the exit time from the emergency position. The inclusion of the second memory block EPROM with a high impedance of resistance at the output, allows you to reduce the number of clock cycles when calculating nonlinear algorithms and reduce the response time of the control system to changes in the control object to the maximum allowable delay. However, in this case, the program becomes more complicated due to the need to program the modes of "jumps" and the control and diagnostics of the device operation becomes more complicated, since the monitoring and diagnostic system should distinguish between emergency failures in the operation of the device from the normal "jump" mode, for example, when calculating nonlinear algorithms.

The presence in block 2 of the second counting trigger 47, the eighth element I116, the first element OR117 and the fifth element I46 allows you to write in the second counting trigger 47 a certain result of the analysis (calculation) of nonlinear algorithms in blocks 2 and 7, which is fed to its counting input, according to the corresponding commands, through the controlled element 16 of block 7 or from blocks 1, 3, BUP to block 2 and through the AND-OR elements 40, EXCLUSIVE OR 41, the ninth element I119 or from the output of the EXCLUSIVE OR 120 element, through element I46 and then through the elements OR 117 , I116 and which, in a single state, can switch the flip-flop 47 to the "0" state at its inverse output and block the operation of unit 7 and decoder 81 with a signal d` for a certain number of clock cycles until the arrival of signals C12 = 1 or C17 = 1 to the inputs of the OR117 elements or And 94. Similarly to the element I119, the element I46 is connected by inputs to the outputs of the EXCLUSIVE OR element 120 and the decoder 37, and the output is connected to the corresponding input of the AND element 117. The above process, when calculating nonlinear algorithms, allows you to make a choice between the execution of two subroutines, depending on the previously obtained calculation results and to branch the program by blocking the d` signal from the operation of all device blocks working with multi-bit data for all clock cycles of an unselected subroutine, at the same time, unit 2 can continue to work with single-bit variables with single outputs of the OR108 element and the introduced fourth trigger 137, connected, respectively, with the input of the decoder 37 and the inputs of the I42, I45, I122, I123 and I125 elements, which expands the functionality of the device. This method of calculating nonlinear algorithms increases the number of clock cycles in the implementation of nonlinear algorithms, but makes it possible to simplify the compilation of the program, since there is no need to program "jumps" and the process of diagnostics and control of the device operation is simplified, when any violation of the sequence of clock cycles is recorded as a failure in the operation of the device. The fifth element I115 in block 6 is connected by two inputs with the inverse output of the first counting trigger 62 and the output of the element HE68, and the output is connected to the inputs of the fifth element I21 and the eighth element I72 of block 7 and to certain inputs of the fourth and seventh elements I45 and I94 of the switching and computing unit 2, the I115 element allows you to supply the trigger reset pulses in the first quarter of the device operation cycles. As an MRK module, for example, a standard EPROM can be used, which converts the program code with the number of U1 ... Uk bits into the command code with a different C1 ... C33 bit depth.

The module for converting information MPI (Fig. 15) contains "n" memory modules MP1 ... MPn, each memory module has a counting flip-flop 130, an I131 element and an EXCLUSIVE OR133 element, and the first memory module also contains a second I132 element, and the outputs T` `1 ... T``n counting triggers 130 of all memory modules are connected to the information inputs of the third electronic switch 136, the outputs of which T1 ... Tn are connected to common buses 80 of the communication system, in each, except for the first, memory module the first and second inputs of the EXCLUSIVE OR element133 are connected, respectively, to the outputs of the counting triggers 130 of this memory module and the previous memory module, and in the first memory module, the second input of element 133 is the input of the MPI module and is connected to the output of the EXCLUSIVE OR element 41 of block 2, the inputs of the second element I132 of the first memory module are connected to a specific output decoder 8 of block 7 and with the output Z1 of the synchronization unit 6, and the output is connected to the reset inputs to "0" of the counting triggers 130 of all memory modules, in the strokes of the I131 element of all memory modules are connected to the corresponding output of the decoder 8 of the unit 7 and the d1 output of the synchronization unit 6, the control input of the third key 136 is connected to the output C31 of the MRK module. Before starting work, all triggers 130 are reset to "0" by a pulse from the output of element I132 of the first memory module MP1. The MPI module allows, when sequentially, in clock cycles, the supply of information bits to its input, at the outputs of the counting flip-flops 130 to obtain a parallel binary code. For example, the bits of information are sequentially received in clock cycles from the output i of the input block 1 and with the corresponding values of the commands C4, C5 and C6 through the AND-OR40 and EXCLUSIVE OR 41 elements are fed to the input of the MPI module and a parallel code T``1 is set at the outputs of the flip-flops 130 ... Т``n from "n" consecutively received bits, which, with the command С31 = 1, will go to the common buses 80 of the communication system Т1 ... Tn and can be used for further operations. The introduction into each logical channel of block 7 of the connection between the input of the AND-HE26 element and the output of the EXCLUSIVE OR100 element of the corresponding logical fragment from F1 ... Fn made it possible to reduce the number of clock cycles in sequential bitwise interdependent calculation of the OR, AND functions. Element I126 in circuit fragments F1 ... Fn allows you to block the signal at the output of element I15 of block 7 during the bitwise calculation of the functions AND, OR in block 7

The use in block 2 of the AND-HE44 element, connected with the output of the EXCLUSIVE OR120 element, expanded the functionality of the trigger 43 and simplified the process of calculating the logical functions in block 2.

The use of a counting trigger 47 and related elements in block 2 made it possible to significantly simplify the process of controlling program execution when implementing nonlinear algorithms, depending on the results of previous calculations, eliminating jump operations during program execution, i.e. writing and reading out-of-order binary codes from memory elements and installing them into a multi-bit counter of a program unit when moving from one subroutine to another, while retaining the possibility of implementing nonlinear algorithms without changing the continuous sequence of reading program codes, which makes it possible to simplify control over the operation of the device and compilation of a program when calculating nonlinear algorithms.

In order to ensure independent operation with single-bit binary variables in block 2 and multi-bit binary variables in block 7, when implementing nonlinear algorithms in them, the fourth trigger 137 is introduced into block 2, elements: the fourth OR141, the fourteenth I144, the fifteenth I143 and the sixteenth I142. In this case, the trigger 137 by the output S is connected to the blocking input of the decoder 37 and to the inputs of the elements: I42, I45, I122, I123, I125, the trigger 137 by the reset input to zero is connected to the output of the I144 element, the inputs of which are connected to the output Z of the synchronization unit 6 and the output C32 of the MRK module, the counting input of the trigger 137 is connected to the output of the I143 element, connected by the inputs to the dl output of the synchronization unit 6 and the output of the OR141 element, the inputs of the latter are connected to the C34 output of the MRK module and to the output of the I142 element, whose inputs are connected to the C35 output of the MRK module and with the output of the EXCLUSIVE OR120 element of block 2. The operation of the trigger 137 is similar to the operation of the trigger 47 in the block 2. At the beginning, the trigger 137 by the command C32 = 1 is set to a single state. If it is necessary to block a part of the program being executed, depending on the value of the previous calculation, i.e. from the value of the signal at the output of element 120 of block 2 and with C35 = 1 logical 1 through the elements OR141 and I143 will throw the trigger to "0" and the operation of block 2 will be blocked for a certain number of clock cycles, and then with C34 = 1 trigger 137 will change its state and operation block 2 will continue. In the case of the implementation of nonlinear algorithms without a jump, it is easier to organize control of the device's operation, when a jump in the program is recorded as a failure in the operation of the device and it is easier to draw up a program for its operation, because no need to program the jump process. The implementation of the calculation of similar nonlinear algorithms using a jump, when executing a program, allows you to reduce the number of clock cycles and increase the speed, if necessary according to the technological requirements in the operation of the control object, but this complicates the process of control and programming. A selection appears when creating a program.

Below is an example of a partial accelerated transfer by the BUK block, taking into account the function (1A) for six bits, the first group of three bits has a parallel transfer and the second group of three bits also has a parallel transfer, and a sequential transfer occurs between these groups. From function (1A) it follows:

the transfer formula for the first group of three digits is:

the transfer formula for the second group of three digits is:

The meanings of numbers, letters and signs in functions (1B), (1C) and (1A) are the same. The technical and economic effect of using the proposed device, in comparison with the analogue and the prototype, is to increase the speed when calculating nonlinear algorithms, depending on the results of previous calculations and the ability to choose one of two ways to implement nonlinear algorithms, namely "jump" or continuous program execution , each of which has its own advantages and disadvantages, i.e. effectively adapt, in accordance with the operating conditions of the control object, as well as in expanding the functionality by calculating nonlinear algorithms in the switching computing unit that processes one-bit variables, regardless of the similar process in a multichannel operating unit that implements functions with multi-bit variables.

1. RF patent for invention No. 2616153, Bul. 11 for 2017 (analogue)

2. RF patent for invention №2685985, Bul. # 12 2019 (prototype)

Claims (7)

A device for building programmable digital microprocessor systems, containing an input unit that receives signals from sensors and generates a certain code at its output, an output unit for recording the values of codes coming from all logical channels of a multichannel operating unit and from a switching computing unit to the corresponding cells memory and transferring them through digital-to-analog converters to electronic devices, electric drive mechanisms and signaling, a program unit, an MRK command distribution module connected by inputs to certain outputs of the program unit, and outputs to the inputs of the corresponding units and modules, a random access memory unit, a synchronization and switching unit - a computing unit consisting of AND-OR elements, EXCLUSIVE OR elements, AND elements, counting triggers, a decoder, while the corresponding decoder inputs are connected to three specific outputs of the MRK module, the first inputs of the first two AND of the AND-OR element are connected to the third and fourth outputs of the decoder, and the second inputs are connected to the output of the input unit, connected by the first and second groups of inputs to the group of information outputs of the control object and to the group of address outputs of the program unit, as well as to the output of the RAM block, the output of the AND-OR element is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to a specific output of the MRK module, the output of the EXCLUSIVE OR element is connected to the first input of the third AND element connected by the second input to the output of the synchronization unit, the first input of the fourth AND element is connected to the corresponding output of the MRK module, the second the input is connected to the output of the synchronization unit, and the output is connected to the input of the setting to "0" of the counting trigger, the inputs of the second EXCLUSIVE OR element are connected to the output of the counting trigger and to one of the outputs of the MRK module, and the output is connected to the information inputs of the output block and the RAM block , the first inputs of the first and second elements AND are connected to the first and second outputs of the decoder, their second inputs are combined and connected to the corresponding output of the synchronization unit, and the outputs are connected to the corresponding inputs of the output unit and the RAM block to control the recording of information, a multichannel operating unit containing a controlled element, the second and from the fourth to the twelfth elements And, the first, from the third to the sixth and the eighth OR elements, the first and second decoders that control the operation of the logical elements of the device, a controlled memory cell, a controlled trigger, an electronic switch, an OR-NOT element, an element and the first EXCLUSIVE OR element and "n" in parallel operating logical channels having a similar structure and each of which contains an EXCLUSIVE OR element, three AND elements, an OR element, two counting flip-flops, bit shift modules, while in each logical channel of a multichannel operating unit, the output of the EXCLUSIVE OR logic element is connected to the first input of the element OR, second input to is connected to the output of the second AND element, the output of the OR element and the corresponding output of the synchronization unit are connected to the corresponding inputs of the third AND element, the output of the latter is connected to the counting input of the first counting trigger, the output of which is connected to the counting input of the second counting trigger, while in a multichannel operating unit the output of the first OR element is connected to the second inputs of the EXCLUSIVE OR elements of logical channels, the first and second inputs of the first OR element are connected, respectively, to the outputs of the second decoder and the seventh AND element, the first and second inputs of the second AND element are connected to one of the outputs of the synchronization unit and to a specific output the first decoder, and the output is connected to the control input of the controlled trigger, the output of the OR-NOT element is connected to the third input of the LM logic module, the inputs of the OR-NOT element are connected to the output of the tenth AND element, to the output of the first decoder and to the output of the third OR element, the inputs of which connected to outputs od of the eleventh and twelfth elements AND, the first inputs of the last elements are connected to certain outputs of the MRK module, and the second inputs are connected to the outputs of the first counting triggers of the first and last channels of the multichannel operating unit, the first input of the seventh element AND is connected to the corresponding output of the second decoder, and the second inputs of the sixth and the seventh AND elements are connected, respectively, with the direct and inverse outputs of the controlled memory cell, the information input of which is connected to the output of the OR element of the discrete module DM, containing the first and second AND elements, the NOT element, the OR element and the third logical element AND, and the inputs of the third logic element And they are connected to the outputs of the first counting triggers of the penultimate and last channels, the inputs of the second AND element are connected to the output of the third AND element and to the corresponding output of the MRK module, which is also connected to the input of the NOT element, the output of the latter is connected to the input of the first AND element, the other input of which is connected from one of the outputs of the BUP block, and the output is connected to the corresponding input of the OR element, the second input of which is connected to the output of the second AND element, in the multichannel operating unit the control input of the controlled memory cell is connected to the output of the fourth AND element, the information input of the controlled trigger is connected to the direct output of the controlled memory cells, the inverse output of the controlled trigger is connected through one of the common buses of the communication system to the output unit, three control inputs of the controlled element are connected to certain three outputs of the MRK module, one of which is also connected to the second input of the first EXCLUSIVE OR element, and the other to the first the input of the fifth OR element, the output of the latter is connected to the first input of the ninth AND element, in the device, in the switching computing unit that calculates logical functions containing one-bit input logical variables that come through the corresponding logical elements to the counting input of the counting trigger, the first inputs of the third and the fourth AND elements included in the AND-OR element are connected to the corresponding two outputs of the decoder, and the second inputs are connected to the output of the controlled element of the multichannel operating unit and to the output of the discrete module DM, the inputs of the first and second decoders in the multichannel operating unit are connected to the corresponding outputs of the MRK module , certain outputs of the transfer control unit PCU, providing arithmetic operations of addition and subtraction, are connected to the corresponding inputs of the second elements AND of all logical channels except the first, the second input of the second element AND of the first logical channel is connected together with the corresponding input of the PCU block to the output of the first EXCLUSIVE OR multi-channel operating unit, where the corresponding output of the first decoder is connected to the second input of the ninth AND gate, the inputs of the eighth AND gate are connected to the outputs of the synchronization block and the sixth OR gate, and the output is connected to the first input of the fourth OR gate, the output of which th is connected to the reset inputs to "0" of the second counting triggers of all logical channels, the inputs of the fifth AND element are connected to a specific output of the MRK module and the corresponding output of the synchronization block, and the output is connected to the second input of the fourth OR element and to the reset inputs to "0" of the first counting triggers of all logical channels, the logical module LM whose structure and its functioning are determined by the logical functions С`` = (С24 + С22) • d` • t1, С` = С24 • d` • t1,

, C ⁰ = C22 • C24 • d` • t1, where C24, C22 are the inputs of the logic module LM and are connected to the corresponding outputs of the MRK module, t1 comes from the output of the OR-NOT element of the multichannel operating unit, d` is connected to the output of the sixth AND element the switching and computing unit, and C`, C``, C <sup>0</sup> , C``, the outputs of the logic module LM and are connected by the output C``, with the first input of the sixth element OR of the multichannel operating unit, other outputs - the module LM is connected to the corresponding inputs bit shift modules MCP1, MCP2 and MCP3 in the corresponding logical channels, and the bit shift module MCP1 is located in all logical channels, except for the first and the last and implements the logical functions Y`1 = (b` ⊕b``) • C``, Y `2 = (b`⊕b``) • С`, where У`1 and У`2 are the outputs of the MCP1 module and are connected to the corresponding inputs of the OR element of this and subsequent logical channels, the variables b`, b``, С` , С,, are input signals for MCP1, and b`, b``, come from the outputs of the first counting flip-flops The ditch of this and subsequent logical channels, C` and C,, come from the outputs of the logical module LM, the MCP2 module in the first logical channel implements logical functions

, У2 = (b1⊕ b2) • С`` and У3 = (b1⊕ b2) • С`, where У1, У2 and У3 serve as the outputs of the MCP2 module and are connected, respectively, with the third and fourth inputs of the OR element of the first logical channel, and with the third input of the OR element of the second logical channel, b1, b2, bn, C`, C``, C ⁰ are the inputs of the MCP2 module and are connected, respectively, with the outputs of the first counting flip-flops of the first, second and last logical channels and with three outputs of the LM logical module , the MCP3 module calculates the logical function

, where signal U1,,, comes from the output of the MCP3 module to a certain input of the OR element of the last logical channel, signals b1, bn, C,,, C15 are fed to the inputs of the MCP3 module, respectively, from the outputs of the first counting triggers of the first and last logical channel, from the output of the LM logic module and from a certain output of the MRK module, and

there is an inversion C15, in a multichannel operating unit, where the first input of the fourth AND element is connected to a specific output of the MRK module, the second input is connected to the corresponding output of the synchronization unit, and the third input is connected to the output of the OR-NOT element, the control input of the electronic switch is connected to the corresponding output the first decoder, the output of the ninth AND element is connected to the first inputs of the first AND elements in each logical channel, the second inputs of the first AND elements of each logical channel, together with the information outputs of the electronic switch of the multichannel operating unit, are connected to the common buses of the communication system T1 ... Tn, and the outputs of the first elements AND in each logical channel are connected to the first inputs of the EXCLUSIVE OR elements, common buses T1 ... Tn are also connected to certain outputs of the first and second keys of the communication system and to the corresponding inputs of the RAM unit and the output unit, and the inputs of the first and second keys are connected to certain outputs input th block and a block of random access memory, the control inputs of the first and second keys, the block of random access memory and the output block are connected to the corresponding outputs of the decoder of the communication system, the inputs of which are connected to certain outputs of the program block, in the multichannel operating unit, the eighth element OR is connected by the first and second inputs with the second and third outputs of the second decoder, and the output is connected to the first input of the sixth AND element, the inputs of the EXCLUSIVE OR element are connected to a specific output of the MRK module and to the first T1 bus from among the common buses of the communication system, and the output is connected to the second input of the fifth OR element, in the multichannel operating unit there are "n" identical circuit fragments F1 ... Fn according to the number of logical channels, each circuit fragment is associated with the corresponding logical channel and contains two logical elements OR and EXCLUSIVE OR, and the second and third inputs of the OR gate are connected to the output of the second AND gate corresponding logical channel and with the corresponding the output of the MRK command distribution module available in the device, and the output is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to the output of the first counting trigger of the corresponding logical channel, and the outputs of the EXCLUSIVE OR elements, which are the outputs of the corresponding circuit fragments, are connected to the information inputs of the electronic switch and a controlled element of a multichannel operating unit, where the first input of the first EXCLUSIVE OR element is connected to the output of the sixth AND element, in the switching-computing unit the first OR element connected by three inputs to the output of the MRK module, to the output of the fifth AND element and to the output of the ninth AND element, and the output with the first input of the eighth AND element, the inputs of the ninth AND element are connected, respectively, to the output of the EXCLUSIVE OR element and to a specific output of the MRK module, the counting input of the second counting trigger is connected to the output of the eighth AND element, the OR element is connected by inputs to a specific output of the MRK module and with the bus St of the alarm transmission, and the output is connected to the blocking input of the decoder of the switching and computing unit and to the inputs of the third, fourth, sixth, tenth and eleventh elements And, the other input of the sixth element And is connected to the inverse output of the second counting trigger, and the output is connected with the blocking inputs of the first and second decoders and the corresponding inputs of the fourth, fifth and tenth elements AND of the multichannel operating unit, as well as with the blocking input of the decoder of the communication system and with a specific input of the third element AND of each logical channel, the inputs of the seventh element AND are connected to the corresponding outputs the synchronization unit and the MRK module, and the output is connected to the reset input to "0" of the second counting trigger, two inputs of the fifth element AND are connected to the output of the decoder and to the output of the second EXCLUSIVE OR element, the second input of the eighth element AND is connected to the corresponding output of the synchronization block, the output element AND NOT link and with the third input of the third AND element, the first input of the AND-NOT element is connected to the corresponding output of the MRK module, the second input of the tenth AND element in the multichannel operating unit is connected to the corresponding output of the MRK module, and the output is connected to another input of the sixth OR element and to a specific input the second AND element of all logical channels, each of them has a AND-NOT logic element, its first input is connected to the corresponding output of the MRK module, and the output is connected to a specific input of the third AND element of the corresponding channel of the multichannel operating unit, the fast transfer unit of the PCU has the structure, defined by the following logical functions:

M1 is the signal from the output of the first EXCLUSIVE OR element of the multichannel operating unit, which is fed to the corresponding input of the BUP unit; M2 ... Mn - transfer signals coming from the outputs of the BUP block to the inputs of the second elements AND of all logical channels, except for the first; Mn + 1 - transfer signal coming from the output of the BUP unit to the input of the discrete module DM; В1 ... Bn - signals from the outputs of the first counting flip-flops of all logical channels, arriving at the corresponding inputs of the BUP block; P1 ... Pn - transfer signals coming from the outputs of the second counting triggers of all logical channels to certain inputs of the BUP block, the information conversion module MPI containing "n" memory modules MP1 ... MPn according to the number of common buses T1 ... Tn in the communication system, each memory module includes a counting trigger, an AND logical element and an EXCLUSIVE OR logical element, and the first memory module MP1 additionally includes a second AND element, and for all memory modules, the reset input to "0" of counting triggers is connected to the output of the second AND element of the first memory module, the inputs of the second element And they are connected to certain outputs of the first decoder of the multichannel operating unit and the synchronization unit, in each memory module the counting input of the counting flip-flop is connected to the output of the AND element, three inputs of which are connected to the output of the first decoder of the multichannel operating unit, to a specific output of the synchronization unit and to the output of the EXCLUSIVE element OR, the first and second inputs of the latter are linked for all modules memory, except for the first one, respectively, with the outputs of the counting triggers of this and the previous memory modules, and for the first memory module with the output of the counting trigger of this memory module and with the output of the EXCLUSIVE OR element of the commutation-computing unit, the third electronic key connected by information inputs to the outputs of the counting triggers of all memory modules, the control input is connected to the corresponding output of the MRK module, and the outputs are connected to the common buses T1 ... Tn of the communication system, in the multichannel operating unit in each logical channel a connection is introduced between the second input of the NAND element and the output of the EXCLUSIVE OR element of the corresponding circuit fragment from F1 ... Fn, in each of which there is an AND element connected with its inputs to the output of the first OR element of the multichannel operating unit and to the output of the MRK module, and the output is connected to the first input of the OR element, in the switching and computing unit the output of the second EXCLUSIVE OR element is connected to inputs of the element NAND, eleven th element AND and element NOT, the output of which is connected to the input of the tenth element AND, three other inputs of the tenth element AND are connected to the outputs of the MRK module, the synchronization block and to the direct output of the third trigger, the other three inputs of the eleventh element And are connected to the inverse output of the third trigger, with the outputs of the MRK module and the synchronization unit, the output of the tenth AND element is connected to the first input of the third OR element, the output of the eleventh AND element is connected to the input of the setting in "1" of the third trigger, the inverse output of which is connected to the input of the third AND element, four inputs of the twelfth AND element connected to the direct output of the third trigger, with certain outputs of the MRK module, the synchronization block and the OR element, and the output is connected to the first input of the second OR element, the second input of which is connected to the output of the third AND element, and the output is connected to the counting input of the counting trigger, the reset input in "0" of the third trigger is connected to the output of the third OR element, the second input of which is connected to the outputs ode of the fourth AND element, the input of the second element is NOT connected to the output of the MRK module, and the output is connected to the input of the third AND element, characterized in that the first and second memory blocks of the PSU and EPROM with new connections are introduced, and the information outputs are the first and second memory blocks of the PSU and EPROM are connected to the information input of the electronic key of the pulse counter of the program unit, and binary codes from the outputs of the counting triggers of the pulse counter of the program unit are fed to the address inputs of the second memory unit of the PROM, the alarm signal St is sent to the input of permission to read from the outputs of the first memory unit. the second memory block of the EPROM, the input for enabling the reading of information is connected to the output of the element AND whose inputs are connected to the corresponding output of the MRK module and to the output of the element NOT of the pulse counter, into which the elements OR, the first and second AND elements are still introduced, and the input of the element is NOT associated with the alarm signal Art, and the output is also connected to the input of the second element AND, the other inputs of which are connected to the corresponding outputs of the MRK module, the synchronization unit and the sixth AND element of the switching-computing unit, the output of the second AND element is connected to the second input of the OR element of the pulse counter of the program unit, and the first input of the OR element is connected to the output of the first AND element connected by the inputs to the emergency signal St and with a certain output of the synchronization unit, the output of the OR element is connected in the pulse counter to the control input of the electronic key, the fourth trigger is introduced into the switching-computing unit, the reset input is at "0", connected with the output of the fourteenth AND element connected by inputs to the output of the module MRK and to the output of the synchronization unit, and the fourth flip-flop is connected by the counting input to the output of the fifteenth AND element, the inputs connected to the output of the synchronization block and to the output of the fourth OR element, connected by inputs to the output of the MRK module and to the output of the sixteenth AND element, which is connected by inputs to the output module MRK and with the output of the second element EXCLUSIVE OR switching computing unit, and the output of the fourth trigger is connected to the first blocking input of the decoder and to the inputs of the third, fourth, tenth, eleventh and twelfth elements of I.

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