SU1101821A1 - Module for integrating computing network - Google Patents

Abstract

1. INTEGRATING COMPUTING STRUCTURE MODULE containing a switch and a digital integrator, with the initialization output, the initial data output group of the integrand function, and the output pulse of the initial data of the integral function of the switch are connected to the initial installation input, respectively, with the input group The initial data HbFX and the resolution input record the initial data of the digital integrator, and the first input, the group of inputs and the second input of the switch are connected respectively to the module select input, with the module initial data bus and the module reset input, characterized in that, in order to expand the field of application by solving more complex systems of urgency, it additionally contains the module address register, a group of 3 input increment address registers (where input increments of the digital integrator), address comparison module. module, a group of 3 blocks of input increment comparison, a group of L positive increment triggers, a group of 3 negative increment triggers, a group of 3 input electrons entog. Positive increments, a group of 3 input elements AND, negative increments, output elements AND positive and negative increments, a clock counter, an OR element, an incomplete decoder and a pulse width former, the output of the initial state, 1 - (1, 2, 3, ... L) the group of information outputs and the output of the -th pulse from the group of outputs of the pulses accompanying the initial data of the switch are connected respectively to the input of the zero setting, the group of information inputs and the recording resolution input of the 1st the register of the address of the input increments of the group, and the output of the setup to the initial state, (L - | -1) - the group of information outputs and the output

Description

the output is connected to the first input of the output element And positive increments and to the first input of the output element And negative increments, the second inputs of which are connected respectively to the outputs of the positive and negative increments of the integral of the digital integrator, and the outputs from the outputs of the positive and negative processor increments, respectively, a single output of each bit Yes, the register of the address of the input increments of the group is associated with the first group of inputs of the -th block of the comparison of the addresses of the input increments of the group, torus, the group of inputs of which is connected to the group of single outputs of the clock counter, and the output of the i-th block of the comparison of addresses of the input increments of the group is connected to the first input of the -th input element of the positive group increments and the first input of the a-th input element of the negative group increments, second the inputs of which are connected respectively to the input of positive increments of the module and to the input of negative increments of the module, and the outputs are connected respectively to a single input of the 1st trigger of positive increments and to one By the initial input of the 1st trigger of the negative increments of the group, the unit outputs of which are connected respectively to the i-th inputs from the input groups of the positive and negative values of the input increments of the digital integrator, the group of inputs of the incomplete decoder is connected to the group of single outputs of the clock counter, state outputs (N + 1) (where N is the number of modules in the integrated computing structure), states (N + gp-1) and states (N + m + 1) of the incomplete decoder (where In is the number of bits in the register of the integrand function of the digital in tegrator) are connected respectively with the first one, the second and the third inputs of the clock group

1821

JBXo; tOB shaper YNMynbcoB of performance, zero input of each trigger of positive group increments and each trigger of negative group increments connected to the output of the OR element, the second input of which is connected to the output of the incomplete decoder state (t + tri + 1) and a signal with the duration (# -2) of the pulse duration pulse generator and the output (}, 1 + P1 + 1) of the incomplete decoder are connected to the input of the calculation resolution signal, respectively, to the input of the integral residue extraction signal and the input signal of the iteration end of the digital integrator, the counting input of the clock counter is connected to the input of the module module resolution, and the output state (K + m + 1) of the incomplete decoder is also connected to the output of the module clock control.

2. The module according to claim 1, characterized by the fact that the pulse width driver contains two OR elements and two flip-flops, the output of the first OR element and the output of the second OR element are respectively connected with the zero input of the first flip-flop and the zero input of the second flip-flop , the first inputs of the first OR element and the second OR element are connected to the reset input of the imager, the first input from the group of clock inputs of the forerunner is connected to the single inputs of the first and second triggers, the unit codes of which are connected respectively to the output of the signal with duration of m cycles and with the output of signal with duration (t-2) of the clock of the generator, the second inputs of the second OR element and the first element OR are connected respectively to the second and third inputs from the group of clock inputs of the generator, the first input from the group of clock inputs of the generator is connected single inputs of the first and second triggers.

The invention relates to computing and is intended for

uses in integrative xlicelite structures (ITT).  Digital integrators are known that contain registers and adders of the integrand function, registers and adders of the remainder of the integral, nodes of intelligence, nodes of increments and intended for use in willows l and 2.  The main disadvantage of these digital integrators is that they cannot perform the function of a programmable switch, as a result of which it is impossible to build economic basis for large computing power, while ICS of similar power built on the basis of these digital integrators - due to the high costs of equipment for their switching, it is very uneconomical and even not always practically real: uyems.  The closest in technical essence to the invention is an ICS processor with one-bit increments, comprising a switch, a setup register, an input switches node, an output switches node, and a digital integrator that includes the register and adder of the integrand function, the register and the residual accumulator I1 {the multiplication node, output increment allocation node, first and second scaling nodes, with the first and second switches of the switch being connected respectively to the input of the setup register and the input of the first scale node Rovani digital integrator. and the switch inputs are connected to the processor selection bus, the initial data bus and the reset bus, the setup register outputs are connected to the input switch node input and the first switch output node input, the second input of which is connected to the output output node of the digital integrator, the input group of the input switch node is connected to four input increment buses, and the outputs are connected respectively to the inputs of the second scaling node and the multiplicator node of the digital integrator, group input s of the output switch node is connected to four input increment buses, and a group of outputs with four output increment buses, the output of the second digital integrator scaling node is connected to the first adder input of the integrator function of the digital integrator, the second input of which is connected to the register output of the integrator and digital integrator, and the output of the adder of the integrand function of the digital integrator is connected to the first inputs of the register of the integrand function and the multiplication unit of the digital integrato a, the output of the multiplicator node of the digital integrator is connected to the first input of the adder of the remainder of the integral of the digital integrator, the output of which is connected to the input of the allocation node of the output increments of the digital integrator directly and through the register of the remainder of the integral of the digital integrator, the first and second outputs of the first scaling node the digital integrator is connected respectively to the inputs of the second scaling node and the register of the integrator of the digital integrator.  The well-known processor of ICS, along with the implementation of the main task - numerical integration, can simultaneously perform tasks of a programmable switch, which allows it to create cost-effective flat willows with a large computational power sj.  The main disadvantage of the known ICT processor is the limited switching capacity, since the capped processor can only connect with four neighboring processors and can be used as a switch as the increment switch of these four neighboring processors, which does not provide the universality of switching.  Expanding the switching capabilities of a well-known ICT processor is hindered by the dramatically increasing costs of equipment and an increase in the number of external links, which makes it impossible in this case to create a large computing power based on the ICS.  At the same time, the limited switching capabilities of a known ICS processor make it difficult to program the task and require considerable time to prepare the task for the solution on this ICS, as well as the difficulty of drawing up a block diagram of the task, t. e.  the complexity of the task in the ITT, due to the limited connections, there can be dead ends (lack of connections).  t. e.  when a task is not invested in a willow, built on the basis of a known processor.  The aim of the invention is to expand the field of application by solving more complex systems of equal) 1st.  This goal is achieved by the fact that in the liBC module containing a switch and a digital integrator, the output of the resetting group is the output data group of the integrand function and the pulse output. The maintenance of the initial data of the integral function of the switch is connected respectively to the installation input to the source state 5 with a group of inputs of the initial data and the input enable recording of the initial data of the digital integrator, and the first input, a group of inputs and the second input of the switch are connected to the input of the module selection, with the initial data bus and a module reset input, enter the module address register, a group of j input address increment registers (where J is the number of input increments of the digital integrator), module address comparison unit, gr Upp of 3 blocks of comparison of addresses of input increments, a group of J triggers of golottelnyh increments, a group of J triggers of negative increments, a group of J input elements And positive increments, a group of 3 input elements And negative increments, output elements And positive and negative increments, clock counter, OR element, incomplete decoder and pulse width former, with the output setting of the initial state, 1 - the group of information outputs and the output of the 1st pulse from the group of outputs The impulses accompanying the initial data of the switch are connected respectively to the installation input zero, the group of information inputs and the input resolution of the entry of the -th register of the address of the input group increments (i 1, 2,.  .  . 1), and the output of the installation to the initial state, (T + 1) - the group of information outputs and the output of the (3 + 1) -th pulse from the group of outputs of the pulses followed by the initial data of the switch are connected respectively to the input of the zero setting, from the information inputs and the enable input of the register of the module address register, in addition, the output of the initialization of the switch is connected to the set input of the zero clock counter, the reset input of the pulse width generator and the input of the OR element, the unit output of each bit of the address register The module is connected to the first group of inputs of the module of the block of addresses of the module, the second group of inputs of which is connected to the group of single outputs of the clock counter, and the output to the first input of the output element And positive increments and to the first input of the output element And negative increments, the second inputs of which are connected respectively with outputs of positive and negative increments of the integral of the digital integrator, and outputs with outputs of positive and negative processor increments, respectively, a single output The third register of the input increments of the group is connected to the first group of inputs of the 1st block of the group of input address increments, the second group of inputs of which is connected to the group of single outputs of the clock counter, and the output of the i-th block of the addresses of the input group of increments of the group with the first input of the input element And the positelnik Hf. ix group increments and the first input of the 1st input element And negative group increments, the second inputs of which are connected respectively to the input of positive module increments and the input of negative module increments, and the outputs respectively to the single input of the 1st group positive increment and single the input of the t-th trigger of negative increments of a group, the unit outputs of which are connected respectively to the 1st inputs of 1 groups of inputs of positive and negative values of the input increments of the digital input a tegrator, a group of inputs of an incomplete decoder — with a group of single outputs of a clock counter, outputs of a state (J + 1) (where N is the number of modules in the ICS), a state (Nt-rrrO, and a state (+ 1) of an incomplete day (where rrnumber: rasters in the integrator digital integrator function register) are connected respectively to the first, second and third inputs of the group of clock inputs of the pulse shaper, the zero input of each trigger of the positive group increments and each trigger of the negative group increments are connected to the output of the OR element, the second input of which is connected to the output of the state (N + in + 1) of the incomplete decoder, the outputs of the signal with duration of m ticks and the signal with duration (t-2) of taps of the pulse width former and output of the state (N-HT1 + 1) incomplete decoder is connected respectively to the input of the enable signal of the calculations, to the input signal of the residual integral and to the input signal of the iteration end of the digital integrator, the counting input of the clock counter is connected to the enable input of the module, and the output of the (N + rn + 1) incomplete decryptor The ra is also connected to the output of the module clock control.  In addition, the pulse shaper contains two OR or two flip-flops, the output of the first OR element and the output of the second OR element are respectively connected to the zero input of the first trigger and the zero input of the second trigger, the first inputs of the first OR element and the second OR element are connected to the reset input of the imaging unit is the first input from the group of clock inputs of the imaging unit connected to the single inputs of the first and second triggers, the unit outputs of which are connected respectively to the output of the signal; SPU clock cycles and with the output of the signal duration (t-2) clock of the driver, and the second inputs of the second element OR and the first element OR are connected respectively with the second and third inputs of the group of clock inputs of the generator, the first input of the group of clock inputs of the generator is connected to single inputs of the first and second triggers.  FIG.  Figure 1 shows the block diagram of the ITT module; in fig.  2 - an example of the implementation of a digital integrator; FIG. 3 is a diagram of the implementation of switch i in FIG.  4 is a diagram of the implementation of the recording device; FIG. 5 diagram of the implementation of the digital integrator scaling node; in fig.  6 shows the implementation scheme of the input node of the digital integrator} in FIG.  7 is a diagram of the implementation of the node of the output increments of the digital integrator,, in FIG.  8 is an example of combining modules in IHD.  The module RGVS, shown in FIG.  1, contains switch 1, digital integrator 2, module address register 3, input increment address register 4, 5 clock counter, pulse width generator 6, module address comparison block 7, blocks 8 of the input increment address comparison, output element And 9 positive increments , output element And 10 negative increments, input elements And 11 positive increments, input elements And 12 negative increments, triggers 13 positive increments, triggers 14 negative increments, element OR 15, incomplete decoder sixteen.  The number 17 denotes the module selection input, the number 18 represents the initial data bus, the number 19 denotes the reset bus, the number 20 denotes the input of the module module enable.  Numbers 21 and 22 denote the input of positive increments of the module and the input are negative}}, the increments of the module, 23 and 24, respectively, the output of positive increments of the module and the output of negative increments of the module, and 25, the output of the control of the module ticks.  The integrator 2 shown in FIG.  2, a scaling node 26 is entered, an input node 27, an adder 28 of an integrand function, a first delay element 29, a multiplication node 30, a register 31 of an integrand function, an integral residue adder 32, a second delay element 33, an output increment node 34 integral.  The numbers 36 and 37 denote the first and second inputs of the digital integrator, respectively, the number 38 of the inputs of the digital integrator, the number 39 denotes the output of the digital integrator. The switch 1 of the ICS module presented in FIG.  3, includes the first element AND 40, the element OR 41 ,.  The delay element 42, the counter 43, the second element And 44, the decoder 45, the rupp of elements And 46, the group of elements And 47.  The numbers 48-50 designate the first, second, and retium inputs of switch 1, respectively, and the numbers 51 and 52 denote the first and second outputs of the switch, respectively.  The pulse shaper modulator 6, presented in FIG.  4, includes the first evil OR 53, the second element OR 54, the first trigger 55, the second trigger 56.  The number 57 denotes the input of the formatter, the numbers 58 denotes the group of inputs of this former, the numeral 59 denotes the output of the former.  The composition of the scaling unit 26 of the digital integrator 2 shown in FIG.  5, the element OR the trigger 61 enters, the first element AND 62, the first delay element 63, the second element AND 64, the second delay element 65, the third element AND 66, the third delay element 67, the fourth element AND 68.  Numbers 69-71 denote the first, second and third inputs of the scaling unit 26, respectively, and 72, the output of the node.  The input node 27 of the digital integrator 2 shown in FIG.  6, the first combinational adder 73, the first element AND 74 the second element I75, the third element AND 76, the first element OR 77, the second combinational adder 78, the fourth element And 79, the fifth element And 80, the sixth element And 81, the second element OR 82, element NO 83, seventh element AND 84, trigger 85, eighth element AND 86, third element OR 87, first delay element 88, third combiner adder 89, second delay element 90 Numeric 91 is the input of input node 27, numeral 92 is group of inputs of this node, the number 93 - the output of the input node 27.  The unit 34 for allocating output increments of the digital integrator 2 shown in FIG.  7, the first element AND 94, the first delay element 95, the second element 9 enter. 6 delay, the second element I. 97, the first element is NOT 98, the third element is AND 9 the first element is OR 100, the first is trigger 101, the fourth element is AND 102, the second element is NOT 103, the fifth element is AND 104, the second element is OR 105. , the second trigger 106, the sixth element And 107, the seventh element And 108.  Numbers 109-111 denote the first, the second and the third inputs of the output increment 34, respectively, and the number 112, the output of the output increment allocation 34.  The first output of the switch 1 is connected to the first input of the digital integrator 2, and the second output to the input of the register 3 module addresses, with the input of each register 4 addresses of the input increments, to the first input of the counter 5 cycles and to the input of the imager 6.  The output of each register register 3 address of the processor is connected to the first group of inputs of the block 7 comparison of addresses of processors, the second - a group of inputs of which is connected to the group of outputs of the counter 5 cycles.  The output of each bit of each register 4 addresses of input increments is connected to the first group of inputs of the corresponding block 8 comparing the addresses | - of the input increments, the second group of inputs of each of which is connected to the group of outputs of the counter 5 cycles.  The output of block 7 of the module address comparison is connected to the first input of the output element AND 9 positive increments and to the first input BE) of the INPUT element AND 10 negative increments, the second inputs of which are connected to the output of the digital integrator 2.  The output of each block 8 of the input increment address comparison is connected to the first input of the corresponding input element AND 11 positive increments and to the first input of the corresponding input element AND 12 negative increments, the outputs of which are connected respectively to the single inputs of the corresponding trigger 13 positive trigger 14 and the corresponding trigger 14 negative increments, the unit outputs of which are connected to the corresponding input from the group of inputs of the digital integrator 2.  The zero input of each trigger 13 positive increments and each trigger 14 negative increments are connected to the output of the RSHI element 15, the first and second inputs of which are connected respectively to the second output of the switch 1 and to the output of the partial decoder 16, the input group of which is connected to the output group of the counter 5 cycles, and the group of outputs with the group of inputs of the driver 6.  The second input of the digital integrator 2 is connected to the output of formate 11 and to the output of the incomplete decoder 16.  The first, second and third inputs of the switch 1 are connected respectively to the input 17 of the processor selection, to the initial data bus 18 and to the reset bus 19.  The second input of the 5 clock counter is connected to the processor resolution resolution input 20.  The second input of each input element And 11 positive increments and the second input of each input element And 12 negative increments are connected respectively to the input 21 positive increments of the module and to the input 22 negative increments of the module.  The output of the output element And 9 positive increments and the output of the output element And 10 negative. increments are connected respectively with the output of 23 positive increments of the module and with the output of 24 negative increments of the module.  The output of the incomplete decoder 16 is also connected to the output 25 of the control module clock.  The output of scaling node 26 is connected to the input of input node 27, the output of which is connected to the first input of adder 28 of the integrand, the first output of which is connected through the first delay element 29 to the second input of the adder 28 of the integrand, and the second output to the input of multiplication node 30 and with the input of the register 31 of the integrand function, the output of which is connected to the third input of the adder 28 of the integrand and with the input of the scaling node 26.  The output of the multiplication node 30 is connected to the first input of the adder 32 of the integral, the first output of which is connected through the second element 33 to the second input of the adder 32 of the integral residue, and the second output to the input of the output increment 34 and the input of the integral residue register 35, output which is connected to the third input of the adder 32 of the remainder of the integral.  The second input of the scaling unit 26, the second input of the register 31 of the integrand function, the second input of the node 3 in the output increments and the second input of the register 35 of the integral balance 112 are connected to the first input 36 of the digital integrator 2i The third input of the scaling node 26, the second input of the node 30 multiplying, the third input of the register 31 of the integrand, the third input of the output increment node 34 and the third input of the integral remainder register 35 are connected to the second input 37 of the digital integrator 2.  The third input of the multiplication unit 30 is connected to one of the inputs of a group of inputs 38 of digital integrator 2, and the remaining inputs of this group of inputs 38 of a digital integrator are the 2nd group of inputs of the input node 27.  The output of the node 34 in the output increments is connected to the output 39 of the digital integrator 2.  The output of the first element And 40 is connected to the input of the element OR 41, the second in, the coding of which is connected to the output of the delay element 42, and the output to the input of the counter 43, the second input of which is connected to the output of the second element And 44, and the group of outputs to the group inputs of the decoder 45, the output of which is connected to the input of the element 42 of the delay and with the first inputs of a group of elements And 46.  Each output of the output group of the decoder 45 is connected to the first inputs of the corresponding group of elements And 47 of the a groups of these elements.  The first input of the first element AND 40, the first input of the second element AND 44, the second inputs of the group of elements AND 46 and the second inputs of each group of elements AND 47 of the n groups of these elements are connected to the first input 48 of switch 1.  The second input of the second element is And 44, the third inputs of the group of elements And 46 and the third inputs of each group of elements And 47 of the VI groups of these elements are connected to the second input 49 of switch 1, and the second input of the first element And 40 with the third input 50 of switch 1.  The output of the first element And 40, the output of the decoder 45 and the outputs of the group of elements And 46 are combined into the first output 51 of switch 1, and the output of the first element And 40, the group of outputs of the decoder 45 and the outputs of each group of elements And 47 of the l groups of these elements are combined into the second output 52.  switch 1.  The outputs of the first element OR 53 and the second element OR 54 are connected 13, respectively, with the zero input of the first trigger 55 and the zero input of the second trigger 56.  The first inputs of the first element OR 53 and the second element OR 54 are connected to the input 5 of the generator, and the second inputs of the first element OR 53 and the second element OR 54 and the single ones of the first trigger 55, and the second trigger 56 are connected to a group of inputs of 58 bodies.  The unit output of the first trigger 55 and the unit output of the second trigger 56 are connected to the output 59 of the driver.  The output element OR 60 is connected to the zero input of the trigger 61, the zero output of which is connected to the input of the first element And 62, the output of which is connected to the input of the second delay element 65, the output of which is connected to the single input of the trigger 6 and the input of the second delay element 65, the output of which is connected to the input of the third element And 66 and to the input of the third delay element 67, the output of which is connected to the input of the fourth element And 68.  The second input of the first element AND 62 is connected to the first input 69 of the node 26 by scaling the NIN, and the first input of the element OR 60 is connected to the second input 70 of the node 26 of the scaling.  The second input of the element OR 60 is the third input of the first element AND 62 and the second inputs of the second element AND 64 of the third element AND 66, the fourth element And 68 are connected to the third input 71 of the scaling node 26.  The outputs of the element OR 60, the second element AND 64, the third element AND 66 and the fourth element AND 68 are connected to the output 72 of the first scaling node 26, the V7Oroy and the third outputs of the first Raman adder 73 connected respectively to the first input of the first element AND 74, the first input of the second element And 75, the first input of the third element And 76, the outputs of each of which are connected to the inputs of the first element OR 77.  Per „- you, the second and third outputs of the second combinational adder 78 are connected respectively with the first input of the fourth element And 79, with the first input of the fifth element And 80, with the first inputs of the sixth element And 81, the outputs of each of which are connected to the inputs of the second element OR 82, the output of which is connected to the input element 2114 of the HE 83 and with the input of the seventh element I 84, the second input of which is connected to the zero output of the trigger 85, the single output of which is connected to the input of the eighth element And 86, the second input of which is connected to the output of the element NO 83, and the output to the input of the third element OR 87, the second input of which is connected to the output of the seventh element AND 84 and to the input of the first delay element 88 whose output is connected to the single input of the trigger 85.  The output of the first element OR 77 and the output of the third element OR 87 are connected respectively to the first and second inputs of the third Raman adder 89, the first output of which is connected via the second delay element 90 to the third input of the third Raman adder 89.  The second inputs of the first element And 74, the second element And 75, the third element And 76, the fourth element And 79, the fifth element And 80, the sixth element And 81 and the zero input of the trigger 85 are connected to the input 91 of the input node 27, and the group of inputs of the first combinational the adder 73 and the group of inputs of the second combinational adder 78 - with a group of input 92 of the input node 27, the second output of the third combinational adder 89 is connected to the output 93 of the input node 27.  The output of the first element And 94 is connected via the first delay element 95 to the input of the delay element 96, to the input of the second element 97 and to the input of the first element NOT 98, the output of which is connected to the input of the third element AND 99 whose output is connected to the input of the first element OR 100, the output of which is connected to the zero input of the first trigger 101, the single input of which is connected to the output of the second element 97.  The output of the second delay element 96 is connected to the input of the fourth element AND 102 and to the input of the second element NOT 103, which is connected to the input of the fifth element AND 104, the output of which is connected to the input of the second element OR 105, the output of which is connected to zero. vm the input of the second trigger 106, a single input of which is connected to the output of the fourth element And 102.  . Zero and single outputs of the first trigger 101 are connected respectively to the first input of the sixth element AND 107 and to the first input of the seventh element And 108, the second input of each of which is connected to the single output of the second trigger 106.  The first input of the first element AND 94 is connected to the first input 109 of the node FOR allocating output increments, and the second input of the first element OR 100 and the second input of the second element OR 105 are connected to the second input 110 of the node 34 in the output increments.  The second inputs of the first element And 94, the second element And 97, the third element And 99, the fourth element And 10 and the fifth element And 104 are connected to the third input 111 of the node 34 in the left output increments, and the outputs of the sixth element And 107 and the seventh element And 108 are connected with.  the output 112 of the allocation unit 34; the output increments.  Before starting, the module is installed in its original state.  At the same time, a single signal is fed to the module selection input 17, which, having passed through the input 48 of switch 1, opens element 40, and when a reset signal is sent through input 19 of the module to input 50 of switch 1, this signal passes through the open element 40 and enters output 52 to the inputs for setting zero of registers 3 and 4 and counter 5, setting them to the zero state, and passing through the OR 15 element, this signal will set the triggers 13 and 14 to the zero state.  In addition, the reset signal from the output 52 of the switch 1 will go to the input 57 of block 6 and, having passed through the elements OR 53 and OR 54, will reset the triggers 55 and 56 to the zero state.  At the same time, the reset signal will come from the output of the element 40 and 40, the output 51 of the switch 1 to the digital integrator 2 through its first input to the inputs of setting zero registers 3 and 35, setting them to the zero state, and passing from the input 36 of digital integrator 2 through the input 70 of the node 26, and through the element OR 60, sets trigger 61 to the zero state.  In addition, the reset signal from the output of the OR 60 element will pass through the output 72 of the scaling node 26 and the input 91 of the input node 27 to the zero input of the trigger 85 and set it to the zero state. At the same time, the reset signal from the input 36 of the digital integrator is fed to the input 110 of the node 34 extracting the output increments and, having passed through the elements, OR 100 and OR 105, will reset to the zero state, respectively, tri1-ger 101 and trigger 106.  In addition, the reset signal from the output of the AND 40 element will pass through the OR 41 element and reset to the zero state the counter 43.  The flow is the entry of initial data.  At the same time, through input 17 to input 48 of switch 1, potential is applied to input of element I 44, to second inputs of group of elements I 46 and to second inputs of each group of elements And 47 from And groups of these elements, and via bus 18 to bus 49 of switch 1, the parallel data is supplied with the initial data that comes from the bus 49 to the third inputs of the group of elements AND 46 and to the third inputs to each groups of elements AND 47 of the P groups of these elements.  At the same time, one of the communication lines of the bus 18 initial data (usually the last communication line) to switch 1 to the second input of element I 44 receives data tracking pulses that pass through this element AND 44 (its second input receives the potential from input 17) to the summing input of the counter 43, the state of which is decoded by the decoder 45.  When each new tracking pulse arrives, the state of counter 43 increases by one, and a corresponding signal appears at the corresponding output of the decoder 45, which allows the initial data to pass through the corresponding element group 47 from 1 of these element groups and through output 52 of switch 1 to the inputs of the parallel record of register 3 or the corresponding register 4 addresses of the input increments.  At the same time, this single signal from the corresponding output of the decoder 45 will go through the output 52 of the switch 1 to the input of the recording resolution of the corresponding register 3 or 4, thereby ensuring the input of the initial information into the corresponding register.  In this case, the address 3 will contain the address corresponding to the module number on the block diagram of the problem solution, and the registers 4 - the input increment addresses corresponding to this module, t. e.  the numbers of those modules which, according to the structural scheme of the solution, problem

- 17

connected to the corresponding input of this module.

The last data tracking impulse transfers counter A3 to the last state, which at the last output of the decoder 45 turns on a single signal that will allow the passage of g) given Nyh through the group of elements 46 and; 51; 36 to the inputs of a parallel recording of the register 31 of the integrand, and at the same time this single signal from the last output of the decoder 45 will go through the output 51 of the switch 1 and through the input 36 of the digital integrator 2 to the input of the recording resolution of the register 31, and the result in the register 31 corresponding to a given module zapishets initial value of the integrand. In addition, a single signal from the last decoder 45 enters the input of delay element 42 and, delayed by one clock cycle on this delay element 42, enters through the HLI element 41 and resets counter 43 to the zero state. This entry of the initial data ends

 The willow modulus operates on one-bit increments represented in the ternary coding system, i.e. having three meanings: +1, 0, and -1, therefore, the exchange of increments between modules is carried out in two channels, positive and negative. The output elements of And 9 and 10 are performed according to the open-collector scheme, which allows for the simple assembly of their outputs to implement the INSTALL OR function. The scheme of connecting the modules to each other is shown in FIG. 8, where two outputs for each module are 23 positive increments and 24 negative increments, and two inputs — 21 positive increments and 22 negative module increments (in Fig. 8, only the inputs and outputs that provide the modules are shown between each other, and all other inputs that provide communication between the modules and other willow devices are omitted). As can be seen from FIG. 8, the output of positive increments of each module through the INSTALLER OR is connected to the input of the positive increments of each processor.

182118

and the output of the negative increments of each processor through the INSTALLATION OR is connected to the input of the negative increments of each module. 5 Module willow works as follows.

The signal allowing the decision, the module through the input 20 to the input of the counter 5 cycles start to arrive

) 0 from the central control unit pulse signals, which in each iteration successively change the state of counter 5 from 1 to (N + m + l), where N is the number of modes) 5 lei in the wave, W is the number of bits in the register integrand module function. In this case, the process of solving each iteration is divided into two stages: the step of transmitting increments

2Q and the calculation step. Moreover, the incremental transfer stage occurs in the first N cycles, i.e. when the counter changes its state from 1 to N, and the calculation step is performed in m

-. ticks, when the counter changes its state from M to (N + Gl), and the (M + T + 1) -th tick is used to prepare the module for the next interaction. Then, when entering the input of 20 pulsed

signals successively 0s

in each clock cycle the value of the counter 5

will begin to arrive as module addresses from 1 to M from the unit outputs of each bit of this counter in parallel code to the inputs of block 7

5 comparisons and at the inputs of the B blocks. If the address that came from the outputs of counter 5 to the inputs of comparison unit 7 with the module address recorded in register 3 coincides, the comparison unit 7 outputs the enable signal to the inputs of elements 9 and 10, thereby ensuring the passage of one-bit increments of the integral from output 39 digital integrator 2 through

 elements And 9 and 10 and through INSTALLING OR to inputs 21 and 22 of all willow modules.

If the address received from the outputs of counter 5 coincides with the address recorded in register 4, the corresponding node 8 compares the resolving signal to the inputs of the corresponding elements 11 and 12 and the one-bit increments of the integrap, which at

Inputs 21 and 22 of all modules (these will be one-bit increments of the integral from the codes 23 and 24 of that module that are connected to this input of this module and, therefore, whose address is written in the corresponding register 4 of this module) the corresponding elements of And 11 and 12 and recorded in the corresponding triggers 13 and 14.  After W clocks, counter 5 is set to a state equal to W, and the last N-th module will be redirected to increments.  At this stage, the transfer of increments will end, and in the next one that counter 5. switches to the state equal to H +1, and at the corresponding output of the decoder 16, a single signal is received that will arrive via the corresponding input from the group of inputs 58 of the former 6 to the single inputs of the flip-flops 55 and 56 and transfer them to a single state.  As a result, the trigger 55 will begin to generate a single signal with a duration (t-2) of a clock that will arrive from the single output of the trigger 5 via the output 59 of block 6 to the digital integrator 2 through the second input 37 to the shift control input of the integral remainder register.  Since the processor operates with one-bit increments, in accordance with the algorithm of its operation, quantization of the unquantized increments of the integral is performed as follows: quantized single-bit increments are allocated in the sign bits of the In-digit modified code of the unquantized integral increment of the integral, and the remaining the numeric bits of this code, without any significant bits, are allocated as the remainder of the integral, therefore the remainder register of the integral has (t-2) bits, and the shift control signal has a duration (Fn-2) cycles.  At the single output of the trigger 56, a signal will be generated at the same time, permitting calculations that will go through output 59 of the driver 6 and through input 37 to the digital integrator 2 to the input of the shift control of the integrate register 31, to the input of the -30 multiplication node, to the node 26 scaling through thirds of its input 71 to the third input of the And 62 element and to the second inputs of the And 64, 66 and 68 elements, as well as to the node 3, aiming the output increments through its third input 111, to the second input of the And 94 element and allowing this digital the integrator 2 numerical integration operations.  The computation stage with duration of m clock cycles (counter 5 at this time changes its state from W + 1) to (N + tri), during which the value of the integrand represented in the modified complementary binary code will come from the register output by the younger 31 bits ahead to the input of the adder 28 and to the first input 69 of the scaling node 26.  As a result, the first unit in the code of the integrand, which is the initial pulse, the position of which depends on the scale of the representation of the values, goes to the scaling node 26 via input 69, through the open element 62 and, having delayed for one clock cycle on the element 63 of delay, spreads the trigger 61 is in the unit state, thereby closing the element And 62, and simultaneously arrives through the open element And 64 (at the second input of this element, as well as at the second input of the elements And 66, 68 and the third input of the element And 62 enters through the input 71 from the 6 sig block cash, allowing computations) and via output 72 to the input node 27 as the first large impulse corresponding to the quantum of the integrand, t. e.  last minor.  In addition, after a delay of one clock cycle on delay element 65, this signal will arrive as the second scale of the pulse corresponding to the last but one. the discharge of the integrand function through the open element I 66 and through output 72 also into the input node 27, and having lagged one more clock cycle on the element 67 of the delay, this signal will arrive as the third large-scale pulse through the open element I 68 and through output 72 input node 27.  At the same time, one-bit increments represented in the ternary coding system are received. from the outputs of the trigger 13 positive increments and triggers 14 negative increments in the form of potentials corresponding to +1 or -1, through the group of inputs 38 21 of the digital integrator 2 and through the group of inputs 92 of the input node 27 to the inputs of the combinational adder 73 and the combinational adder 78, respectively, Moreover, summation of positive increments takes place in the combinational adder 73, and negative increments in the combinational adder 78.  The resulting sums of positive increments and negative increments are received respectively from the steps of the adder 73 and the outputs of the adder. and 78 parallel three-digit code (the number of bits in these codes, equal to the number of outputs from these cyi iMators, does not exceed three, since the number of simultaneously summable increments of the integrand j of the thermal a, and the number of inputs to the input node, t . e.  the number of inputs for the integrand function of a digital integrator does not exceed seven and in practice is usually 3-5) at the first inputs of the And 74-76 elements and the And 79-81 elements, respectively, the second inputs of which come from the output 72 of the scaling node 26 through the input 91 the input node 27, the first, second and third large-scale pulses in accordance with the weight of the discharge parallel to the three-bit code of the sum of increments.  Moreover, the first large-scale impulse corresponding to the quantum of the integrand, t. e.  the last, younger bit enters the second inputs of the elements And 74 and 79, the first inputs of which receive the lower bits of the three-bit parallel codes of positive increments and the sum of negative increments, respectively, the second large-scale pulse corresponding to the penultimate discharge of the integrand, goes to the second the inputs of the elements And 75 and 80, the first inputs of which are received average times. the rows of three-bit parallel kodos, respectively, are the sums of positive increments and the sum of negative growths, and the third large-scale impulse, as well as the higher bits of the three-time parallel codes of the summations, are sent to the inputs of the And 76 and 81 elements.  As a result, the scale impulses produced by the scaling unit 26, result in the sum of positive 21 22 and negative increments to the scale of the integrand function of this module and translate them from parallel binary to serial code.  At the same time, the number of scale signals produced by node 26 depends, just as the number of codes for adders 73 and 78, on the number of simultaneously summable increments of the integrand function and practically does not exceed three, since the maximum number of simultaneously summable increments of the integrand function is theoretically so And almost no more than seven.  The sequential code of the sum of positive increments, reduced to the scale of the integrand of this module, from the output of the element OR 77 goes to the first input of the combinational adder 89, and the sequential code of the sum of negative increments, coming from the output of the element OR 82, is first converted into an additional code, but potrm already with the output of the element OR 87 is fed to the second input of the adder 89.  The formation of an additional code for the sum of negative increments is performed as follows.  The first unit in the sequential code of the sum of negative increments coming from the output of the element OR 82 passes through the open element AND 84 (the second input of this element receives a single signal from the zero output of the trigger 85, since this trigger was set to the zero state in preparation for the decision signal reset) and will go unchanged through the element OR 87 to the second input of the adder 89, and delayed. Touching down for one clock cycle on delay element 88, this unit will go to the single input of trigger 85 and transfer it to a single state.  As a result, the trigger 85 closes the element And 84 and opens the element And 86, and the remaining consecutive code of the sum of negative increments, inverted on the element NO 83; will arrive in the inverse form through the open element I 86 and the element ШШ 87 to the second input of the adder 89.  The additional code of the sum of negative increments formed in this way, coming from the output of the element OR 87, will be summed up on the adder 89 with the sum of positive increments coming from the output of the element OR 77, and the total sum of the increments of the integrand function will come from the output of the adder 89 to the output 93 of the input node 27 .  A one-shot delay element 90 is included in the transfer chain of the adder 89 to form a bitwise transfer when summing the sum of positive increments with the sum of negative increments.  The resulting total sum of the input increments of the integrand from output 93 of input node 27 to the input of summator 28, to another input of which comes from register 31 is the value of the integrand.  The transfer chain of this adder 28 includes a single-cycle delay element 29 serving to form a transfer while adding the total sum of the input increments of the integrand to the current value of the integrand.  The resulting summation on the adder 28 a new value of the integrand will go to register 31 and to the input of the multiplication section 30, where this multiplication of the integrand will be multiplied by the increment of the integration variable that goes to another input of the 30 multiplication node from the output of the corresponding trigger 13 or 14 through corresponding input 38 of a digital integrator 2.  The result of the multiplication will go to the input of the adder 32 of the integral's remainder, to the other input of which the value of the integral's remainder is received from register 35.  A delay element 33 is included in the transfer chain of the adder 32, serving to form a transfer by adding multiplication with the current increase in the integral residual. The value of the non-quantized integral increment received at the input of the node 34, where the new value of the quantized increment is allocated, is summed up on the adder 32 integral, and in register 35, in which the allocated new remainder of the integral is written, which is the value of n according to the algorithm with one-bit increments The equivalence increments of the integral without sign bits and the sign bits define the value of the quantized increment of the integral.  And the introduction of new characters. The remainder of the integral is produced, as already noted, by using a shortened register that has (t-2) discharge, and by feeding from the shaper 6 from the output of the trigger 55 (gp-2) -shift shift control signal, according to which only 35 numerical bits without sign ones, and according to (N + m + O-My cycle, decoder 16 will generate a single signal through the corresponding input from the group of inputs 58 and through the OR 53 element to the zero input of the trigger 55, the trigger 55 of the former 6 will go to the zero state the information, and the shift of information in register 35 will stop.  The remaining sign bits that determine the value of the quantized increment of the integral are analyzed at node 34.  This is done as follows.  The value of the unquantized increment of the integral, acting from the output of the adder 32, will pass through the input 109 of the node 34 and arrive at the input of the element AND 94.  And since the signal entering the second input of this element AND 94 through input 111 of shaper 6 permitting calculations, this value of the unquantized increment of the integral passes through element And 94 and arrives at the input of delay element 95, is delayed by this delay element per clock (this the delay is performed so that the first (most significant) bit coincides with the module preparation signal for the next iteration appearing at the output of the decoder 16 at the end of the calculation step in (H + Mon-1) tact) and arrives at entry element 97 and through the element HE 98 at the input of the element AND 99, and having lagged one more clock cycle on the delay element 96 (this delay is performed so that the second (lower) sign bit, which follows a beat before the first (senior) sign yes, it coincided with the process preparation signal for the next iteration, the output of 5 ms appeared at the output of the decoder 16, as already noted, at the end of the calculation step in the (N + ni + 1) -M cycle in order to enable simultaneous analysis of both sign bits), enters the input of the element And 102 and through the element NOT 103 to the input element AND 104, A to the second inputs of elements AND 97, 99, 102 and 104 enters at the end of the calculation step in the (N + tn + -1) -M cycle from the output of the encoder 16 through input 37 of the digital integrator 2 and through input 111 of node 34, the signal for preparing the module for the next interaction, since the counter 5 is established in this cycle also in the state equal to (W + m + Oj and B as a result of this signal, triggers 101 and 106 are set in the corresponding corresponding to the eldest and youngest significant races, t. e.  trigger 101 will analyze the sign, and trigger 106 will override the sign bit.  Since the quantized increments of the integral are one-bit and are represented in the ternary coding system, the increment coding is as follows: 01– +1, 11 –1, and 00– 0 t. e.  if the modulo prepay signal for the next iteration, appearing at the output of the decoder 16 at the end of the computation step in the (H + Hp + 1) -th cycle, the trigger 101 is set to the Zero state, and the trigger 106 is set to one, then the output of the element And 107 in terms of a single signal with a duration of one iteration, corresponding to strings, to the positive increment of the integral +1, which through the output 112 of the node 34 and through the output 39 of the digital integrator 2 will go to the input of the element And 9 positive increments; if on the signal of preparation of the module for the next interaction in (N + KD + DM cycle, both triggers 101 and 106 are set to one state, then a single signal of one iteration duration, corresponding to a negative increment of the integral -1, turns out at the output of the And element 108 and go through the output 112 of the node 34 and through the output 39 of the digital integrator 2 to the input element And 10 negative. increments.  If both triggers 101 and 106 turn out to be in the zero state, they will not be output on output 112 of node 34, which corresponds to. the increment value of the integral, equal to O.  At the same time, in (N + m + 1) -M cycle from decoder 16 to block 6 through 2112 cut the corresponding input from the group of inputs 58 and through the OR 54 element to the zero input of trigger 56 ,.  In the calculation resolution enable signal, a single signal will arrive that will transfer this trigger 56 of block 6 to the zero state, stopping the supply of the calculation resolution signal to input 37 of the digital integrator and completing the calculation step of duration, hp clock cycles.  In addition, the cycle 5 () -M used to prepare the module for the next iteration, at the output of the decoder 16, due to the fact that the counter 5 is set to the state equal to (l + m + l), the reset signal will come from the output of the decoder 16 through the element OR 15 to the zero inputs of the triggers 13 and 14, preparing them for the step of transmitting the increments in the next iteration.  This signal will then go through input 37 of digital integrator 2 to scaling node 26 through its third input 71 and through element OR 60 to zero input of trigger 61, set it to zero state, and from output of element OR 60 this signal will come through output 72 of node 26 and through the input 91 of the node 27 to the zero input of the trigger 85, setting it to the zero state and thus preparing the node 26 and the node 27 for the calculation step in the next iteration.  At the same time, this signal from the output of the decoder 16, corresponding to the state of counter 5, equal to (N + tTi + 1), will go through the output. 25 module c. The central control unit, and in case of coincidence of these signals, entering the central control unit of the IVS from the inputs of 25 all the modules of the IVS, indicating the absence of any disruptions in the counting process at the first iteration, the central control unit of the IVS will continue to give impulse signals on the input. There are already 20 all modules of the ICS for the next iteration.  And the first pulse signal in the first clock cycle of the next iteration will transfer counter 5 from the state (M - (- tTi + 1) to the equal-one state (counter 5 is a modulo-counter (N + m + 1), and.  the second iteration begins, during which W increments will be redirected after W clocks and TU No. 27.  the numerical integration operation is performed, and in (N + in + 1) -ft cycle, the module will be prepared for the next interaction, as well as the control of the counting process by the central IVS control, and if there are no failures in the counting process, the central IO control will continue to generate pulsed signals at input 20, and in the next clock cycle, counter 5 will go from the state (L / + - t + 1) to the state equal to one, and a new iteration will begin, and so on. d.  In the event that when the counting process is monitored, in the (N + m + 1) -M cycle of some iteration, the central control unit -ICS will find that there is no signal from the output 25 of at least one ICS module in this cycle, which indicates the presence of a fault in during the counting process, the central control unit of the ICS will stop 21 pulsing the signals to the inputs 20 of the module, and the decision process will be stopped.  Thus, the proposed ICT module, along with the performance of the numerical integration function, provides the possibility of universal switching, i. e.  Any input of any module can be connected to any output of any module by setting the corresponding address to the register address of the input increments.  At the same time, in comparison with a well-known IVS module, the equipment costs for the proposed module, taking into account its implementation on modern chip complexes, do not exceed the costs of a known module, which allows creating on its basis ITTs of the same computing power as the known module, but providing universality of switching at the same time greatly simplifies the programming of the problem and reduces the time of preparing the task for solving

25

/ 7 18 W

Phg / s. 7

FIG. 2

FIG. eight

Claims (2)

1. MODULE OF AN INTEGRATING COMPUTER STRUCTURE, comprising a switch and a digital integrator, the output of the installation being in the initial state, the group of outputs of the initial data of the integrand and the output pulse of the tracking of the initial data of the integrand of the switch are connected respectively to the input of the installation to the initial state, with a group of inputs of the initial data and input enable recording the initial data of the digital integrator, and the first input, group of inputs and the second input of the switch are connected respectively to the input module selection, with the module initial data bus and module reset input, characterized in that, in order to expand the scope by solving more complex systems of equations, it additionally contains the module address register, a group of 3 input increment address registers (where Z is the number of input increments of the digital integrator), address comparison unit. modules, a group of 3 blocks comparing the addresses of input increments, a group of 3 triggers of positive increments, a group of 3 triggers of negative increments, a group of 3 input elements AND positive increments, a group of 0 input elements I. negative increments, output elements And positive and negative increments, a clock counter, an OR element, an incomplete decoder and a pulse shaper, and the output of the installation to its initial state, 1st (ί = 1, 2,3,.,. 3) the group of information outputs and the output of the <th pulse from the group of outputs of the pulse pulses for tracking the initial data of the switch are connected respectively to the zero-setting input, the group of information inputs, and the write permission input of the 1st register of the address of the group input increments, and the output of the installation to its initial state, the (3 + 1) th group of information outputs and the output of the (3 + 1) th pulse from the group of outputs of the pulses of tracking the initial data of the switch are connected respectively to the zero setting input, to the group of information inputs and write enable input module address register, setting the initial state output switch connected to the input zero-setting clocks counter with the reset input of the pulse duration and to an input of the OR gate, the output of each unit discharge D 128 UN of the address module of the module is connected to the first group of inputs of the module for comparing the addresses of the module, the second group of inputs of which is connected to the pear of the single outputs of the clock counter, and the output is connected to the first input of the output element AND of positive increments and the first input of the output element AND of negative increments the second inputs of which are connected respectively to the outputs of the positive and negative increments of the integral of the digital integrator, and the outputs with the outputs of positive and negative increments of the processor, respectively In fact, the single output of each bit of the ιth register of the address of the input increments of the group is connected to the first group of inputs of the 1st block for comparing the addresses of the input increments of the group, the second group of inputs of which is connected to the group of single outputs of the clock counter, and the output of the ϊth block of comparing the addresses of input group increments connected to the first input of the <th input element AND positive group increments and to the first input of the ίth input element AND negative group increments, the second inputs of which are connected respectively to the input field of positive module increments and with the input of negative module increments, and the outputs are connected respectively to the single input of the ίth trigger of positive increments of the group and to the single input of the 1st trigger of negative increments of the group, whose unit outputs are connected respectively to the tth inputs from the groups of inputs of positive and negative values of the input increments of the digital integrator, the group of inputs of the incomplete decoder is connected to the group of single outputs of the clock counter, status outputs (Ν +1) (where N is the number of modes in the integrating computational structure), the state (Ν + m ~ 1) and the state (N + m + 1) of the incomplete decoder (where tn is the number of bits in the register of the integrand of the digital integrator) are connected respectively to the first, second, and third inputs of the clock group (inputs of the shaper of the duration of the pulses, the zero input of each trigger of positive increments of the group and each trigger of negative increments of the group is connected to the output of the OR element, the second input of which is connected to the state output (M + t + 1) of the incomplete decoder, you the signal strokes with the duration of M clocks and the signal duration (t-2) of the pulses of the pulse shaper and the state output (\ l + ni + 1) of the incomplete decoder are connected respectively to the input of the calculation resolution signal, to the input of the signal for extracting the remainder of the integral and to the input of the signal of the end of the iteration digital integrator, the counting input of the clock counter is connected to the input of the counting resolution of the module, and the status output (N + 'n + D of the incomplete decoder is also connected to the control output of the clock of the module. 2. The module pop. ^ characterized in that the pulse width former comprises two OR elements and two triggers, wherein the output of the first OR element and the output of the second OR element are connected respectively to the zero input of the first trigger and to the zero input of the second trigger, the first inputs of the first OR element and the second OR element are connected with the reset input of the driver, the first input from the group of clock inputs of the driver is connected to the unit inputs of the first and second triggers, the unit outputs of which are connected respectively to the signal output for with the duration of m cycles and with the output of the signal with the duration (t-2) of the shaper cycle, the second inputs of the second OR element and the first OR element are connected respectively to the second and third inputs from the group of clock inputs of the shaper, the first input from the group of clock inputs of the shaper is connected to single inputs of the first and second triggers. - ® I