RU2029368C1 - Device for simulating neurons - Google Patents

Abstract

FIELD: bionics and computer engineering. SUBSTANCE: device has a unit for changing synaptic weighing unit first n inputs of which are the main information inputs of the device and second n inputs of which are setting ones. The device is characterized by the use of n/m (m<n, n ≥ 12, m ≥ 2) adders, n/m output units, switching unit and addressing unit, each output unit having first and second AND gates, first and second registers and logic unit. The device provides simulating formally-logic, gradual, dynamic adaptive and non-adaptive models of neurons, spatial adder, computer of scalar production and digital integrators. EFFECT: widened operating capabilities, simplified construction. 2 cl, 1 dwg

Description

 The invention relates to bionics and computer engineering and can be used as an element of neural networks in modeling neurophysiological processes in the nervous system, in processing devices, analysis and pattern recognition, in intellectual work control systems, in digital neurocomputers.

 Known devices (ed. St. USSR N 682910, class G 01 G 7/60, 1979; ed. St. USSR N 767788, class 1980) containing n blocks for changing synaptic weights, an adder and five digital integrators.

 The disadvantage of these devices is their lack of functionality that does not allow simulating adaptive neurons.

 It is also known a device (ed. St. USSR N 736130, class G 06 G 7/60, 1980) containing n synapse simulation blocks, an adaptive adder, three adders, a comparison unit and ten digital integrators. The device has wider functionality and allows, in particular, to simulate adaptive neurons, but has high hardware complexity.

 The closest in technical essence to the claimed is a device for modeling an adaptive neuron (ed. St. USSR N 708369, class G 06 G 7/60, 1980), containing a unit for summing synaptic weights, the first n inputs of which are the inputs of the device, and the output the synaptic balance summation unit is connected to the input of the integration variable of the first digital integrator, the output of which is connected to the first input of the first adder, the second input of which is connected to the output of the second digital integrator, the input of the integrator which is connected to the output of the third digital integrator, the input of the integrand of which is connected to the output of the first adder, the output of which is connected to the first input of the second adder, the output of which is connected to the input of the integrand of the fourth digital integrator, the output of which is connected to the input of the comparison unit, the output of which is the output of the device and is connected to the input of the integration variable of the fifth digital integrator, the output of which is connected to the first input of the third adder, the second input of which It is connected to the output of the sixth digital integrator, the variable integration input of which is connected to the output of the seventh digital integrator, whose integrand input is connected to the direct output of the third adder, whose inverse output is connected to the second input of the second adder, the output of the eighth digital integrator is connected to the third adder input, the fourth input of which is connected to the output of the ninth digital integrator, the input of the integration variable of which is connected to the output of the third digital integrator ora, the inputs of the integration variable of the third, fourth, seventh and eighth digital integrators are connected to one control input of the device, the second n outputs of the summation unit of the synaptic weights and the inputs of the integrand of the first, second, fifth, sixth, eighth and ninth digital integrators are connected to other control inputs devices respectively.

The disadvantages of the prototype are not wide enough functionality that does not allow it to be used for modeling various known models of neurons, their functional units and ensembles, as well as high hardware complexity that impedes the use of modern microelectronic technology. Indeed, each digital integrator in its minimum configuration (working according to the rectangle formula) contains two adders, two registers, a multiplier and a quantizer. Considering that the block of summation of synaptic weights for n inputs in the prototype is also implemented on digital integrators (one integrator per input), we can assume that the hardware costs for implementing the prototype are approximately 2 (n + 9) +4 adders, 2 (n +9) registers, n + 9 multipliers, n + 9 quantizers and one comparison unit. This level of complexity does not allow, in the current state of microelectronic technology, to implement the prototype in the form of a large integrated circuit, and therefore makes it impossible to build a modeling neural network or parallel neurocomputer, sufficient for practical purposes of dimension 10 ³ -10 ² elements.

 The aim of the invention is the expansion of functionality and simplification of the device.

 The goal is achieved by the fact that in the device containing the synaptic balance change unit (in the prototype, the synaptic balance summation unit), the first n inputs of which are the main information inputs of the device, and the second n inputs are installation inputs, n / m (m <n, n> 12, m> 2) adders, n / m output blocks, a switch and an addressing block, and the third n inputs of the synaptic balance change block are additional information inputs of the device, and n / m partial sum outputs are connected respectively to the first inputs of each and n / m adders, the second m inputs of each of which are connected respectively to the first group of n outputs of the switch, the outputs of all n / m adders are connected to the inputs of the corresponding n / m output blocks, to the first group of n / m inputs of the switch a group of n / m outputs of the device, the first, second and third outputs of all output blocks are connected respectively to the second, third and fourth groups of n / m inputs of the switch and are respectively the second, third and fourth groups of n / m outputs of the device, and the fourth outputs of all output blocks are connected to the third single inputs of the respective adders, the second and third groups of n outputs of the switch are connected respectively to n primary and n additional information inputs of the device, and the address inputs of the switch are connected to the outputs of the addressing block, each output block contains the first and second elements And, the first inputs of which are connected and are the input of the output block, the first and second registers, the inputs of which are connected respectively to the outputs of the first and second elements And, and the logical block, input rows of which are connected to the outputs of the second AND gate and a second register which, together with a logical block and the first register outputs are respectively the first, second, third and fourth output block outputs.

 The presence of distinctive features: n / m adders, n / m output units, switch and addressing unit with the above connections determines the compliance of the claimed technical solution with the criterion of "novelty." The claimed technical solution also meets the criterion of "significant differences", because no solutions were found with features similar to those distinguishing the claimed technical solution from the prototype.

 The ability to achieve the purpose of the invention is the expansion of functionality and simplification of the device is due to the presence of the listed distinctive essential features of the proposed technical solution. Indeed, by changing the configuration program of the proposed device’s switch using the addressing unit, it is possible, in particular, to reproduce formal logical models of neurons, graded models of neurons, dynamic models of non-adaptive neurons, dynamic adaptive models of neurons with adaptation either by input or output, or by input and output simultaneously, a spatial adder with n inputs, scalar product calculators, digital integrators.

 The inventive device, in addition, is simpler than the prototype. So, for m = 2, which is already enough to implement all the functions listed above, it contains n + n / 2 adders, 2n + 2 registers (the addressing block is essentially two address registers), n multipliers, n triggers, 3n elements of type AND (OR), one switch. Assuming, for example, n = 12, get 46 adders, 42 registers, 21 multipliers, 21 quantizers, one comparison unit, for the inventive device 18 adders, 26 registers, 12 multipliers, 12 triggers, 36 AND elements (OR), for the prototype one switch.

 The presence of significant distinguishing features of the proposed technical solution allows, expanding the functionality of the prototype, at the same time simplify it and thereby achieve the purpose of the invention.

 In FIG. 1 shows a structural diagram of a device; figure 2 is a functional diagram of a block for changing synaptic weights; figure 3 is a structural-functional diagram of the output unit; figure 4 is a functional diagram of a logical block; figure 5 is a structural-functional diagram of the switch and the addressing unit.

A device for modeling neurons (Fig. 1) contains a synaptic balance change unit 1, which has n main information inputs 2 ₁ , 2 ₂ ,. . . , 2 _n , n additional information inputs 3 ₁ , 3 ₂ , ..., 3 _n and n installation inputs 4 ₁ , 4 ₂ , ..., 4 _n . The outputs of partial sums of m terms of each of this block are connected to the inputs 5 ₁ , 5 ₂ , ..., 5 _{n / m of} combinational adders 6 ₁ , 6 ₂ , ..., 6 _{n / m} . The outputs of the adders 6 ₁ , 6 ₂ , ..., 6 _{n / m are} connected to the inputs of the output blocks 7 ₁ , 7 ₂ . .., 7 _{n / m} and are the first group of n / m outputs 8 ₁ , 8 ₂ , ..., 8 _{n / m} devices. The output blocks 7 ₁ , 7 ₂ , ..., 7 _{n / m} have outputs 9 ₁ , 9 ₂ , ..., 9 _{n / m} , 10 ₁ , 10 ₂ , ..., 10 _{n / m} , 11 ₁ , 11 ₂ , ..., 11 _{n / m} , which make up the second, third and fourth groups of n / m outputs of the device and, in addition, together with the group of outputs 8 ₁ , 8 ₂ ,. . ., 8 _{n / m are} connected to the inputs of the same name on the switch 12. Adders 6 ₁ , 6 ₂ , ..., 6 _{n / m} have groups of m inputs 13 ₁₁ , 13 ₁₂ , ..., 13 _1m , 13 ₂₁ , 13 _22,. . . , 13 _2m , 13 _{n / m1} , 13n / _m2 , ..., 13 _{n / mm} , which are connected to the outputs of the same name on the switch 12, as well as single inputs 14 ₁ , 14 ₂ , ..., 14 _{n / m} , which connected to the corresponding outputs 15 ₁ , 15 ₂ , ..., 15 _{n / m of the} output blocks 7 ₁ , 7 ₂ , ..., 7 _{n / m} . The main 2 ₁ , 2 ₂ , ..., 2 _n and additional 3 ₁ , 3 ₂ , ..., 3 _n device inputs are also connected to the outputs of the same switch 12. Address inputs 16 ₁ and 16 _{2 of the} switch 12 are connected to the block outputs 17 addressing.

Block 1 changes the synaptic weights (figure 2) consists of n cells of the same type, each of which contains a series-connected shift register 18, an adder 19 and a multiplier 20. The output of the adder 19 is connected to the input of the shift register 18. The second inputs of the multipliers 20 and the adders 19 are respectively the main 2 ₁ , 2 ₂ , ..., 2 _n and additional 3 ₁ , 3 ₂ , ..., 3 _n information inputs of the device, and the second inputs of the registers 18 shift - installation inputs 4 ₁ , 4 ₂ , ..., 4 _n devices. The outputs of the multipliers 20 by m are combined on the adders 21, the outputs of which are the outputs 5 ₁ , 5 ₂ , ..., 5 _{n / m are} partial sums of the synaptic balance change block.

 The output block 7 (figure 3) contains the elements And 22, 23, the first inputs of which are connected and are the input of the block 7, the shift registers 24, 25, the inputs of which are connected to the outputs of the elements And 22, 23, respectively, the logical block 26, the inputs of which are connected to the outputs of the element And 22 and the register 24 shift. The second inputs of the elements And 22, 23, as well as the third, fourth, fifth and sixth inputs of the logical unit 26 are the control inputs 27 of the device. The outputs of the element And 22, the shift register 24, the logic unit 26 and the shift register 25 are respectively the outputs 9, 10, 11 and 15 of the output unit 7 and the entire device.

The logical block 26 (Fig. 4) contains triggers 28, 29, the first inputs of which are connected and are the first input 30 of the logical block 26, which is connected to the output of the element And 22, the elements And 31, 32, the first inputs of which are connected to the inverse output of the trigger 29 , the elements And 33, 34, the first inputs of which are connected respectively to the outputs of the elements And 31, 32, while the second input of the element And 33 is the second input 35 of the logical unit 26 and is connected to the output of the shift register 24, and the second input of the element And 34 is connected to trigger direct output 28, OR element 36, inputs of which connected to the outputs of the elements AND 33, 34, and the output is the output of the logical unit 26 and the third output 11 of the output unit 7 and the entire device. The second inputs of the triggers 28, 29 and the elements And 31, 32 are respectively the control inputs 27 ₃ , 27 ₄ , 27 ₅ , 27 _{6 of the} logical block 26.

The switch 12 (Fig. 5) contains a matrix of 37 trigger keys, the sampling inputs of which along the X and Y axis are connected to the outputs of the address decoders 38 ₁ , 38 ₂ . The inputs of the decoders 38 ₁ , 38 _{2 are} connected to the bit outputs of the address registers 39 ₁ , 39 ₂ , which essentially comprise the device addressing unit 17. The information inputs of the switch are connected to a matrix of 37 trigger keys. The information outputs of the switch 12 through the buffer register 40 are connected to the information outputs of the matrix 37. The switch 12 also has an input 41 for recording control of the switching program and an input 42 for controlling information output. The switch can be made on a serial chip K1801VP1.

Before starting operation of the device, the registers 18 ₁ , ..., 18 _n and the registers of the multipliers 20 ₁ , ..., 20 _{n of the} block 1 for changing the synaptic weights (Figs. 1 and 2), the registers 24, 25 of the output block are reset to zero 7 (Figs. 1 and 3), flip-flops 28, 29 of the logic block 26 of the output block 7 (Figs. 1, 3 and 4), address registers 39 ₁ , 39 ₂ of the addressing block 17 (Figs. 1 and 5) and buffer register 40 switch 12 (figures 1 and 5). After that, the device is configured for the selected operating mode. For this, the required switching code is recorded in the address registers 39 ₁ , 39 ₂ of the addressing unit 17. The switch 12 has 3n outputs and 4n / m inputs connected respectively to the information inputs and through the buffer register 40 to the information outputs of the trigger key matrix 37. In other words, the switch trigger matrix is 3nx4n / m. In order to form the required communication channel between the ith information input and the jth information output of matrix 12 of switch 12, the corresponding switching codes are written into registers 39 ₁ and 39 ₂ , under the action of which single signals appear at the outputs of decoders 38 ₁ and 38 ₂ in the single state, the trigger key at the intersection of the jth row and the ith column of the matrix 37. The dimension of the switching codes and, therefore, the width of the registers 39 ₁ and 39 ₂ respectively log ₂ 3n and log ₂ 4n / m. By sequentially constructing the required communication channels using the method described above, the necessary switching system is implemented between the information inputs and outputs of the matrix 37 of trigger keys of the switch 12. After setting the required switching system, the logical blocks 26 of the output blocks 7 ₁ , are configured in the switch. . ., 7 _{n / m} (by applying a single or zero signal to the control inputs 27 _5, 27 ₆₎ to perform functions sign P _i, max {0, P _i} or disabling of these blocks, and then record in accordance registers January _18, ..., 18 _n block changes in the synaptic weights of the parameters of the implemented neuron models. After that, the device is ready for operation.

 Consider the setup process and the operation of the device for various modes of operation.

X_ijγ_ij
Как видно из временной диаграммы на фиг.6, под действием управляющего сигнала f₂₇₁ (поступающего на управляющий вход 27₁ каждого выходного блока 7₁, ...,7_n/m) старшие k разрядов (вместе со знаком) каждого из n/m чисел P_i через элементы И 22 (фиг.3) записываются в регистры 24 выходных блоков 7₁,. ..,7_n/m. При этом перед поступлением k старших разрядов числа P_i осуществляется сброс в нулевое состояние триггеров 28 логических блоков 26 каждого выходного блока 7₁,...,7_n/mпутем подачи в любом из k+1,...,2k (на фиг.6 в (k+1)-м такте) тактах времени управляющего сигнала f₂₇₃ на управляющие входы 27₃ логических блоков 26 каждого выходного блока 7₁,...,7_n/m, а в момент поступления самого старшего (знакового) разряда каждого числа P_i на управляющий вход 27₄ логического блока 26 каждого выходного блока 7₁,...,7_n/m подается единичный сигнал f₂₇₄ (фиг.6), под действием которого в триггер 29 логического блока 26 каждого выходного блока 7₁,...,7_n/m записывается значение знакового разряда соответствующего числа P_i: триггер 29 переходит в состояние "1", если P_i<0, и в состояние "0", если P_i ≥ 0. Если число P_i<0, то элемент И 32 логического блока 26 каждого выходного блока 7₁,..., 7_n/m закрыт и на выходе 11 каждого выходного блока 7₁,...,7_n/m в течение последующих k тактов времени формируется нулевой сигнал. Если P_i=0 (т.е. среди значащих разрядов нет ни одной "1"), то триггеры 28, 29 логического блока 26 каждого выходного блока 7₁,...,7_n/mнаходятся в нулевом состоянии элемент И 32 открыт, но элемент И 34 закрыт) и на выходе 11 каждого выходного блока 7₁,...,7_n/m также сформирован двоичный k-разрядный код нуля. Когда P_i>0, то триггер 28 переходит в единичное состояние, элементы И 32 и 34 открыты и на выходе 11 каждого выходного блока 7₁,...,7_n/m в течение k тактов времени формируется единичный сигнал. Таким образом, при данном режиме работы устройство реализует работу ансамбля из n/m не связанных между собой формально-логических моделей нейрона, каждый из которых выполняет следующий алгоритм:
P_i=

X

у_выхi=sign P_i.Operating mode 1: n / m formal-logical models of a neuron with m inputs each. In this mode, the device implements an ensemble of n / m unconnected formal logical neurons with m inputs each. In this mode, it is not necessary to establish communication channels between the inputs and outputs of the switch 12, therefore, in the registers 39 ₁ and 39 _{2 of the} switch, zero switching codes are stored, generated in them at the stage of resetting all device registers to zero. To the control inputs 27 ₅ , 27 _{6 of the} logical block 26 of each output block 7 ₁ ,. .., 7 _{n / m,} respectively, the zero and unit potentials are applied, which configure them to perform the sign P _i function. Then, into the registers 18 ₁ , ..., 18 _n through the installation inputs 4 ₁ , ..., 4 _{n of the} block 1 for changing the synaptic weights, the initial values of the synaptic weights γ _i1 , ..., γ _{inm of the neuron} models are written: synaptic weights _γi1 , ..., γ _im for each of the n / m neuron models. After that, the device is ready to receive input signals X _i1 , ... X _im to each of the n / m neuron models through the information inputs 2 ₁ , ..., 2 _{n of the} device. The device operates in accordance with the time diagram presented in Fig.6. During the first k clock cycles, the k-bit binary codes of input signals X _i1 , ..., X _in are received through the main information inputs 2 ₁ , ..., 2 _n into the registers of the multipliers 20 ₁ , 20 _n of the synaptic change block 1 weights (Figs. 1 and 2) and simultaneously output from the registers 24 through the information outputs 11 ₁ , ..., 11 _{n / m of the} output blocks 7 ₁ ,. . . , 7 _{n / m} k-bit binary codes of output signals at the _{outputs of} each of the n / m neuron models. If necessary, k-bit binary increment codes Δγ _i4 , ... Δγ _in synaptic weights can be received in the same first k time steps through additional information inputs 3 ₁ , ..., 3 _n and summed on the adders 19 ₁ , ... , 19 _n of the synaptic balance change block (FIGS. 1 and 2) with synaptic weights γ _i-1,1 , ... γ _{i-1, n} obtained at the previous (i-1) th step of the device operation. After that, over the next 2k clock cycles, multiplication in the multipliers 20 ₁ , ..., 20 _{n of the} input signals X _i1 , ..., X _{in is} performed by the synaptic weights γ _i1 , ..., γ _in and then the summation in the adders 21 ₁ ,. .., 21 _{n / m of} received 2k-bit products (m products for each of n / m neuron models). Received n / m sums of products from the outputs of block 1 of the synaptic weight change are fed to the inputs 5 ₁ , ..., 5 _{n / m} adders 6 ₁ , ... 6 _{n / m} , pass through these adders and appear on their outputs. Thus, during the considered 2k time steps, a 2k-bit binary code of the number is generated at the output of each of the adders 6 ₁ , ..., 6 _{n / m}
P _i =

X _ij γ _ij
As can be seen from the timing diagram in Fig. 6, under the action of the control signal f ₂₇₁ (arriving at the control input 27 _{1 of} each output unit 7 ₁ , ..., 7 _{n / m} ), the highest k bits (together with the sign) of each of n / m numbers P _i through the elements And 22 (figure 3) are recorded in the registers 24 of the output blocks 7 ₁ ,. .., 7 _{n / m} . Thus before entering MSBs number k P _i resets flip-flops in the null state 28, logic blocks 26 each output block 7 _1, ..., 7 _{n / m} by feeding in any one of k + 1, ..., 2k (for 6 in the (k + 1) -th cycle) clock cycles of the control signal f ₂₇₃ to the control inputs 27 _{3 of the} logic blocks 26 of each output block 7 ₁ , ..., 7 _{n / m} , and at the time of the arrival of the oldest (sign ) discharge of each of P _i to the control input ₂₇ April logic block 26, each output block 7 _1, ..., 7 _{n / m} is applied a single signal f ₂₇₄ (Figure 6) under the action in which t 29 igger logic block 26, each output block 7 _1, ..., 7 _{n / m} stored sign bit value corresponding to the number P _i: trigger 29 moves to state "1" if P _i <0, and "0" state, if P _i ≥ 0. If the number P _i <0, then the AND element 32 of the logic block 26 of each output block 7 ₁ , ..., 7 _{n / m is} closed and at the output 11 of each output block 7 ₁ , ..., 7 _{n / m} during the next k clock cycles a zero signal is formed. If P _i = 0 (that is, there is not a single “1” among the significant digits), then the triggers 28, 29 of the logic block 26 of each output block 7 ₁ , ..., 7 _{n / m} are in the zero state, element And 32 open, but AND element 34 is closed) and at the output 11 of each output block 7 ₁ , ..., 7 _{n / m} a binary k-bit zero code is also generated. When P _i > 0, then the trigger 28 goes into a single state, the elements And 32 and 34 are open and at the output 11 of each output block 7 ₁ , ..., 7 _{n / m} a single signal is generated during k clock cycles. Thus, in this operating mode, the device implements the work of an ensemble of n / m unconnected formal logical models of the neuron, each of which performs the following algorithm:
P _i =

X

at _{output i} = sign P _i .

From this mode of operation of a device for modeling neurons, it is easy to switch to another mode: n / m interconnected formal logical models of a neuron with m inputs each. For this, it is only necessary to establish the required structure of synaptic connections between neuron models, which is quite easily implemented by switch 12 by constructing (as described above) the necessary communication channels between the inputs and outputs of the switch, which are connected to the required information outputs 11 ₁ , ..., 11 _{n / m} and inputs 2 ₁ , ..., 2 _{n of the} device (Fig. 1). The operation of the device in this mode for each of the n / m models of the neuron is carried out in accordance with the time diagram in Fig.6.

If necessary, you can go to another close mode of operation of the device: one formal logical model of a neuron with n inputs. In this mode, the logical blocks 26 of the output blocks 7 ₁ , ..., 7 _{n / m-1 are} turned off by supplying zero potentials to their control inputs 27 ₅ , 27 ₆ , and the logical block 26 of the output block 7 _{n / m} remains configured for implementation the function y _oi = sign P _i (as was shown for the main mode 1). After this, the union of n / m adders 6 into one adder for n inputs. For this, in the switch 12, communication channels are implemented that connect the output 8 _l (l = 1,2, ..., n / m-1) of each previous adder 6 _l with one of the inputs 13 _{l + 1,1} , ..., 13 _{l + 1, m of the} subsequent adder 6 _{l + 1} (Fig. 1). The operation of the device in this mode is carried out as described above in accordance with the time chart in Fig.6.

X

на управляющий вход 27₄ логического блока 26 каждого выходного блока 7₁,...,7_n/m подается управляющий сигнал f₂₇₄, под действием которого триггер 29 переходит в единичное (если P_i<0) либо в нулевое (P_i ≥ 0) состояние. Тогда, если P_i ≥ 0, то элемент И 31 открывается и величина P_iс выхода регистра 24 через вход 35 и элемент И 33 логического блока 26 каждого выходного блока 7₁,...,7_n/m (фиг.1, 3 и 4) в течение последующих k тактов времени появляется на выходе 11 выходных блоков 7₁,..., 7_n/m. Если P_i<0, то элемент И 31 логического блока 26 каждого выходного блока 7₁,...,7_n/m закрыт и на выходе 11 выходных блоков 7₁,...,7_n/m в течение k тактов времени формируется нулевой сигнал. Иными словами в данном режиме устройство реализует работу ансамбля из n/m не связанных между собой градуальных моделей нейрона, каждый из которых выполняет алгоритм P_i=

X

у_выхi=max{0, P_i}.Operating mode 2: n / m degree neuron models with m inputs each. In this mode, the device implements the work of an ensemble of n / m unconnected gradual neuron models with m inputs each. The device is configured in the same way as for the n / m mode of formal logical models of the neuron. The only difference is that the control inputs 27 ₅ , 27 _{6 of the} logic block 26 of each output block 7 ₁ , ..., 7 _{n / m} are supplied with the unit and zero potentials, respectively, which configure the logic blocks to perform the function at the _{output i} = max { 0, P _i }. The operation of the device is carried out in accordance with the time diagram of Fig.6. After the formation in the register 24 of each output block 7 ₁ , ..., 7 _{n / m} k senior bits of the corresponding value of the value P _i =

X

to the control input 27 _{4 of the} logical block 26 of each output block 7 ₁ , ..., 7 _{n / m} , a control signal f ₂₇₄ is supplied, under the action of which the trigger 29 goes to single (if P _i <0) or to zero (P _i ≥ 0) condition. Then, if P _i ≥ 0, then the And 31 element opens and the value of P _i from the output of the register 24 through the input 35 and the And 33 element of the logical block 26 of each output block 7 ₁ , ..., 7 _{n / m} (Fig. 1, 3 and 4) during the next k clock cycles, it appears at the output of 11 output blocks 7 ₁ , ..., 7 _{n / m} . If P _i <0, then the element And 31 of the logical block 26 of each output block 7 ₁ , ..., 7 _{n / m is} closed and at the output of 11 output blocks 7 ₁ , ..., 7 _{n / m} for k clock cycles a zero signal is generated. In other words, in this mode, the device implements the work of an ensemble of n / m unconnected gradual neuron models, each of which performs the algorithm P _i =

X

at _{output i} = max {0, P _i }.

 From this mode of operation of the device, one can easily switch to close modes: n / m interconnected degree models of a neuron and one degree model of a neuron with n inputs. Such a transition is carried out in the same way as for the mode 1 described above.

Operating mode 3: dynamic model of a non-adaptive neuron on n-2m inputs. To implement this mode, the switch 12 implements a system of communication channels between the device units (communication channels are allocated) in accordance with FIG. 7. The implementation of these communication channels is carried out by setting the appropriate switching codes in the block 17 addressing and transfer to a single state of the required trigger keys of the matrix 37 of the switch 12, as shown above. In accordance with the switching shown in Fig.7, the output 10 _{1 of the} device is connected to the main information input 2m + 1 of the device, the output 9 _{2 of the} device is connected to the additional information input 3 _{1 of the} device, and the adders 6 ₃ , ..., 6 _{n / m} are combined into one common adder for n-2m inputs by connecting each l-th output of 8 _l device (l = n / m, ..., 3) with one of the inputs 13 _l-1,1 , ..., 13 _{l- 1, m of the} previous adder 6 _l-1 , and the output 8 _{3 of the} last of these adders 6 _{3 is} connected to any one of the inputs 13 ₂₁ , ..., 13 _2m (in Fig. 7, the input 13 _2m ) of the adder 6 ₂ . Thereafter, the register 18, _{m + 1} unit 1 changes of synaptic weights (1, 2 and 7) through the adjusting input 4 _{m + 1} is written k-bit binary value of inertia ratio (- α _i) a neuron model in the register 18 through _2m installation input 4 _{2m the} binary value of the threshold (θ _i ) of the neuron model is written, and in the registers 18 _{2m + 1,.} . . , 18 _n through the installation inputs 4 _{2m + 1} , ..., 4 _n binary values of the synaptic weights γ _{i, 2m + 1} , ..., γ _{i, n of} the neuron model are written. The logic blocks 26 of the output blocks 7 ₂ , ..., 7 _{n / m are} turned off by supplying zero potentials to their control inputs 27 ₅ , 27 ₆ , and the logic block of the output block 7 _{1 is} configured to implement the function at _{output i} = max {0, P _i } by supplying to its control inputs 27 ₅ , 27 _6, respectively, unit and zero potentials. After that, the device is ready to receive binary k-bit values of the input signals X _{i, 2m + 1} Δ t, ..., X _{i, n} Δ t coming through the main information inputs 22 _{m + 1} , ..., 2 _n devices . The device operates in accordance with the time chart in Fig. 8. During the first k clock cycles, reception is made through the main information inputs 2 _{2m + 1} , ..., 2 _{n of the} device of k-bit binary values of the input signals X _{i, 2m + 1} Δ t, ..., X _{i, n} Δ t which are recorded in the registers of the multipliers 20 _{2m + 1} , ..., 20 _{n of} block 1 of the change in the synaptic weights, as well as the output from the register 24 of the output block 7 ₁ through the output 11 _{1 of} the output device at the _output Δ t of the neuron model and through output 10 ₁ device of the magnitude of the membrane potential (P _i-1Δ t) of the neuron model, which is available via the communication channel (Fig. 7) through the information input 2 _{m + 1} It is written in the register of the multiplier 20 _{m + 1} . In the first step, that is, for i = 1, the value of P _o Δ t = 0 and is generated automatically by resetting all device registers to the zero state. During the first k time steps, the synaptic weights of the k-bit binary code of the value of the independent variable Δ t are recorded through the information input 2 _2m in the register of the multiplier 20 _{2m of the} block 1 and, if necessary, through additional information inputs 3 _{m + 1} , 3 _2m , 3 _{2m +1} , ..., 3 _n , k-bit binary codes of increments Δα _i , Δθ _i , Δγ _{i, 2m + 1} , ..., Δγ _{i, n} can be received, which are summed in the adders 19 _{m + 1} , 19 _2m , 19 _{2m + 1} , ..., 19 _n (Figs. 1, 2 and 7) with the values α _i-1 , θ _i-1 , γ _{i-1, 2m + 1} , ..., γ _{i-1 , n} obtained in the previous (i-1) -th step of the device.

X_ij·Δt·γ_ij-θ_iΔt
Как видно из фиг.8, под действием уп-равляющего сигнала f

2, поступающего на управляющий вход 27₁ выходного блока 7₂, старшие k разрядов числа Δ P_i поступают (фиг.7) через выход 9₁, канал связи в коммутаторе 12, вход 3₁ на сумматор 19₁ блока 1 изменения синаптических весов, где суммируется с величиной P_i-1, полученной на предыдущем (i-1)-м шаге (на первом шаге при i= 1 величина P_o=0 и формируется автоматически путем сброса всех регистров устройства в нулевое состояние) и хранящейся в регистре 18₁. Одновременно с этим через информационный вход 2₁ устройства осуществляется запись k-разрядного двоичного значения независимой переменной Δ t в регистр умножителя 20₁блока изменения синаптических весов. После этого в течение следующих 2k тактов происходит умножение в умножителе 20₁ величины P_i= =Δ P_i+P_i-1 на независимую переменную Δ t. Формируемое в течение этих 2k тактов времени 2k-разрядное произведение P_i Δ t проходит через сумматоры 21₁ и 6₁(фиг. 7), и в соответствии с временной диаграммой на фиг.8 под действием управляющего сигнала f

1, поступающего на управляющий вход 27₁, выходного блока 7₁, k старших разрядов этого произведения записываются в регистр 24 выходного блока 7₁ (фиг.1, 3 и 7). При этом в момент поступления самого старшего (знакового) разряда (на фиг.8 в 5-м такте времени) числа P_i Δ t на управляющий вход 27₄ логического блока 26 выходного блока 7₁ подается единичный управ- ляющий сигнал f

1, под действием которого в триггер 29 логического блока 26 выходного блока 7₁записывается значение знакового разряда величины P_i Δ t: триггер 29 переходит в состояние "1", если P_i Δ t<0, и в состояние "0", если P_i Δ t ≥ 0. Как указывалось выше, логический блок 26 выходного блока 7₁настроен на выполнение функции у_выхi=max{0, P_i}. Таким образом, в данном режиме устройство реализует алгоритм работы динамического неадаптивного нейрона, который имеет следующий вид:
ΔP_i= -α_iP_i-1Δt+

X_ij·Δt·γ_ij-θ_iΔt
у_выхi+1 Δ t=max{0, P_{i Δ} t}.Over the next 2k clock cycles of the device, multiplication takes place in the multipliers 20 _{2m + 1,.} .., 20 _n block 1 changes the synaptic weights of the input signals Xi _{, 2m + 1} Δ t, ... X _{i, n,} Δ t by the synaptic weights γ _{i, 2m + 1} , ... γ _{i, n} in the multiplier 20 _{m + 1 of the} quantity P _i-1 Δ t by the coefficient α _i , in the multiplier 20 _2m of the threshold θ _i by the independent variable Δ t and the summation on the adders 21 ₂ , ... 21 _{n / m} , 6 _{n / m} , .. ., 6 ₂ received works. As a result, during the considered 2k clock cycles, the output of the adder 6 ₂ generates a 2k-bit binary code of the number
ΔP _i = -α _i P _i-1 Δt +

X _ij Δt γ _ij -θ _i Δt
As can be seen from Fig. 8, under the action of the control signal f

2 received at the control input 27 _{1 of the} output unit 7 ₂ , the highest k bits of the number Δ P _i are received (Fig. 7) through the output 9 ₁ , the communication channel in the switch 12, input 3 ₁ to the adder 19 _{1 of the} unit 1 for changing the synaptic weights, where it is summed with the value of P _i-1 obtained at the previous (i-1) th step (at the first step at i = 1 the value of P _o = 0 and is generated automatically by resetting all device registers to zero) and stored in register 18 ₁ . At the same time, through the information input 2 _{1 of the} device, a k-bit binary value of the independent variable Δ t is recorded in the register of the multiplier 20 ₁ of the synaptic balance change unit. After that, over the next 2k clock cycles, the multiplier 20 ₁ multiplies the value of P _i = = Δ P _i + P _i-1 by an independent variable Δ t. The 2k-bit product P _i Δ t formed during these 2k clock cycles passes through the adders 21 ₁ and 6 ₁ (Fig. 7), and in accordance with the time diagram in Fig. 8 under the action of the control signal f

1, received at the control input 27 ₁ , of the output block 7 ₁ , k of the most significant bits of this product are recorded in the register 24 of the output block 7 ₁ (Figs. 1, 3, and 7). At the same time, at the time of the arrival of the most significant (significant) digit (in Fig. 8 in the 5th time step) of the number P _i Δ t, a single control signal f is supplied to the control input 27 _{4 of the} logical block 26 of the output block 7 ₁

1, under the action of which a sign value of the value P _i Δ t is recorded in the trigger 29 of the logical block 26 of the output block 7 ₁ : trigger 29 goes into state "1" if P _i Δ t <0, and into state "0" if P _i Δ t ≥ 0. As indicated above, the logic block 26 of the output block 7 _{1 is} configured to perform the function of the _{output i} = max {0, P _i }. Thus, in this mode, the device implements the algorithm of the dynamic non-adaptive neuron, which has the following form:
ΔP _i = -α _i P _i-1 Δt +

X _ij Δt γ _ij -θ _i Δt
at _{output i + 1} Δ t = max {0, P _{i Δ} t}.

 In the next 5k clock cycles, the operation of the device is completely repeated in accordance with the timing diagram in FIG.

Operating mode 4: dynamic model of an adaptive neuron on n-6m inputs. To implement this mode, the switch 12 implements (as described above) a system of communication channels between units of the device in accordance with FIG. 9 (communication channels are highlighted). In accordance with the switching shown in Fig.9, the output 10 _{1 of the} device is connected to the main information inputs 2 _{m + 1} and 2 _{6m of the} device, the output 9 _{2 of the} device is connected to the additional information inputs 3 ₁ and 3 _{2m + 1 of the} device, the output 11 _{3 of the} device is connected to the main information input 2 _{5m + 1} , the output 10 _{1 of the} device is connected to the main information input 2 _{4m + 1} , the output 9 _{5 of the} device is connected to the additional information inputs 3 _3m and 3 _{3m + 1} , the output 8 _{6 of the} device is connected to one of the inputs 13 _5.1 . .., 13 _{5, m} (in Fig. 9 input 13 _{5, m} ), and adders 6 ₇ , ..., 6 _{n / m} are combined into one common input on n-6m by connecting each l-th output 8 of the device (l = 7, ..., n / m) with one of the inputs 13 _{l + 1,1} , ..., 13 _{l + 1, m of the} subsequent adder 6 _{l + 1} , and the output is 8 _{n / m of the} last of these adders 6n / m is connected to one of the inputs 13 _2,1,. . . , 13 _{2, m} (in Fig. 9, the input 13 _{2, m of the} adder 6 _2. After that, k 18 is written in the register 18 _{m + 1 of the} block 1 for changing the synaptic weights through the installation input 4 _{m + 1} (Figs. 1, 2 and 9) -bit binary code of the number - α _{i, 1,} into the register 18 _{4m + 1} through the installation input 4 _{4m + 1} - code of the number - α _{i, 2} , into the register 18 _5m through the installation input 4 _5m - code of the number - θ *, in register 18 _{5m + 1} through the installation input 4 _{5m + 1} - code number α _1,4 , into the register 18 _6m through the installation input 4 _6m - code number - α _{i, 3} , and into the registers 18 _{6m + 1} , ..., 18 _n through the setting codes 4 _{6m + 1} , ..., 4 _n - codes of numbers γ _{i, 6m + 1} , ..., γ _{i, n} . Logic blocks 26 of the output blocks 7 ₁ , 7 ₂ , 7 ₄ ,. . ., 7 _{n / m are} switched off by supplying zero potentials to their control inputs 27 ₅ , 27 ₆ , and the logic block 26 of the output block 7 _{3 is} configured to implement the function _yi = max {0, P _i } by applying to its control inputs 27 ₅ and 27 _6, respectively and a single zero potential. Then the device is ready to receive the k-bit binary input signals X _{i, 6m + 1 Δ t, ..., X i,} n Δ t, the main information received through the input 2 _{6m +1,.} .., 2 _n devices. The device operates in accordance with the time chart in figure 10. During the first k clock cycles, k-bit codes of the numbers X _{i, 6m + 1} Δ t, ..., X _{i, n} Δ t through the main information inputs 2 _{6m + 1} , ..., 2 _n devices are recorded in the registers of multipliers 20 _{6m + 1} , ..., 20 _n block 1 changes synaptic weights (Fig.1, 2 and 9). At the same time, from the register 24 of the output block 7 _{1, the} code of the number P _i-1 Δ t is issued (in the first step, for i = 1, the value P _o = 0 and is generated automatically by resetting all device registers to zero), which is output 10 ₁ on the existing communication channel (Fig. 9), through the main information inputs 2 _{m + 1} and 2 _{6m, it is} written to the registers 18 _{2m + 1} and 18 _6m of the synaptic balance change unit, from the register 24 of the output block 7 _{3 the} code of the number of _{output, i- 1} Δ t (in the first step at a value of i = 1, y = 0 and _vyho formed automatically resetting all registers to zero device), which through a stroke 11 ₃ devices, the available communication channel (FIG. 9) through entrance 2 _{5m + 1} is written in the register of the multiplier 20 _{5m + 1,} from the register 24 of the output unit ₇ April issued code number θ _i-1 Δ t (in the first step with i = 1, the value θ _о = 0 and is formed automatically when all device registers are reset to zero), which is written out through the output 10 ₄ via the existing communication channel (Fig. 9), through the main information input 2 _{4m + 1} to the multiplier 20 _{4m + 1} . During the first k time steps, the code of the number Δ t is recorded through the information input 2 _5m in the multiplier register 20 _5m and, if necessary, through additional information inputs 3 _{m + 1} , 3 _{4m + 1} , 3 _{5m + 1} , 3 _6m , 3 _{6m + 1} ,. . . , 3 _n , codes of increments Δα _{i, 1} , Δα _{i, 2} , Δα _{i, 4} , Δα _{i, 3} , Δγ _{6m + 1} , can come. . ., Δγ _n , which are summed up on the adders 19 _{m + 1} , 19 _{4m + 1} , 19 _{5m + 1} , 19 _6m , 19 _{6m + 1} , ..., 19 _{n of the} block for changing synaptic weights with values α _i-1,1 , α _i-1,2 , α _i-1,4 , α _i-1,3 , γ _{i-1, 6m + 1} , ..., γ _{i-1, n} obtained in the previous (i-1) step of the device.

X_i,j·Δt·γ_ij а на выходе сумматора 6₅ формируется 2k-разрядный код числа
Δ θ_i =- α _i,2 θ _i-1Δ t- θ * Δ t- α _i,3P_i-1 Δ t- α _i,4y_выхi-1 Δ t.Over the next 2k cycles of operation of the device, the operation of multiplication in the multipliers 20 _{6m + 1} , ..., 20 _{n of the} quantities X _{i, 6m + 1} Δ t, ..., X _{i, n} Δ t by γ _{i, 6m + 1} , ..., γ _{i, n} , in the multiplier 20 _{6m of the} quantity P _i-1 Δ t by - α _{i, 3} , in the multiplier of 20 _{5m + 1 the} values of the _{output i-1} Δ t by - α _{i, 4} , in the multiplier 20 _5m magnitude - θ * by Δ t, in the multiplier 20 _{4m + 1} magnitude θ _i-1 Δ t by -α _{i, 2,} in the multiplier 20 _{2m + 1} magnitude P _i-1 Δ t by -α _{i, 1} and summation of the indicated 2k-bit products on the adders 21 ₂ , 21 ₅ , 21 ₆ , ..., 21 _{n / m} , 6 ₂ , 6 ₅ , 6 ₆ , ..., 6 _n . As a result, during the considered 2k clock cycles, the output of the adder 6 ₂ generates a 2k-bit code of the number
ΔP _i = -α _{i, 1} P _i-1 Δt +

X _{i, j} · Δt · γ _ij and at the output of adder 6 ₅ a 2k-bit code of the number is generated
Δ θ _i = - α _{i, 2} θ _i-1 Δ t- θ * Δ t- α _{i, 3} P _i-1 Δ t-α _{i, 4} y _outi-1 Δ t.

2, поступающего на управляющий вход 27₁выходного блока 7₂, старшие k разрядов числа Δ P_i поступают (фиг.9) через выход 9₂, имеющийся канал связи, входы 3₁ и 3_2m+1 на сумматоры 19₁и 19_2m+1, где суммируются с величиной P_i-1, полученной на предыдущем шаге (на первом шаге P_o=0) и хранящейся в регистрах 18₁ и 18_2m+1, а под действием управляющего сигнала f

5, поступающего на управляющий вход 27₁ выходного блока 7₅, старшие k разрядов числа Δθ_i поступают через выход 9₅, имеющийся канал связи (фиг.9), входы 3_3m и 3_3m+1 на сумматоры 19_3m и 19_3m+1, где суммируются с величиной θ_i-1, полученной на предыдущем (i-1)-м шаге (на первом шаге θ _о=0) и хранящейся в регистрах 18_3m и 18_3m+1. Одновременно с этим через информационные входы 2₁, 2_2m+1, 2_3m, 2_3m+1 устройства осуществляется запись k-разрядного числа Δ t в регистры умножителей 20₁, 20_2m+1, 20_3m, 20_3m+1 блока 1 изменения синаптических весов.As can be seen from the timing diagram in figure 10, under the action of the control signal f

2 received at the control input 27 _{1 of the} output unit 7 ₂ , the highest k bits of the number Δ P _i are received (Fig. 9) through output 9 ₂ , an existing communication channel, inputs 3 ₁ and 3 _{2m + 1} to the adders 19 ₁ and 19 _{2m +1} , where they are summed with the value of P _i-1 obtained at the previous step (at the first step P _o = 0) and stored in the registers 18 ₁ and 18 _{2m + 1} , and under the action of the control signal f

5, received at the control input 27 _{1 of the} output unit 7 ₅ , the highest k bits of the number Δθ _i enter through output 9 ₅ , an existing communication channel (Fig. 9), inputs 3 _3m and 3 _{3m + 1} to the adders 19 _3m and 19 _{3m + 1} , where they are summed up with the value θ _i-1 obtained at the previous (i-1) th step (at the first step θ _о = 0) and stored in the registers 18 _3m and 18 _{3m + 1} . At the same time, through the information inputs 2 ₁ , 2 _{2m + 1} , 2 _3m , 2 _{3m + 1 of the} device, a k-bit number Δ t is recorded in the registers of the multipliers 20 ₁ , 20 _{2m + 1} , 20 _3m , 20 _{3m + 1 of} block 1 changes in synaptic weights.

1, f

3, f

4, поступающих на управляющие входы 27₁ выходных блоков 7₁, 7₃, 7₄(фиг.3 и 10), k старших разрядов величины P_i Δ t записываются в регистр 24 выходного блока 7₁, k старших разрядов величины P_i Δ t- θ_i Δ t записываются в регистр 24 выходного блока 7₃ и k старших разрядов величины θ_i Δ t записываются в регистр 24 выходного блока 7₄. При этом в момент поступления самого старшего (знакового) разряда величины P_i Δ t- θ _i Δ t (на фиг. 10 5k такт времени) на управляющий вход 27₄логического блока 26 выходного блока 7₃ подается единичный управляющий сигнал f

3 , под дей- ствием которого в триггер 29 логического блока 26 выходного блока 7₃записывается значение знакового разряда числа P_iΔt-θ_i Δ t. После этого логический блок 26 выходного блока 7₃ оказывается настроенным на реализацию функции у_выхi= max{ 0, P_i} (функционирование блока 26 при реализации этой функции описано выше). В результате в данном режиме устройство реализует алгоритм работы динамического адаптивного по входу и выходу нейрона, который имеет следующий вид:
ΔP_i= -α_i,1P_i-1Δt+

X_i,j·Δt·γ_ij
Δ θ _i=- α _i,2 θ _i-1Δ t- θ *Δ t- α _i,3P_i-1Δ t-
- α _i,4 y_{вых i-1}Δ t;
y_выхin Δ t=max{0,(P_i Δ t- θ_i Δ t)}.Thereafter, during the next 2k cycles of time is multiplied in multipliers 20 _1, 20 _{2m + 1,} 20 _3m, 20, _{3m + 1,} respectively, the magnitude P _i = P _i-1 + Δ P _i to Δ t, the magnitude P _i = P _{i -1} + ΔP _i at Δ t, values θ _i = = θ _i-1 + Δ θ _i at Δ t, values θ _i = θ _i-1 + Δ t at Δ t formed during these 2k time steps 2k -bit products P _i Δ t, P _i Δ t, θ _i Δt, θ _i Δ t pass through the adders 21 ₁ and 6 ₁ , 21 ₃ and 6 ₃ , 21 ₄ and 6 ₄ and under the action of control signals f

1, f

3, f

4 arriving at the control inputs 27 _{1 of the} output blocks 7 ₁ , 7 ₃ , 7 ₄ (Figs. 3 and 10), k high order bits of the value P _i Δ t are recorded in the register 24 of the output block 7 ₁ , k high order bits of the value P _i Δ t- θ _i Δ t are written to the register 24 of the output block 7 ₃ and k senior bits of the value θ _i Δ t are written to the register 24 of the output block 7 ₄ . In this case, at the time of the arrival of the oldest (significant) digit of the value P _i Δ t- θ _i Δ t (in Fig. 10 5k clock cycle), a single control signal f is supplied to the control input 27 _{4 of the} logical block 26 of the output block 7 ₃

3, under which the value of the sign digit of the number P _i Δt-θ _i Δ t is recorded in the trigger 29 of the logical block 26 of the output block 7 ₃ . After that, the logical block 26 of the output block 7 ₃ is configured to implement the function y _i = max {0, P _i } (the operation of block 26 when implementing this function is described above). As a result, in this mode, the device implements a dynamic adaptive algorithm for the input and output of a neuron, which has the following form:
ΔP _i = -α _{i, 1} P _i-1 Δt +

_{X i, j · Δt · γ} ij
Δ θ _i = - α _{i, 2} θ _i- 1Δ t- θ * Δ t- α _{i, 3} P _i-1 Δ t-
- α _{i, 4} y _{out i-1} Δ t;
y _outin Δ t = max {0, (P _i Δ t- θ _i Δ t)}.

In the next 5k clock cycles, the operation of the device is completely repeated in accordance with the timing diagram of FIG. 10. If it is necessary to implement a model of a dynamic adaptive input neuron, it is sufficient to set the value of α _{i, 4} = 0, and for a model of a dynamic adaptive output neuron, it is necessary to set α _{i, 3} = 0.

X_i,jγ_i,j, которая является пространственной суммой или скалярным произведением векторов

и

. В тоже время при наличии управляющих сигналов (как это было показано на временных диаграммах фиг.8 и 10) 27₁ выходного блока 7₁, можно получить на выходе 9₁ или 10₁ k-разрядный код числа

X_i,jγ_i,j. Возможность получения скалярного произведения в виде k-разрядного и 2k-разрядного двоичного кода позволяет реализовать указанную операцию с требуемой точностью.Operation mode 5: a spatial adder with n inputs and a scalar product calculator of n-component vectors. To implement this mode, adders 6 ₁ , ..., 6 _{n / m} are combined into one common adder with n inputs. For this purpose, in the switch 12, a system of communication channels is implemented in which the output 8 _l (l = n / m, ..., 2) of each l-th output unit 7 _{l is} connected to one of the inputs 13 _l-1,1,. .., 13 _l-1 , m of the previous output block 7 _l-1 , and the output of the last output block 7 _{2 is} connected to any of the inputs 13 _1,1,. . . , 13 _{1, m of the} output block 7 ₁ . As a result, at the output 8 _{1 of the} output block 7 _1, one can obtain a 2k-bit binary code of the quantity

X _{i, j} γ _{i, j} , which is the spatial sum or scalar product of vectors

and

. At the same time, in the presence of control signals (as was shown in the time diagrams of Figs. 8 and 10) 27 _{1 of the} output block 7 ₁ , one can get the output _{1 1} or 10 ₁ k-bit code of the number

X _{i, j} γ _{i, j} . The ability to obtain a scalar product in the form of k-bit and 2k-bit binary code allows you to implement the specified operation with the required accuracy.

Operating mode 6: n / m digital integrators. When this mode is implemented, there are no communication between the device blocks, therefore, zero switching codes are stored in the registers of the addressing block 17, which are automatically generated at the initial reset of all device registers to the zero state. Logic blocks 26 of all output blocks 7 ₁ , ..., 7 _{n / m are} switched off by supplying zero potentials to their control inputs 27 ₅ , 27 ₆ . After that, to the registers 18 _{lm + 1} (l = 0,1, ..., n / m-1) through the installation inputs 4 _{lm + 1} (l = 0,1, ..., n / m-1) of the block 1 changes in the synaptic weights are recorded initial values of the integrand functions Y _{0, l} (l = 0,1, .., n / m-1). The operation of the device in this mode is carried out in accordance with the time chart in Fig.11. During the first k clock cycles, the main information inputs 2 _{lm + 1 of the} device receive k-bit binary codes of the independent variable Δ t, which are written to the registers of multipliers 20 _{lm + 1 of} block 1 of the synaptic balance change, and to the additional information inputs 3 _{lm + 1} devices receive k-bit increments of the integrands Δ Y _{i, l} , which are summed in the adders 19 _{lm + 1} with the initial values of these functions (stored in the registers 18 _{lm + 1} , and the obtained current values of the integrands Y _{i, l} = Y _{i- 1, l + Y i, l (} l = 0,1, ..., n / m- 1) recording vayutsya registers 18 _{lm + 1} (Figures 1 and 2). At the same time the output of the registers 24 7 units _1,. .., 7 _{n / m} via the outputs 10 _1, ..., 10 _{n / m} is read increment of the integrals Δ P _{i-1, l} obtained at the previous (i-1) step 1. Over the next 2k clock cycles, the multipliers 20 _{lm + 1 of the} current values of the integrands Y _{i, l} are multiplied by the independent variable Δ t and the obtained works pass through adders 21 ₁ , 6 ₁ , ..., 21 _{n / m} , 6 _{n / m} . As a result, at the outputs of adders 6 ₁ , ..., 6 _{n / m} , 2k-bit products Δ P _{i, l} = Y _{i-1, l} + Y _{i, l} , (l = 0,1, ..., n / m-1), which are the values of the increment of the integrals obtained in this ith step. In this case (Fig. 11), under the action of the control signals f ₂₇₂ , 7 _{n / m} , k low order bits of the numbers Δ P _{i, l are} written into the registers 25 of the output blocks 7 ₁ , ..., 7 _{n / m} , and under the action of the control the signals f ₂₇₁ received at the control inputs 27 _{1 of the} output blocks 7 ₁ , ..., 7 _{n / m} , k high-order bits of the numbers Δ P _{i, l are} written into the registers 24 of the output blocks 7 ₁ , ..., 7 _{n / m} . Upon receipt of new values of the input signals, the above procedure is completely repeated.

 The technical and economic efficiency of the proposed technical solution in comparison with the prototype consists in a significant expansion of its functional capabilities (the possibility of modeling by restructuring the structure: formal-logical, gradual summing, dynamic adaptive with adaptation either by input, or by output, or by input and by output, dynamic non-adaptive neurons, spatial adder, calculator of scalar products of vectors, digital integrators) while simplifying, which allows you to implement devices on a single chip LSI already with the current state of domestic microelectronic technology.

Claims (2)

 1. DEVICE FOR MODELING A NEURON, containing a synaptic balance change unit, the outputs of which are connected to the inputs of the group adders, an addressing unit, the outputs of which are connected to the inputs of the switching unit, the outputs of which are connected to the inputs of the synaptic balance change unit, characterized in that a group is entered into it shapers of directions of connections, and the outputs of the adders of the group are connected to the inputs of the shapers of directions of connections of the group, the outputs of which are connected to the inputs of the corresponding adders of the group and block mutations.  2. The device according to claim 1, characterized in that the generator of directions of communications contains two elements And, two shift registers, a logical switch, the output of the first element And connected to the inputs of the first shift register and logical switch, the output of the second element And with the input of the second shift register, the output of the first shift register - with the input of the logical switch, the inputs of the shaper - with the inputs of the first and second elements And and the logical switch, the outputs of the first element And, the first and second shift registers and the logical switch torus.

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