CN111563599A - Quantum line decomposition method and device, storage medium and electronic device - Google Patents

Quantum line decomposition method and device, storage medium and electronic device Download PDF

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CN111563599A
CN111563599A CN202010361361.4A CN202010361361A CN111563599A CN 111563599 A CN111563599 A CN 111563599A CN 202010361361 A CN202010361361 A CN 202010361361A CN 111563599 A CN111563599 A CN 111563599A
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俞磊
窦猛汉
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Origin Quantum Computing Technology Co Ltd
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Abstract

The invention discloses a quantum line decomposition method, a quantum line decomposition device, a storage medium and an electronic device, wherein the method comprises the following steps: acquiring a unitary matrix U corresponding to the quantum circuit; wherein the order number N of the unitary matrix is 2nThe n is the total number of quantum bits contained in the quantum wire; decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein, satisfy Ur…Ui…U1U＝INSaid UiI is more than or equal to 1 and is more than or equal to r, the unitary matrix corresponding to the ith single quantum logic gate carrying the controlled information
Figure DDA0002475182660000011
Said INIs an N-order identity matrix; outputting a quantum wire containing the r single quantum logic gates carrying the controlled information. By utilizing the embodiment of the invention, the calculation amount of the quantum circuit can be reduced, the simulation efficiency of the quantum circuit is improved, and the occupation of hardware resources is reduced.

Description

Quantum line decomposition method and device, storage medium and electronic device
Technical Field
The invention belongs to the technical field of quantum computing, and particularly relates to a quantum line decomposition method, a quantum line decomposition device, a storage medium and an electronic device.
Background
Quantum computers are physical devices that perform high-speed mathematical and logical operations, store and process quantum information in compliance with the laws of quantum mechanics. When a device processes and calculates quantum information and runs quantum algorithms, the device is a quantum computer. Quantum computers are a key technology under study because they have the ability to handle mathematical problems more efficiently than ordinary computers, for example, they can speed up the time to break RSA keys from hundreds of years to hours.
The quantum computation simulation is a simulation computation which simulates and follows the law of quantum mechanics by means of numerical computation and computer science, and is used as a simulation program which describes the space-time evolution of quantum states by utilizing the high-speed computing capability of a computer according to the basic law of quantum bits of the quantum mechanics.
At present, algorithms for quantum computing are typically represented by quantum wires, which include quantum logic gate operations. Generally, a continuous quantum wire usually includes tens of hundreds or even thousands of quantum logic gate operations, and the larger the number of quantum logic gates or the number of quantum bits operated by the quantum logic gates, the more complicated the calculation process, resulting in lower simulation efficiency of the quantum wire and more occupation of hardware resources.
Disclosure of Invention
The invention aims to provide a quantum line decomposition method, a quantum line decomposition device, a storage medium and an electronic device, which can solve the defects in the prior art, reduce the calculation amount of a quantum line, improve the simulation efficiency of the quantum line and reduce the occupation of hardware resources.
One embodiment of the present application provides a quantum line decomposition method, including:
acquiring a unitary matrix U corresponding to the quantum circuit; wherein the order number N of the unitary matrix is 2nThe n is the total number of quantum bits contained in the quantum wire;
decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein, satisfy Ur…Ui…U1U＝INSaid UiI is more than or equal to 1 and is more than or equal to r, the unitary matrix corresponding to the ith single quantum logic gate carrying the controlled information
Figure BDA0002475182640000021
Said INIs an N-order identity matrix;
outputting a quantum wire containing the r single quantum logic gates carrying the controlled information.
Optionally, decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information includes:
determining the sequence of non-diagonal elements to be set to 0 below the diagonal elements in the unitary matrix U;
constructing an N-order unitary matrix U of a specific quantum logic gate for the ith off-diagonal element in the orderingiTo make the matrix Ui…U1Setting the element at the same position as the non-diagonal element in the U as 0, and not changing the non-diagonal element with 0;
the specific quantum logic gate comprises a single quantum logic gate for operating one bit, the single quantum logic gate carries controlled information controlled by other bits, and i is more than or equal to 1 and less than or equal to r; when the i is 1, the unitary matrix of the single quantum logic gate is determined by elements of a unitary matrix U corresponding to the quantum circuit; when 1 is<When i is less than or equal to r, the unitary matrix of the single quantum logic gate is composed of a matrix Ui-1…U1Determining elements of U; and when the ith off-diagonal element is ordered to be the last of the columns, simultaneously enabling the matrix Ui…U1The diagonal element in the same column of U is set to 1.
Optionally, the determining the ordering of the non-diagonal elements to be set to 0 below the diagonal element in the unitary matrix U includes:
when n is 1, ordering the off-diagonal elements below the diagonal elements in the unitary matrix U and to be set to 0 as (2, 1); wherein the (2,1) represents an off-diagonal element with coordinates of row 2, column 1;
when n is greater than 1, determining a first column sequence of non-diagonal elements to be set to 0 below diagonal elements in the unitary matrix U corresponding to the n-bit quantum lines according to a first column sequence of the unitary matrix corresponding to the (n-1) bit quantum lines; wherein the ordering of the off-diagonal elements of coordinates (N/2+1,1) in the first column is located at the last of the first column;
respectively determining the ordering of off-diagonal elements to be set to 0 below diagonal elements in the 2 nd to the N/2 nd columns corresponding to the N-bit quantum lines based on the first column ordering corresponding to the N-bit quantum lines;
and correspondingly determining the sequencing of the non-diagonal elements to be set to 0 under the diagonal elements in the (N/2+1) th to the N (N) th columns corresponding to the N-bit quantum lines according to the sequencing of the non-diagonal elements to be set to 0 under the diagonal elements in the unitary matrix corresponding to the (N-1) bit quantum lines.
Optionally, the representation form of the single quantum logic gate carrying the controlled information includes:
{Cn…Cm…C1wherein, the CmRepresents 0,1, or a single quantum logic gate V, said m representing a qubit, m ∈ [1, n]And, has and only one CmRepresenting a single quantum logic gate V, the unitary matrix of which is determined by the unitary matrix U;
when C is presentmWhen the quantum state of the qubit of the bit is 0 state, the single quantum logic gate V is executed before the quantum wire runs to the single quantum logic gate V;
when C is presentmWhen the value is 1, the quantum circuit executes the single quantum logic gate V when the quantum state of the quantum bit of the bit is 1 state before running to the single quantum logic gate V;
when C is presentmAnd is, before the quantum wire runs to the single quantum logic gate V, when the quantum state of the quantum bit of the bit is an arbitrary state, the single quantum logic gate V is executed.
Another embodiment of the present application provides a quantum line decomposition device, including:
the acquisition module is used for acquiring a unitary matrix U corresponding to the quantum circuit; wherein the order number N of the unitary matrix is 2nThe n is the total number of quantum bits contained in the quantum wire;
the decomposition module is used for decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein, satisfy Ur…Ui…U1U＝INSaid UiI is more than or equal to 1 and is more than or equal to r, the unitary matrix corresponding to the ith single quantum logic gate carrying the controlled information
Figure BDA0002475182640000031
Said INIs an N-order identity matrix;
and the output module is used for outputting the quantum wires containing the r single quantum logic gates carrying the controlled information.
Optionally, the decomposition module includes:
a determining unit, configured to determine an ordering of non-diagonal elements to be set to 0 below diagonal elements in the unitary matrix U;
a construction unit for constructing an N-order unitary matrix U of a specific quantum logic gate for the ith off-diagonal element in the orderingiTo make the matrix Ui…U1Setting the element at the same position as the non-diagonal element in the U as 0, and not changing the non-diagonal element with 0;
the specific quantum logic gate comprises a single quantum logic gate for operating one bit, the single quantum logic gate carries controlled information controlled by other bits, and i is more than or equal to 1 and less than or equal to r; when the i is 1, the unitary matrix of the single quantum logic gate is determined by elements of a unitary matrix U corresponding to the quantum circuit; when 1 is<When i is less than or equal to r, the unitary matrix of the single quantum logic gate is composed of a matrix Ui-1…U1Determining elements of U; and when the ith off-diagonal element is ordered to be the last of the columns, simultaneously enabling the matrix Ui…U1The diagonal element in the same column of U is set to 1.
Optionally, the determining unit is specifically configured to:
when n is 1, ordering the off-diagonal elements below the diagonal elements in the unitary matrix U and to be set to 0 as (2, 1); wherein the (2,1) represents an off-diagonal element with coordinates of row 2, column 1;
when n is greater than 1, determining a first column sequence of non-diagonal elements to be set to 0 below diagonal elements in the unitary matrix U corresponding to the n-bit quantum lines according to a first column sequence of the unitary matrix corresponding to the (n-1) bit quantum lines; wherein the ordering of the off-diagonal elements of coordinates (N/2+1,1) in the first column is located at the last of the first column;
respectively determining the ordering of off-diagonal elements to be set to 0 below diagonal elements in the 2 nd to the N/2 nd columns corresponding to the N-bit quantum lines based on the first column ordering corresponding to the N-bit quantum lines;
and correspondingly determining the sequencing of the non-diagonal elements to be set to 0 under the diagonal elements in the (N/2+1) th to the N (N) th columns corresponding to the N-bit quantum lines according to the sequencing of the non-diagonal elements to be set to 0 under the diagonal elements in the unitary matrix corresponding to the (N-1) bit quantum lines.
Optionally, the representation form of the single quantum logic gate carrying the controlled information includes:
{Cn…Cm…C1wherein, the CmRepresents 0,1, or a single quantum logic gate V, said m representing a qubit, m ∈ [1, n]And, has and only one CmRepresenting a single quantum logic gate V, the unitary matrix of which is determined by the unitary matrix U;
when C is presentmWhen the quantum state of the qubit of the bit is 0 state, the single quantum logic gate V is executed before the quantum wire runs to the single quantum logic gate V;
when C is presentmWhen the value is 1, the quantum circuit executes the single quantum logic gate V when the quantum state of the quantum bit of the bit is 1 state before running to the single quantum logic gate V;
when C is presentmAnd is, before the quantum wire runs to the single quantum logic gate V, when the quantum state of the quantum bit of the bit is an arbitrary state, the single quantum logic gate V is executed.
Another embodiment of the application provides a storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the method of any of the above when executed.
Another embodiment of the present application provides an electronic device comprising a memory having a computer program stored therein and a processor configured to execute the computer program to perform the method of any one of the above.
Compared with the prior artCompared with the prior art, the quantum line decomposition method provided by the invention firstly acquires the unitary matrix U corresponding to the quantum line, wherein the order number N of the unitary matrix is 2nN is the total number of qubits contained in the quantum wire; decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein, satisfy Ur…Ui…U1U＝IN，UiRepresenting the unitary matrix corresponding to the ith single quantum logic gate carrying the controlled information, i is more than or equal to 1 and less than or equal to r,
Figure BDA0002475182640000051
INis an N-order identity matrix; finally, a quantum wire containing r single quantum logic gates carrying the controlled information is output. The quantum logic gates in the output quantum circuit are limited in number, and the multi-bit quantum logic gates with complex unitary matrix form are eliminated, so that the quantum logic gate form is simplified, the calculation amount can be reduced, the simulation efficiency of the quantum circuit is improved, and the occupation of hardware resources is reduced.
Drawings
Fig. 1 is a block diagram of a hardware structure of a computer terminal of a quantum circuit decomposition method according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a quantum line decomposition method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating the division of the execution timings of quantum lines according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a quantum circuit according to an embodiment of the present invention;
FIG. 5 is a diagram of a specific quantum logic gate in a quantum wire according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a quantum line decomposition device according to an embodiment of the present invention.
Detailed Description
The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
The embodiment of the invention firstly provides a quantum circuit decomposition method, which can be applied to electronic equipment, such as a computer terminal, in particular to a common computer, a quantum computer and the like.
This will be described in detail below by way of example as it would run on a computer terminal. Fig. 1 is a block diagram of a hardware structure of a computer terminal of a quantum line decomposition method according to an embodiment of the present invention. As shown in fig. 1, the computer terminal 10 may include one or more (only one shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, and optionally may also include a transmission device 106 for communication functions and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration and is not intended to limit the structure of the computer terminal. For example, the computer terminal 10 may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum computing simulation method in the embodiment of the present application, and the processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, so as to implement the above-mentioned method. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the computer terminal 10 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal 10. In one example, the transmission device 106 includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission device 106 can be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.
It should be noted that a true quantum computer is a hybrid structure, which includes two major components: one part is a classic computer which is responsible for executing classic calculation and control; the other part is quantum equipment which is responsible for running a quantum program to further realize quantum computation. The quantum program is a string of instruction sequences which can run on a quantum computer and are written by a quantum language such as a Qrun language, so that the support of the operation of the quantum logic gate is realized, and the quantum computation is finally realized. In particular, a quantum program is a sequence of instructions that operate quantum logic gates in a time sequence.
In practical applications, due to the limited development of quantum device hardware, quantum computation simulation is usually required to verify quantum algorithms, quantum applications, and the like. The quantum computing simulation is a process of realizing the simulation operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to build quantum programs for a particular problem. The quantum program referred in the embodiment of the invention is a program written in a classical language for representing quantum bits and evolution thereof, wherein the quantum bits, quantum logic gates and the like related to quantum computation are all represented by corresponding classical codes.
A quantum circuit, which is an embodiment of a quantum program and also a weighing sub-logic circuit, is the most common general quantum computation model, and represents a circuit that operates on a quantum bit under an abstract concept, and the circuit includes the quantum bit, a circuit (timeline), and various quantum logic gates, and finally, a result is often read through a quantum measurement operation.
Unlike conventional circuits that are connected by metal lines to pass either voltage or current signals, in quantum circuits, the lines can be viewed as being connected by time, i.e., the state of a qubit evolves naturally over time, in the process being operated on as indicated by the hamiltonian until a logic gate is encountered.
The quantum program refers to the total quantum circuit, wherein the total number of the quantum bits in the total quantum circuit is the same as the total number of the quantum bits of the quantum program. It can be understood that: a quantum program may consist of quantum wires, measurement operations for quantum bits in the quantum wires, registers to hold measurement results, and control flow nodes (jump instructions), and a quantum wire may contain tens to hundreds or even thousands of quantum logic gate operations. The execution process of the quantum program is a process executed for all the quantum logic gates according to a certain time sequence. It should be noted that timing is the time sequence in which the single quantum logic gate is executed.
It should be noted that in the classical calculation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved through the combination of the logic gates. Similarly, the way qubits are handled is quantum logic gates. The quantum state can be evolved by using quantum logic gates, which are the basis for forming quantum circuits, including single-bit quantum logic gates, such as Hadamard gates (H gates, Hadamard gates), pauli-X gates (X gates), pauli-Y gates (Y gates), pauli-Z gates (Z gates), RX gates, RY gates, RZ gates, and the like; multi-bit quantum logic gates such as CNOT gates, CR gates, isswap gates, Toffoli gates, etc. Quantum logic gates are typically represented using unitary matrices, which are not only matrix-form but also an operation and transformation. The function of a general quantum logic gate on a quantum state is calculated by multiplying a unitary matrix by a matrix corresponding to a quantum state right vector.
Referring to fig. 2, fig. 2 is a schematic flowchart of a quantum circuit decomposition method according to an embodiment of the present invention, where the method may include:
s201, acquiring a unitary matrix U corresponding to a quantum circuit; wherein the order number N of the unitary matrix is 2nThe n is the total number of quantum bits contained in the quantum wire;
specifically, for a quantum wire, the execution timing can be divided for the quantum logic gates included in the quantum wire; and calculating the unitary matrix U corresponding to the quantum circuit according to each execution time sequence and the unitary matrix information corresponding to each quantum logic gate.
In practical application, for each execution sequence, tensor product operation is carried out on unitary matrixes corresponding to all quantum logic gates in the execution sequence according to the numbering sequence of quantum bits, matrix multiplication is carried out on all matrixes obtained by the tensor product operation according to the sequence before and after the execution sequence, and finally unitary matrixes U corresponding to the quantum circuits are obtained. The tensor product is an operation between two matrices of arbitrary size, and is expressed as
Figure BDA0002475182640000084
Also known as direct product, kronecker product, or tensor multiplication. The matrix belongs to a second-order tensor, and a tensor product can play a role in dimension expansion.
And if the specific quantum circuit has an empty quantum logic gate for short, in order to keep the dimension after dimension expansion the same, the unitary matrix corresponding to the empty quantum logic gate is set as a unit matrix I of 2 x 2. The unitary matrix of the existing single-quantum logic gate is 2 × 2, the unitary matrix of the two-quantum logic gate is 4 × 4, for example, the unitary matrix of the H gate is
Figure BDA0002475182640000081
Unitary matrix of X gate is
Figure BDA0002475182640000082
Unitary matrix of CNOT gate is
Figure BDA0002475182640000083
And so on.
And multiplying each matrix obtained by tensor product operation according to the sequence of execution time sequence to obtain the matrix corresponding to the specific quantity sub-circuit.
Taking fig. 3 as an example, fig. 3 is a schematic diagram illustrating the division of the execution timing of the quantum circuit according to the embodiment of the present invention, and the dotted line represents the division of the execution timing. In sequence 1, q3 has no quantum logicThe gate operation, which is actually performed in the program, is an empty gate operation, which can be regarded as a single quantum logic gate of an identity matrix with a unitary matrix of 2 x 2. According to the sequence of bit numbers from low order to high order, multiplying the unitary matrix right (tensor multiplication) in turn to obtain 2n*2nN is the number of quantum bits. In FIG. 3, the numbering sequence of the qubits is 0-4, and n is 5. Similarly, the other 5 time sequences also each result in a matrix of 32 × 32.
Then, matrix multiplication is carried out on the 6 matrixes in sequence according to the corresponding time sequence of the 6 matrixes, and finally a 32-by-32 matrix is obtained, namely the matrix corresponding to the specific quantum circuit. Matrix multiplication here refers to the general matrix product, namely: let a be a matrix of h × p and B be a matrix of p × q, then the matrix C called h × q is the product of the matrices a and B, denoted as C ═ AB, where the i-th row and j-th column elements in the matrix C can be represented as:
Figure BDA0002475182640000091
the unitary matrix of each quantum logic gate in each execution time sequence is subjected to tensor product operation for dimension expansion, so that the matrixes corresponding to each execution time sequence obtained by tensor product operation are in the same dimension, and the accuracy of the space-time evolution of the quantum state of the quantum bit subjected to matrix multiplication and representation on each matrix in the next step is ensured.
Before the division execution sequence, if a part of quantum lines in the transposed conjugate dagger state exists in the quantum lines, at least one quantum logic gate included in the part of quantum lines is reversely ordered, and the transposed conjugate matrix of the unitary matrix of the quantum logic gate is obtained as new unitary matrix information. Wherein a partial quantum wire may comprise a continuous quantum logic gate or gates, or even a whole quantum wire.
For example, a quantum wire segment as shown in fig. 3 includes: h q0, H q1, RY q2, H q4, RX q0, X q1, CNOTq4q3, Z q0, H q1, CNOT q2q3, H q4, CNOT q1q0, H q2, CNOT q3q4, RZ q3, Y q4 and RX q4, wherein q0, q1, q2, q3 and q4 refer to quantum bits with bits from 0 to 4.
Assuming that the partial quantum wire H q0, H q1, RY q2, H q4, RX q0, X q1, CNOT q4q3, Z q0 is at dagger, the logic gates in the partial quantum wire are sorted in reverse: z q0, CNOT q4q3, X q1, RX q0, H q4, RYq2, H q1, H q0, and transpose conjugate operation is performed on the unitary matrix of each logic gate to obtain a new transpose conjugate matrix, and finally the quantum wire can be expressed as: generator q0, CNOT. generator q4q3, x.generator q1, rx.generator q0, h.generator q4, ry.generator q2, h.generator q1, h.generator q0, H q1, CNOT q2q3, H q4, CNOTq1q0, H q2, CNOT q3q4, RZ q3, Y q4, RX q 4. The generator is only a formal expression, and represents a Z gate in the generator, and a unitary matrix of the generator is a transposed conjugate matrix of an original unitary matrix of the Z gate, and the rest is the same.
For another example, a quantum circuit diagram is shown in fig. 4, after time sequence division:
a first time sequence: h q0, CNOT q2q 1;
and a second time sequence: x q2 are provided.
Calculating a unitary matrix within a first timing sequence:
Figure BDA0002475182640000101
obtaining:
Figure BDA0002475182640000102
calculating a unitary matrix within a second timing sequence:
Figure BDA0002475182640000103
then, matrix multiplication is performed:
Figure BDA0002475182640000104
obtaining the following 8-order matrix, namely the unitary matrix corresponding to the quantum circuit:
Figure BDA0002475182640000105
s202, decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein, satisfy Ur…Ui…U1U＝INSaid UiI is more than or equal to 1 and is more than or equal to r, the unitary matrix corresponding to the ith single quantum logic gate carrying the controlled information
Figure BDA0002475182640000111
Said INIs an N-order identity matrix;
specifically, the method may include:
s2021, determining the ordering of the off-diagonal elements to be set to 0 below the diagonal elements in the unitary matrix U;
in one implementation, the ordering of the non-diagonal elements to be set to 0 below the diagonal elements in the unitary matrix U may be: the first column is arranged by column number to the last column, each column of non-diagonal elements is arranged from top to bottom by row number, and the sequence of a 4-order unitary matrix for a two-bit quantum line is shown in table 1.
TABLE 1 element ordering of unitary matrices for two-bit quantum wires
00 01 10 11
00 (1,1)
01 (2,1)1 (2,2)
10 (3,1)2 (3,2)1 (3,3)
11 (4,1)3 (4,2)2 (4,3)1 (4,4)
Wherein 00, 01, 10 and 11 represent binary representations corresponding to rows or columns, and binary bits correspond to qubits one by one; (1,1), (2,2), (3,3), (4,4) denote diagonal elements to which the coordinates correspond, such as (2,1), (3,1), (4,1) denote off-diagonal elements to which the coordinates correspond, and the numbers 1, 2, 3 after the parenthesis denote the corresponding ordering.
It should be emphasized that, since the matrix form of the quantum logic gate is unitary matrix, that is, the product of the unitary matrix and the transpose conjugate of the unitary matrix is a unit matrix, and the product between the unitary matrices is also a unitary matrix, it is only necessary to pay attention to the operation of setting 0 of the off-diagonal elements below the diagonal of the matrix, and the off-diagonal elements in the same column above the diagonal elements are set to 0 while the diagonal elements are set to 1, which is determined by the characteristics of the unitary matrix and will not be described again. Similarly, a 0 operation is also possible that only focuses on off-diagonal elements above the matrix diagonal.
Preferably, to facilitate subsequent matrix construction, in another implementation, the ordering of the non-diagonal elements to be set to 0 below the diagonal elements in the unitary matrix U may be:
when n is 1, ordering the off-diagonal elements below the diagonal elements in the unitary matrix U and to be set to 0 as (2, 1); wherein the (2,1) represents an off-diagonal element with coordinates of row 2, column 1;
when n is greater than 1, determining a first column sequence of non-diagonal elements to be set to 0 below diagonal elements in the unitary matrix U corresponding to the n-bit quantum lines according to a first column sequence of the unitary matrix corresponding to the (n-1) bit quantum lines; wherein the ordering of the off-diagonal elements of coordinates (N/2+1,1) in the first column is located at the last of the first column;
respectively determining the ordering of off-diagonal elements to be set to 0 below diagonal elements in the 2 nd to the N/2 nd columns corresponding to the N-bit quantum lines based on the first column ordering corresponding to the N-bit quantum lines;
and correspondingly determining the sequencing of the non-diagonal elements to be set to 0 under the diagonal elements in the (N/2+1) th to the N (N) th columns corresponding to the N-bit quantum lines according to the sequencing of the non-diagonal elements to be set to 0 under the diagonal elements in the unitary matrix corresponding to the (N-1) bit quantum lines.
Illustratively, for a unitary matrix of order 2 of a 1-bit quantum wire, there is only one element (2,1) below the diagonal elements, so the off-diagonal elements ordered with and only in the first column are: (2,1).
For a 4-order unitary matrix of a 2-bit quantum wire, the first column ordering adopts a recursive idea, that is, referring to the first column ordering of a 1-bit quantum wire, and the non-diagonal element of the (N/2+1) -th row and the 1-st column is arranged at the last of the columns, that is, (2,1) is arranged at the 1 st and (3,1) is arranged at the last 1, so as to determine that (4,1) is arranged at the 2 nd, and finally the 1 st column ordering can be obtained as follows: (2,1), (4,1), (3, 1).
For an 8-order unitary matrix of a 3-bit quantum wire, the first column ordering refers to the first column ordering of a 2-bit quantum wire, i.e., (2,1), (4,1), (3,1) for the 1 st to 3 rd, and (5,1) is located in the last 1, and the remaining (6,1), (7,1), (8,1) refers to the orderings of (2,1), (3,1), (4,1) as (6,1), (8,1), (7,1), and the final 1 st column ordering is: (2,1), (4,1), (3,1), (6,1), (8,1), (7,1) and (5, 1).
By analogy, the 1 st column ordering of a 4-bit quantum wire refers to the 1 st column ordering of a 3-bit quantum wire, which is: (2,1), (4,1), (3,1), (6,1), (8,1), (7,1), (5,1), (10,1), (12,1), (11,1), (14,1), (16,1), (15,1), (13,1) and (9,1), and the 1 st column sorting of more bit quantum wires can be obtained in the same way.
Then, continuing with the example of a 4 th unitary matrix of 2-bit quantum wires, the rank of column 2 is determined:
obtaining the ordering of the elements (3,1), (4,1) in the first column in the same row as the 2 nd column (3,2), (4,2), i.e., (4,1), (3,1), the binary representations of the corresponding rows are 11 and 00, and the exclusive or operation is performed with the binary representation 01 corresponding to the 2 nd column respectively:
11⊕01＝10＝(3,2)
10⊕01＝11＝(4,2)
it can be seen that the 2 nd column ordering of the 4 th unitary matrix of the 2-bit quantum line is: (3,2) and (4, 2).
Determining the rank of column 3 through column 4: unitary matrix ordering for an analog 1-bit quantum line is: (4,3), the resulting ranking is shown in Table 2.
Table 2 unitary matrix ordering for another 2-bit quantum line
00 01 10 11
00 (1,1)
01 (2,1)1 (2,2)
10 (3,1)3 (3,2)1 (3,3)
11 (4,1)2 (4,2)2 (4,3)1 (4,4)
Similarly, taking 3-bit quantum wires as an example, the sequence from column 2 to column 4 is determined:
the order of the non-diagonal elements in column 1 in the same row as column 2 is: (4,1), (3,1), (6,1), (8,1), (7,1), (5,1), the binary of the corresponding row is exclusive-ored with the binary of the 2 nd column, the ordering of (3,2), (4,2) is not changed by the 2-bit quantum circuit, and the exclusive-or operation can be omitted here, that is:
101⊕001＝100＝(5,2)
111⊕001＝110＝(7,2)
110⊕001＝111＝(8,2)
100⊕001＝101＝(6,2)
it can be seen that the 2 nd column ordering of the 8 th unitary matrix for a 3-bit quantum line is: (3,2), (4,2), (5,2), (7,2), (8,2), (6, 2);
the order of the non-diagonal elements in column 1 in the same row as column 3 is: (4,1), (6,1), (8,1), (7,1), (5,1), the binary of the corresponding row is exclusive-ored with the binary of the 3 rd column, the ordering of (4,3) is not changed by the 2-bit quantum circuit, and the exclusive-or operation can be omitted here, that is:
101⊕010＝110＝(8,3)
111⊕010＝101＝(6,3)
110⊕010＝100＝(5,3)
100⊕010＝110＝(7,3)
it can be seen that the 3 rd column ordering of the 8 th unitary matrix for a 3-bit quantum line is: (4,3), (8,3), (6,3), (5,3), (7, 3);
the order of the non-diagonal elements in column 1 in the same row as column 4 is: (6,1), (8,1), (7,1), (5,1), the binary of the corresponding row is exclusive-ored with the binary of the 4 th column, that is:
101⊕011＝110＝(7,4)
111⊕011＝100＝(5,4)
110⊕011＝101＝(6,4)
100⊕011＝111＝(8,4)
it can be seen that the 4 th column ordering of the 8 th unitary matrix for a 3-bit quantum line is: (7,4), (5,4), (6,4), (8, 4).
Then, for the 8 th order row 5 to 8 th order of the 8 th order unitary matrix of the 3-bit quantum circuit, the sequence of the 1 st to 4 th order of the 4 th order unitary matrix of the analog 2-bit quantum circuit can be obtained:
rank 5: (6,5), (8,5), (7, 5);
rank 6: (7,6), (8, 6);
rank 7: (8, 7);
rank 8: none.
The same can determine the order of the 2 nd column to the last column of the unitary matrix for more bit quantum wires. From the above, the partial column ordering of the unitary matrix of a 3-bit quantum line is shown in table 3.
TABLE 3 partial column ordering of unitary matrices for 3-bit quantum wires
000 001 010 011 ...
000 (1,1) ...
001 (2,1)1 (2,2) ...
010 (3,1)3 (3,2)1 (3,3) ...
011 (4,1)2 (4,2)2 (4,3)1 (4,4) ...
100 (5,1)7 (5,2)3 (5,3)4 (5,4)2 ...
101 (6,1)4 (6,2)6 (6,3)3 (6,4)3 ...
110 (7,1)6 (7,2)4 (7,3)5 (7,4)1 ...
111 (8,1)5 (8,2)5 (8,3)2 (8,4)4 ...
S2022, aiming at the ith off-diagonal element in the sequence, constructing an N-order unitary matrix U of a specific quantum logic gateiTo make the matrix Ui…U1The element in U at the same position as the non-diagonal element is set to 0, and the non-diagonal element set to 0 is not changed. And when the ith off-diagonal element is ordered to be the last of the columns, simultaneously making the matrix Ui…U1The diagonal element in the same column of U is set to 1.
For the sake of easy distinction, a single quantum logic gate carrying controlled information can also be understood as a specific quantum logic gate, since its unitary matrix is no longer a 2 nd order unitary matrix of a single quantum logic gate in the ordinary sense, but is an N th order unitary matrix UiThe representation form of the specific quantum logic gate can be as follows:
{Cn…Cm…C1}
wherein, CmRepresenting 0,1, or a single quantum logic gate V, m representing a qubit, m ∈ [1, n]And, has and only one CmRepresenting a single quantum logic gate V. The single-quantum logic gate V is a single-quantum logic gate that operates one qubit in the ordinary sense, but can be additionally controlled by the remaining qubits in the qubit line. The particular quantum logic gate constructed may be different for the off-diagonal elements of the different terms to be set to 0.
When C is presentmWhen the value is 0, the quantum circuit is operated before the single quantum logic gate V (namely the logic gate V is to be executed next step), and when the quantum state of the quantum bit of the bit is judged to be 0 state, the single quantum logic gate V is executed, which is called 0 control for short;
when C is presentmWhen the value is 1, before the quantum circuit runs to the single quantum logic gate V, when the quantum state of the quantum bit of the bit is 1 state, the single quantum logic gate V is executed, which is called 1 control for short;
when C is presentmWhen the quantum state of the qubit of the bit is arbitrary, the single quantum logic gate V is executed before the quantum wire runs to the single quantum logic gate V, which is called uncontrolled for short.
For example, one particular qubit is represented by {10 × V }, meaning that the single qubit V acts on the least significant qubit, { denotes that the gate V is not controlled (uncontrolled) by the 2 nd qubit, 0 denotes that the gate V is controlled (0 controlled) by the 3 rd qubit, and 1 denotes that the gate V is controlled (1 controlled) by the 4 th qubit. It is also known that the quantum line is a 4-bit quantum line, and the unitary matrix of the particular quantum logic gate is 24The unitary matrix of order 16.
Specifically, i is a positive integer, and the value range is as follows: i is more than or equal to 1 and less than or equal to r. When i is 1, the unitary matrix of the single quantum logic gate V is determined by the elements of the unitary matrix U of the quantum circuit; when 1 is<When i is less than or equal to r, the unitary matrix of the single-quantum logic gate V consists of a matrix Ui-1…U1And determining the elements of U.
For example, for a 2-bit quantum wire, on the basis of table 2, a representation form of a specific quantum logic gate is added correspondingly, as shown in table 4, U1＝{*V}，U2＝{1V}，U3＝{V*}，U4＝{1V}，U5＝{V1}，U6＝{1V}。
TABLE 4 specific Quantum logic gates corresponding to 2-bit quantum wires
Figure BDA0002475182640000151
Figure BDA0002475182640000161
Wherein, the specific matrix form is as follows:
Figure BDA0002475182640000162
Figure BDA0002475182640000163
Figure BDA0002475182640000164
Figure BDA0002475182640000165
wherein,
Figure BDA0002475182640000166
it can be added that the matrix form of 0V and V0 for 2-bit quantum wire correlation is as follows:
Figure BDA0002475182640000167
Figure BDA0002475182640000168
a schematic diagram of a specific qubit logic gate, {0V }, {1V }, { V0}, and { V1} in a quantum circuit is shown in fig. 5, where open dots and lines to V indicate 0 control, solid dots and lines to V indicate 1 control, the upper horizontal line indicates the time line for the low qubit, and the lower horizontal line indicates the time line for the high qubit.
Assume that the unitary matrix of a 2-bit quantum wire is as follows:
Figure BDA0002475182640000171
first, u is21The off-diagonal elements of the same position are set to 0:
in the case of a 1-bit quantum wire,
Figure BDA0002475182640000172
Figure BDA0002475182640000173
v21*u11+v22*u21＝0，v11*u11+v12*u21＝1，
Figure BDA0002475182640000174
the calculation can obtain:
Figure BDA0002475182640000175
it can be seen that the element determination of V is related to the (1,1) term and the (2,1) term, and that the (2,1) term can be seen to be eliminated by the (1,1) term, so that the (2,1) term is 0 after matrix multiplication. For 2-bit quantum wires, in a similar manner, the (2,1) term is first eliminated, also with the (1,1) term, V, with each element V in V11、v12、v21、v22Determining from the (1,1) and (2,1) terms:
Figure BDA0002475182640000176
Figure BDA0002475182640000177
second, u is41The off-diagonal elements of the same position are set to 0:
eliminating the (2,1) term analogy with the (1,1) term, the left lower half, using U1The (3,1) term in U eliminates the (4,1) term, from which V is determined:
Figure BDA0002475182640000181
Figure BDA0002475182640000182
thirdly, mixing u31Co-located off-diagonal elements are set to 0, while the column diagonal elements are set to 1:
by means of U2U1The (1,1) term in U eliminates the (3,1) term, from which V is determined:
Figure BDA0002475182640000183
Figure BDA0002475182640000184
Figure BDA0002475182640000191
due to the fact that
Figure BDA0002475182640000192
And
Figure BDA0002475182640000193
the unitary matrix is a unitary matrix, the product of the unitary matrix and the transpose conjugate of the unitary matrix is a unit matrix, and the unitary matrix can be calculated by the condition:
Figure BDA0002475182640000194
by analogy, for column 2, the (3,2) and (4,2) terms are eliminated in a manner that analogizes the (4,1) and (3,1) terms, while not changing the term whose element in the first column is 0. Then, the matrix form is a form of direct summation of a second-order identity matrix and a second-order matrix, the second-order matrix can be regarded as the case of a 1-bit quantum circuit, and a specific quantum logic gate {1V } is adopted for processing, so that the first two columns with 0 set are not influenced.
For the unitary matrix of a 3-bit quantum line, for the first column, the way to eliminate the (2,1), (4,1), (3,1) entries is the same as for the 2-bit quantum line, except that the particular quantum logic gate used is different; for the lower half, the elimination of (6,1), (8,1), (7,1) terms can be analogized to elimination of (2,1), (4,1), (3,1) terms, and finally elimination of (5,1) terms with (1,1) terms. For the second column, the terms (3,2), (4,2) are eliminated in the same way as in the case of a 2-bit quantum wire, and the terms (5,2), (7,2), (8,2), (6,2) are eliminated by analogy with the elimination of the terms (6,1), (8,1), (7,1), (5, 1). The rest of the columns are the same.
More specifically, the term with element a is used to eliminate the term with element b, if the position of the term a is above the term b, then:
Figure BDA0002475182640000195
otherwise, in the case where the a term is below the b term:
Figure BDA0002475182640000201
wherein, a*、b*Represents the conjugation of a and b.
Illustratively, for a 3-bit quantum wire, on the basis of table 3, the representation corresponding to a particular quantum logic gate is shown in table 5 below:
TABLE 5 specific Quantum logic gates corresponding to 3-bit quantum wires
Figure BDA0002475182640000202
First column, (2, 1): u shape1＝{**V}；(4,1)：U2＝{*1V}；(3,1)：U3＝{*V*}；(6,1)：U4＝{1*V}；(8,1)：U5＝{*1V}；(7,1)：U6＝{1V*}；(5,1)：U7＝{V**}；
Second column, (3, 2): u shape8＝{*1V}；(4,2)：U9＝{*V1}；(5,2)：U10＝{1*V}；(7,2)：U11＝{*1V}；(8,2)：U12＝{1V*}；(6,2)：U13＝{V*1}；
Third column, (4, 3): u shape14＝{*1V}；(8,3)：U15＝{1*V}；(6,3)：U16＝{10V}；(5,3)：U17＝{1V*}；(7,3)：U18＝{V1*}；
Fourth column, (7, 4): u shape19＝{1*V}；(5,4)：U20＝{10V}；(6,4)：U21＝{1V*}；(8,4)：U22＝{V11}；
Fifth column, (6, 5): u shape23＝{1*V}；(8,5)：U24＝{11V}；(7,5)：U25＝{1V*}；
Sixth column, (7, 6): u shape26＝{11V}；(8,6)：U27＝{1V1}；
Column seven, (8, 7): u shape28-11V; the eighth column is none.
Those skilled in the art will appreciate the ordering of the off-diagonal elements to be set to 0 and the unitary matrix U of order N for a particular quantum logic gateiIs not limited to the above configuration, and specifically realizes Ur…U1U＝INThe standard is.
There are some basic rules for matrix construction. For example, 2-bit quantum lines are binary-coded (the binary representation described above) for the rows and columns of the original unitary matrix U according to the corresponding number of quantum bits, i.e. from 00 to 11, a {0V } matrix acts on the left side of the unitary matrix U of order 4, and only affects the 00 and 01 parts of U (i.e. the first two rows and the first two columns), and similarly, {1V } only affects the 10 and 11 parts of U, { V0} only affects the 00 and 10 parts of U, and { V1} only affects the 01 and 11 parts of U. For {. V } and { V } matrices, which do not contain any control, it is known from their matrix form that a left multiplication of the original matrix affects all rows and columns of the original matrix.
The construction rules for a matrix representation of a particular quantum logic gate can be summarized as follows:
first, a matrix structure corresponding to a first column of a unitary quantum wire matrix is described:
1, one-bit quantum wire:
the unitary line matrix only has one element (2,1) to be set to 0, and a specific quantum logic gate { C is constructed1It is sufficient to make { V }, U ═ IN；
2, two-bit quantum wires:
using recursive thinkingTo refer to 1-bit quantum circuit, the unitary matrix of the circuit except the last element (3,1) to be set with 0 corresponds to a specific quantum logic gate { C }n…Cm…C1}＝{C2C1}＝{C2V}；
For the upper half of the unitary matrix (2,1), the highest order qubit is set to uncontrolled, i.e. (2, 1): [ C ]2V}＝[*V}；
For the lower half (4,1), C corresponding to the lower quantum bit is determined1Whether or not it is 1, and if not 1, (4, 1): [ C ]2V } is [1V ], otherwise [ C ]2V {. V }; judging to obtain:
(4,1) for a 1-bit quantum wire (2, 1): { C2C1}＝{C2V}＝{1V}；
The last element to be set with 0 (3,1) is directly set to: { C2C1}＝{V*}；
3, three-bit quantum wires:
specific quantum logic gate of corresponding structure Cn…Cm…C1}＝{C3C2C1The upper half part of the unitary line matrix refers to 2-bit quantum lines, and the highest-order quantum bit is still set to be uncontrolled, namely { C }3C2C1}＝{*C2C1Get, get:
(2,1) for a 2-bit quantum wire (2, 1): { C3C2C1}＝{*C2C1}＝{**V}；
(4,1) for a 2-bit quantum wire (4, 1): { C3C2C1}＝{*C2C1}＝}*1V}；
(3,1) for a 2-bit quantum wire (3, 1): { C3C2C1}＝{*C2C1}＝{*V*}；
For the lower half part, except the last element (5,1) to be set with 0, the lower half part is sequentially in one-to-one correspondence with the upper half part, and C corresponding to the lower 2-bit quantum bit of the upper half part is judged2、C1If none is 1, then { C3C2C1}＝{1C2C1Else { C }3C2C1}＝{*C2C1}; judging to obtain:
(6,1) corresponding to { C3C2C1In (C) }, C2、C1C corresponding to (2,1)2、C1The same, namely x and V, and are not 1, can obtain: { C3C2C1}＝{C3*V}＝{1*V}；
In the same way, (8,1) corresponds to (4, 1): { C3C2C1}＝{C31V {. 1V }; (7,1) corresponds to (3, 1): { C3C2C1}＝{C3V*}＝{1V*}；
The last element to be set with 0 (5,1) is directly set to: { C3C2C1}＝{V**}；
By analogy, the matrix structure corresponding to the first column of the unitary matrix of the arbitrary bit quantum circuit can be realized;
second, the matrix structure corresponding to the second column to the N/2 th column of the quantum circuit unitary matrix:
1, two-bit quantum wire, n ═ 2:
column 2, column index l 2, binary 01, binary low l 11, high order l20; according to a preset inequality 2x-1<l≤2xObtaining x as 1; the lower half of the matrix corresponds to the lower half of the previous column in order, matrix C2C1The construction is as follows:
(3,2): reference to {1V } corresponding to (4, 1): if j is n and C in {1V }n,…,Cx+1If none of them is 1, then (3,2) corresponds to { C2C1C in (C) }j1 is ═ 1; if j is more than or equal to 1 and less than or equal to x, and the corresponding C in {1V }j＝l j1, then (3,2) corresponds to { C2C1C in (C) }j0; otherwise, (3,2) the corresponding CjC corresponding to {1V }jKeeping consistent; judging to obtain:
when j is 1, C is satisfiedjC corresponding to {1V }jMaintaining a consistent condition, i.e. C1＝V；
When j is 2, C is satisfiedjC corresponding to {1V }jMaintaining a consistent condition, i.e. C2＝1；
The corresponding { C of (3,2) can be obtained2C1}＝{1V}；
(4,2): it is the last element to be set with 0 in the column, and refers to { V } corresponding to the first column (3, 1): regarding any of { V } as 0, binary plus 1 operation is performed to obtain 1, and { C corresponding to (3,2) is obtained2C1}＝{V1}；
2, three-bit quantum wire, n ═ 3:
column 2, column subscript l 2, binary 001, l1＝1、l2＝0、l30; according to 2x-1<l≤2xThen, x is found to be 1, and the upper half (3,2) and (4,2) refer to two-bit quantum wires:
(3,2) corresponding to { C3C2C1In (C) }, C2C1Taking { C corresponding to (3,2) of a two-bit quantum line2C1Is {1V } same, C3Set as, namely: (3,2) corresponding to { C3C2C1}＝{*1V}；
(4,2) corresponding to { C3C2C1In (C) }, C2C1Taking { C corresponding to (4,2) of a two-bit quantum line2C1C } ═ V1} same3Set as, namely: (3,2) corresponding to { C3C2C1}＝{*V1}；
The lower half of the matrix corresponds to the lower half of the first column in order, matrix C3C2C1The construction is as follows:
(5,2): reference to {1 × V } corresponding to (6, 1): if j is n and C in {1V }n,…,Cx+1If none of them is 1, then (5,2) corresponds to { C3C2C1C in (C) }j1 is ═ 1; if j is more than or equal to 1 and less than or equal to x, and the corresponding C in {1 x V }j＝l j1, then (5,2) corresponds to { C3C2C1C in (C) }j0; otherwise, (5,2) corresponds to { C3C2C1C in (C) }jC corresponding to {1 × V }jKeeping consistent; can judgeObtaining:
when j is 1, C is satisfiedjC corresponding to {1 × V }jMaintaining a consistent condition, i.e. C1＝V；
When j is 2, C is satisfiedjC corresponding to {1 × V }jMaintaining a consistent condition, i.e. C2Is equal to;
when j is 3, C is satisfiedjC corresponding to {1 × V }jMaintaining a consistent condition, i.e. C3＝1；
The corresponding { C of (5,2) can be obtained3C2C1}＝{1*V}；
Similarly, the corresponding { C of (7,2)3C2C11V }; (8,2) corresponding to { C3C2C1}＝{1V*}；
(6,2): it is the last element to be set with 0 in the column, and refers to { V x } corresponding to the first column (5, 1): regarding any of { V } as 0, binary plus 1 operation is performed, 00 becomes 01, that is, changes to 1, and then { C } corresponding to (6,2) is obtained3C2C1}＝{V*1}；
Similarly, column 3:
the upper half part: (4,3) corresponds to {. 1V }; the lower half: (8,3) for {1 x V }, (6,3) for {10V }, and (5,3) for {1V }; the last element (7,3) to be set with 0 in the column corresponds to { V1 };
column 4 is not described in detail; it can be seen that, except for the last element to be set with 0 in each column, the matrix structure of the even column is the same as that of the previous column (odd column), and the matrix of the odd column is determined with reference to the first column;
thirdly, the matrix structure corresponding to the (N/2+1) th column to the last column of the quantum circuit unitary matrix:
referring to the upper half of the 1 st column to the N/2 nd column, the highest bit is changed to 1, and the rest is unchanged, taking the above 3-bit quantum circuit as an example, the following can be obtained:
column 5: (6,5) corresponding to (2,1), obtaining {1 x V }; (8,5) corresponding to (4,1), obtaining {11V }; (7,5) corresponding to (3,1), obtaining {1V };
column 6: (7,6) corresponding to (3,2), obtaining {11V }; (8,6) corresponds to (4,2), and {1V1} can be obtained;
column 7: (8,7) corresponding to (4,3), obtaining {11V }; column 8 none;
by analogy, matrix structures corresponding to all columns of the unitary matrix of arbitrary bit quantum lines can be realized, which is not described herein again.
In particular, the method comprises the following steps of,
Figure BDA0002475182640000241
wherein, VmEqual to:
|0><0|, if Cm＝0；|1><1|, if Cm＝1；V-I2If C ism＝V；I2If C ismIs.
And S203, outputting quantum wires containing the r single quantum logic gates carrying the controlled information.
Specifically, by Ur…U1U＝INThe following can be obtained:
Figure BDA0002475182640000242
Figure BDA0002475182640000243
is U1、UrI.e. the decomposed r single quantum logic gates (specific quantum logic gates) carrying the controlled information are in transposed conjugate dagger states.
After the matrix form of the specific quantum logic gate is determined, the specific quantum logic gate is determined (for example, the schematic diagram of fig. 5 in which the specific quantum logic gate is located in a quantum wire), according to the slave
Figure BDA0002475182640000244
In turn to
Figure BDA0002475182640000245
Constructing and outputting the decomposed, including
Figure BDA0002475182640000246
To
Figure BDA0002475182640000247
The new quantum wire of (1). Compared with the complex quantum circuit which comprises hundreds of quantum logic gates and a large number of multi-bit quantum logic gates, the structure of the new quantum circuit is greatly simplified, and the computation complexity and the resource occupation during the operation of the quantum circuit are obviously reduced.
Therefore, the quantum logic gates in the output quantum circuit are limited in number, and the multi-bit quantum logic gates with complex unitary matrix form are eliminated, so that the quantum logic gate form is simplified, the calculation amount can be reduced, the simulation efficiency of the quantum circuit is improved, and the occupation of hardware resources is reduced.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a quantum line decomposition device according to an embodiment of the present invention, which corresponds to the flow shown in fig. 2, and may include:
an obtaining module 601, configured to obtain a unitary matrix U corresponding to a quantum line; wherein the order number N of the unitary matrix is 2nThe n is the total number of quantum bits contained in the quantum wire;
a decomposition module 602, configured to decompose the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein, satisfy Ur…Ui…U1U＝INSaid UiI is more than or equal to 1 and is more than or equal to r, the unitary matrix corresponding to the ith single quantum logic gate carrying the controlled information
Figure BDA0002475182640000251
Said INIs an N-order identity matrix;
an output module 603, configured to output quantum wires including the r single quantum logic gates carrying controlled information.
Specifically, the decomposition module includes:
a determining unit, configured to determine an ordering of non-diagonal elements to be set to 0 below diagonal elements in the unitary matrix U;
a construction unit for constructing an N-order unitary matrix U of a specific quantum logic gate for the ith off-diagonal element in the orderingiTo make the matrix Ui…U1Setting the element at the same position as the non-diagonal element in the U as 0, and not changing the non-diagonal element with 0;
the specific quantum logic gate comprises a single quantum logic gate for operating one bit, the single quantum logic gate carries controlled information controlled by other bits, and i is more than or equal to 1 and less than or equal to r; when the i is 1, the unitary matrix of the single quantum logic gate is determined by elements of a unitary matrix U corresponding to the quantum circuit; when 1 is<When i is less than or equal to r, the unitary matrix of the single quantum logic gate is composed of a matrix Ui-1…U1Determining elements of U; and when the ith off-diagonal element is ordered to be the last of the columns, simultaneously enabling the matrix Ui…U1The diagonal element in the same column of U is set to 1.
Specifically, the determining unit is specifically configured to:
when n is 1, ordering the off-diagonal elements below the diagonal elements in the unitary matrix U and to be set to 0 as (2, 1); wherein the (2,1) represents an off-diagonal element with coordinates of row 2, column 1;
when n is greater than 1, determining a first column sequence of non-diagonal elements to be set to 0 below diagonal elements in the unitary matrix U corresponding to the n-bit quantum lines according to a first column sequence of the unitary matrix corresponding to the (n-1) bit quantum lines; wherein the ordering of the off-diagonal elements of coordinates (N/2+1,1) in the first column is located at the last of the first column;
respectively determining the ordering of off-diagonal elements to be set to 0 below diagonal elements in the 2 nd to the N/2 nd columns corresponding to the N-bit quantum lines based on the first column ordering corresponding to the N-bit quantum lines;
and correspondingly determining the sequencing of the non-diagonal elements to be set to 0 under the diagonal elements in the (N/2+1) th to the N (N) th columns corresponding to the N-bit quantum lines according to the sequencing of the non-diagonal elements to be set to 0 under the diagonal elements in the unitary matrix corresponding to the (N-1) bit quantum lines.
Specifically, the representation form of the single quantum logic gate carrying the controlled information includes:
{Cn…Cm…C1wherein, the CmRepresents 0,1, or a single quantum logic gate V, said m representing a qubit, m ∈ [1, n]And, has and only one CmRepresenting a single quantum logic gate V, the unitary matrix of which is determined by the unitary matrix U;
when C is presentmWhen the quantum state of the qubit of the bit is 0 state, the single quantum logic gate V is executed before the quantum wire runs to the single quantum logic gate V;
when C is presentmWhen the value is 1, the quantum circuit executes the single quantum logic gate V when the quantum state of the quantum bit of the bit is 1 state before running to the single quantum logic gate V;
when C is presentmAnd is, before the quantum wire runs to the single quantum logic gate V, when the quantum state of the quantum bit of the bit is an arbitrary state, the single quantum logic gate V is executed.
Therefore, the quantum logic gates in the output quantum circuit are limited in number, and the multi-bit quantum logic gates with complex unitary matrix form are eliminated, so that the quantum logic gate form is simplified, the calculation amount can be reduced, the simulation efficiency of the quantum circuit is improved, and the occupation of hardware resources is reduced.
An embodiment of the present invention further provides a storage medium, where a computer program is stored in the storage medium, where the computer program is configured to, when executed, perform the steps in any one of the above method embodiments.
Specifically, in the present embodiment, the storage medium may be configured to store a computer program for executing the steps of:
s1, acquiring unitary matrix U corresponding to the quantum circuit; wherein the order number N of the unitary matrix is 2nThe n is the total number of quantum bits contained in the quantum wire;
s2, decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein, satisfy Ur…Ui…U1U＝INSaid UiFor the ith single quantum logic gate carrying controlled informationI is more than or equal to 1 and is less than or equal to r of the corresponding unitary matrix, wherein
Figure BDA0002475182640000261
Said INIs an N-order identity matrix;
and S3, outputting quantum wires containing the r single quantum logic gates carrying the controlled information.
Specifically, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Therefore, the quantum logic gates in the output quantum circuit are limited in number, and the multi-bit quantum logic gates with complex unitary matrix form are eliminated, so that the quantum logic gate form is simplified, the calculation amount can be reduced, the simulation efficiency of the quantum circuit is improved, and the occupation of hardware resources is reduced.
An embodiment of the present invention further provides an electronic device, which includes a memory and a processor, where the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any one of the method embodiments described above.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in this embodiment, the processor may be configured to execute the following steps by a computer program:
s1, acquiring unitary matrix U corresponding to the quantum circuit; wherein the order number N of the unitary matrix is 2nThe n is the total number of quantum bits contained in the quantum wire;
s2, decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein, satisfy Ur…Ui…U1U＝INSaid UiFor the ith sheet carrying controlled informationI is more than or equal to 1 and less than or equal to r of unitary matrix corresponding to the quantum logic gate, wherein
Figure BDA0002475182640000271
Said INIs an N-order identity matrix;
and S3, outputting quantum wires containing the r single quantum logic gates carrying the controlled information.
Therefore, the quantum logic gates in the output quantum circuit are limited in number, and the multi-bit quantum logic gates with complex unitary matrix form are eliminated, so that the quantum logic gate form is simplified, the calculation amount can be reduced, the simulation efficiency of the quantum circuit is improved, and the occupation of hardware resources is reduced.
The construction, features and functions of the present invention are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present invention, but the present invention is not limited by the drawings, and all equivalent embodiments modified or changed according to the idea of the present invention should fall within the protection scope of the present invention without departing from the spirit of the present invention covered by the description and the drawings.

Claims (10)

1. A method for decomposing a quantum line, comprising:
acquiring a unitary matrix U corresponding to the quantum circuit; wherein the order number N of the unitary matrix is 2nThe n is the total number of quantum bits contained in the quantum wire;
decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein, satisfy Ur…Ui…U1U＝INSaid UiI is more than or equal to 1 and is more than or equal to r, the unitary matrix corresponding to the ith single quantum logic gate carrying the controlled information
Figure FDA0002475182630000011
Said INIs an N-order identity matrix;
outputting a quantum wire containing the r single quantum logic gates carrying the controlled information.
2. The method of claim 1, wherein decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information comprises:
determining the sequence of non-diagonal elements to be set to 0 below the diagonal elements in the unitary matrix U;
constructing an N-order unitary matrix U of a specific quantum logic gate for the ith off-diagonal element in the orderingiTo make the matrix Ui…U1Setting the element at the same position as the non-diagonal element in the U as 0, and not changing the non-diagonal element with 0;
the specific quantum logic gate comprises a single quantum logic gate for operating one bit, the single quantum logic gate carries controlled information controlled by other bits, and i is more than or equal to 1 and less than or equal to r; when the i is 1, the unitary matrix of the single quantum logic gate is determined by elements of a unitary matrix U corresponding to the quantum circuit; when 1 is<When i is less than or equal to r, the unitary matrix of the single quantum logic gate is composed of a matrix Ui-1…U1Determining elements of U; and when the ith off-diagonal element is ordered to be the last of the columns, simultaneously enabling the matrix Ui…U1The diagonal element in the same column of U is set to 1.
3. The method of claim 2, wherein the determining the ordering of the non-diagonal elements to be set to 0 below the diagonal elements in the unitary matrix U comprises:
when n is 1, ordering the off-diagonal elements below the diagonal elements in the unitary matrix U and to be set to 0 as (2, 1); wherein the (2,1) represents an off-diagonal element with coordinates of row 2, column 1;
when n is greater than 1, determining a first column sequence of non-diagonal elements to be set to 0 below diagonal elements in the unitary matrix U corresponding to the n-bit quantum lines according to a first column sequence of the unitary matrix corresponding to the (n-1) bit quantum lines; wherein the ordering of the off-diagonal elements of coordinates (N/2+1,1) in the first column is located at the last of the first column;
respectively determining the ordering of off-diagonal elements to be set to 0 below diagonal elements in the 2 nd to the N/2 nd columns corresponding to the N-bit quantum lines based on the first column ordering corresponding to the N-bit quantum lines;
and correspondingly determining the sequencing of the non-diagonal elements to be set to 0 under the diagonal elements in the (N/2+1) th to the N (N) th columns corresponding to the N-bit quantum lines according to the sequencing of the non-diagonal elements to be set to 0 under the diagonal elements in the unitary matrix corresponding to the (N-1) bit quantum lines.
4. The method of claim 1, wherein the representation of the single quantum logic gate carrying the controlled information comprises:
{Cn…Cm…C1wherein, the CmRepresents 0,1, or a single quantum logic gate V, said m representing a qubit, m ∈ [1, n]And, has and only one CmRepresenting a single quantum logic gate V, the unitary matrix of which is determined by the unitary matrix U;
when C is presentmWhen the quantum state of the qubit of the bit is 0 state, the single quantum logic gate V is executed before the quantum wire runs to the single quantum logic gate V;
when C is presentmWhen the value is 1, the quantum circuit executes the single quantum logic gate V when the quantum state of the quantum bit of the bit is 1 state before running to the single quantum logic gate V;
when C is presentmAnd is, before the quantum wire runs to the single quantum logic gate V, when the quantum state of the quantum bit of the bit is an arbitrary state, the single quantum logic gate V is executed.
5. A quantum line decomposition device, comprising:
the acquisition module is used for acquiring a unitary matrix U corresponding to the quantum circuit; wherein the order number N of the unitary matrix is 2nThe n is the total number of quantum bits contained in the quantum wire;
a decomposition module for decomposing the unitary matrix U into r pieces carrying controlled informationUnitary matrix corresponding to the single quantum logic gate; wherein, satisfy Ur…Ui…U1U＝INSaid UiI is more than or equal to 1 and is more than or equal to r, the unitary matrix corresponding to the ith single quantum logic gate carrying the controlled information
Figure FDA0002475182630000021
Said INIs an N-order identity matrix;
and the output module is used for outputting the quantum wires containing the r single quantum logic gates carrying the controlled information.
6. The apparatus of claim 5, wherein the decomposition module comprises:
a determining unit, configured to determine an ordering of non-diagonal elements to be set to 0 below diagonal elements in the unitary matrix U;
a construction unit for constructing an N-order unitary matrix U of a specific quantum logic gate for the ith off-diagonal element in the orderingiTo make the matrix Ui…U1Setting the element at the same position as the non-diagonal element in the U as 0, and not changing the non-diagonal element with 0;
the specific quantum logic gate comprises a single quantum logic gate for operating one bit, the single quantum logic gate carries controlled information controlled by other bits, and i is more than or equal to 1 and less than or equal to r; when the i is 1, the unitary matrix of the single quantum logic gate is determined by elements of a unitary matrix U corresponding to the quantum circuit; when 1 is<When i is less than or equal to r, the unitary matrix of the single quantum logic gate is composed of a matrix Ui-1…U1Determining elements of U; and when the ith off-diagonal element is ordered to be the last of the columns, simultaneously enabling the matrix Ui…U1The diagonal element in the same column of U is set to 1.
7. The apparatus according to claim 6, wherein the determining unit is specifically configured to:
when n is 1, ordering the off-diagonal elements below the diagonal elements in the unitary matrix U and to be set to 0 as (2, 1); wherein the (2,1) represents an off-diagonal element with coordinates of row 2, column 1;
when n is greater than 1, determining a first column sequence of non-diagonal elements to be set to 0 below diagonal elements in the unitary matrix U corresponding to the n-bit quantum lines according to a first column sequence of the unitary matrix corresponding to the (n-1) bit quantum lines; wherein the ordering of the off-diagonal elements of coordinates (N/2+1,1) in the first column is located at the last of the first column;
respectively determining the ordering of off-diagonal elements to be set to 0 below diagonal elements in the 2 nd to the N/2 nd columns corresponding to the N-bit quantum lines based on the first column ordering corresponding to the N-bit quantum lines;
and correspondingly determining the sequencing of the non-diagonal elements to be set to 0 under the diagonal elements in the (N/2+1) th to the N (N) th columns corresponding to the N-bit quantum lines according to the sequencing of the non-diagonal elements to be set to 0 under the diagonal elements in the unitary matrix corresponding to the (N-1) bit quantum lines.
8. The apparatus of claim 5, wherein the representation of the single quantum logic gate carrying the controlled information comprises:
{Cn…Cm…C1wherein, the CmRepresents 0,1, or a single quantum logic gate V, said m representing a qubit, m ∈ [1, n]And, has and only one CmRepresenting a single quantum logic gate V, the unitary matrix of which is determined by the unitary matrix U;
when C is presentmWhen the quantum state of the qubit of the bit is 0 state, the single quantum logic gate V is executed before the quantum wire runs to the single quantum logic gate V;
when C is presentmWhen the value is 1, the quantum circuit executes the single quantum logic gate V when the quantum state of the quantum bit of the bit is 1 state before running to the single quantum logic gate V;
when C is presentmWhen the quantum state of the quantum bit of the bit is any state before the quantum wire runs to the single quantum logic gate V, the single quantum logic gate V is executed。
9. A storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 1 to 4 when executed.
10. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 4.
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