CN111563599B - Quantum circuit decomposition method and device, storage medium and electronic device - Google Patents
Quantum circuit decomposition method and device, storage medium and electronic device Download PDFInfo
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Abstract
The invention discloses a method and a device for decomposing a quantum circuit, a storage medium and an electronic device, wherein the method comprises the following steps: acquiring a unitary matrix U corresponding to a quantum line; wherein the unitary matrix has an order n=2 n N is the total number of quantum bits contained in the quantum circuit; decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein, satisfy U r …U i …U 1 U＝I N The U is i For the i-th unitary matrix corresponding to the single quantum logic gate carrying the controlled information, i is more than or equal to 1 and less than or equal to r, whereinThe I is N Is an N-order identity matrix; and outputting a quantum circuit containing r single quantum logic gates carrying controlled information. By using the embodiment of the invention, the calculated amount of the quantum circuit can be reduced, the simulation efficiency of the quantum circuit is improved, and meanwhile, the occupation of hardware resources is reduced.
Description
Technical Field
The invention belongs to the technical field of quantum computing, and particularly relates to a method and a device for decomposing a quantum circuit, a storage medium and an electronic device.
Background
The quantum computer is a kind of physical device which performs high-speed mathematical and logical operation, stores and processes quantum information according to the law of quantum mechanics. When a device processes and calculates quantum information and operates on a quantum algorithm, the device is a quantum computer. Quantum computers are a key technology under investigation because of their ability to handle mathematical problems more efficiently than ordinary computers, for example, to accelerate the time to crack RSA keys from hundreds of years to hours.
The quantum computing simulation is a simulation computation which simulates and follows the law of quantum mechanics by means of numerical computation and computer science, and is taken as a simulation program, and the high-speed computing capability of a computer is utilized to characterize the space-time evolution of the quantum state according to the basic law of quantum bits of the quantum mechanics.
Currently, algorithms for quantum computing are typically represented by quantum circuits, which include quantum logic gate operations. Typically, a continuous quantum wire typically contains several tens to hundreds or even thousands of quantum logic gate operations, and the more quantum logic gates or quantum bits of quantum logic gate operations, the more complex the computation process, resulting in a quantum wire with lower simulation efficiency and more hardware resources.
Disclosure of Invention
The application aims to provide a method and a device for decomposing a quantum circuit, a storage medium and an electronic device, so as to solve the defects in the prior art, reduce the calculated amount of the quantum circuit, improve the simulation efficiency of the quantum circuit and reduce the occupation of hardware resources.
One embodiment of the present application provides a method for decomposing a quantum wire, including:
acquiring a unitary matrix U corresponding to a quantum line; wherein the unitary matrix has an order n=2 n N is the total number of quantum bits contained in the quantum circuit;
decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein, satisfy U r …U i …U 1 U＝I N The U is i For the i-th unitary matrix corresponding to the single quantum logic gate carrying the controlled information, i is more than or equal to 1 and less than or equal to r, whereinThe I is N Is an N-order identity matrix;
and outputting a quantum circuit containing r single quantum logic gates carrying controlled information.
Optionally, the decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information includes:
determining the ordering of the non-diagonal elements to be placed 0 below the diagonal elements in the unitary matrix U;
constructing an N-order unitary matrix U of a specific quantum logic gate for the ith off-diagonal element in the ordering i So that matrix U i …U 1 The element at the same position as the non-diagonal element in U is set as 0, and the non-diagonal element with set 0 is not changed;
wherein the specific quantum logic gate comprises single quantum logic operating one bitThe single quantum logic gate carries controlled information controlled by the rest bits, and i is more than or equal to 1 and less than or equal to r; when i=1, the unitary matrix of the single quantum logic gate is determined by the elements of the unitary matrix U corresponding to the quantum line; when 1 <When i is less than or equal to r, the unitary matrix of the single-quantum logic gate consists of a matrix U i-1 …U 1 Determining elements of U; and, when the order of the ith off-diagonal element is the last column, simultaneously making the matrix U i …U 1 Diagonal elements in the same column of U are set to 1.
Optionally, the determining the ordering of the non-diagonal elements to be set 0 below the diagonal elements in the unitary matrix U includes:
when n=1, the non-diagonal elements to be placed 0 below the diagonal elements in the unitary matrix U are ordered as (2, 1); wherein (2, 1) represents a non-diagonal element having coordinates of row 2 and column 1;
when n is greater than 1, determining a first column ordering of non-diagonal elements to be placed 0 below diagonal elements in the unitary matrix U corresponding to the n-bit quantum lines according to the first column ordering of the unitary matrix corresponding to the (n-1) bit quantum lines; wherein the ordering of the off-diagonal elements of coordinates (N/2+1, 1) in the first column is located at the last of the first column;
based on the first column ordering corresponding to the N-bit quantum circuit, determining ordering of non-diagonal elements to be placed 0 below diagonal elements in the 2 nd column to the N/2 nd column corresponding to the N-bit quantum circuit respectively;
and correspondingly determining the ordering of the non-diagonal elements to be placed 0 below the diagonal elements in the (N/2+1) th column to the N th column corresponding to the N-bit quantum lines according to the ordering of the non-diagonal elements to be placed 0 below the diagonal elements in the unitary matrix corresponding to the (N-1) bit quantum lines.
Optionally, the representation of the single quantum logic gate carrying the controlled information includes:
{C n …C m …C 1 -wherein said C m Represents 0, 1, or a single quantum logic gate V, m represents a qubit, m is [1, n ]]And there is and only one C m Representing a single quantum logic gate VThe unitary matrix of the single quantum logic gate V is determined by the unitary matrix U;
when C m When the quantum state of the quantum bit of the bit is 0 state before the quantum circuit runs to the single quantum logic gate V, executing the single quantum logic gate V;
when C m When the quantum state of the quantum bit of the bit is 1 state before the quantum circuit runs to the single quantum logic gate V, executing the single quantum logic gate V;
when C m When this is true, it means that the single quantum logic gate V is implemented when the quantum state of the qubit of the bit is arbitrary before the quantum wire runs to the single quantum logic gate V.
Another embodiment of the present application provides a device for decomposing a quantum wire, including:
the acquisition module is used for acquiring a unitary matrix U corresponding to the quantum line; wherein the unitary matrix has an order n=2 n N is the total number of quantum bits contained in the quantum circuit;
the decomposition module is used for decomposing the unitary matrix U into r unitary matrices corresponding to the single quantum logic gates carrying the controlled information; wherein, satisfy U r …U i …U 1 U＝I N The U is i For the i-th unitary matrix corresponding to the single quantum logic gate carrying the controlled information, i is more than or equal to 1 and less than or equal to r, whereinThe I is N Is an N-order identity matrix;
and the output module is used for outputting a quantum circuit containing the r single quantum logic gates carrying the controlled information.
Optionally, the decomposition module includes:
a determining unit, configured to determine a ranking of non-diagonal elements to be set 0 below diagonal elements in the unitary matrix U;
a construction unit for constructing an N-order unitary matrix U of a specific quantum logic gate for the ith off-diagonal element in the ordering i So that matrix U i …U 1 The element at the same position as the non-diagonal element in U is set as 0, and the non-diagonal element with set 0 is not changed;
the specific quantum logic gate comprises a single quantum logic gate for operating one bit, wherein the single quantum logic gate carries controlled information controlled by the rest bits, and i is more than or equal to 1 and less than or equal to r; when i=1, the unitary matrix of the single quantum logic gate is determined by the elements of the unitary matrix U corresponding to the quantum line; when 1<When i is less than or equal to r, the unitary matrix of the single-quantum logic gate consists of a matrix U i-1 …U 1 Determining elements of U; and, when the order of the ith off-diagonal element is the last column, simultaneously making the matrix U i …U 1 Diagonal elements in the same column of U are set to 1.
Optionally, the determining unit is specifically configured to:
when n=1, the non-diagonal elements to be placed 0 below the diagonal elements in the unitary matrix U are ordered as (2, 1); wherein (2, 1) represents a non-diagonal element having coordinates of row 2 and column 1;
when n is greater than 1, determining a first column ordering of non-diagonal elements to be placed 0 below diagonal elements in the unitary matrix U corresponding to the n-bit quantum lines according to the first column ordering of the unitary matrix corresponding to the (n-1) bit quantum lines; wherein the ordering of the off-diagonal elements of coordinates (N/2+1, 1) in the first column is located at the last of the first column;
based on the first column ordering corresponding to the N-bit quantum circuit, determining ordering of non-diagonal elements to be placed 0 below diagonal elements in the 2 nd column to the N/2 nd column corresponding to the N-bit quantum circuit respectively;
and correspondingly determining the ordering of the non-diagonal elements to be placed 0 below the diagonal elements in the (N/2+1) th column to the N th column corresponding to the N-bit quantum lines according to the ordering of the non-diagonal elements to be placed 0 below the diagonal elements in the unitary matrix corresponding to the (N-1) bit quantum lines.
Optionally, the representation of the single quantum logic gate carrying the controlled information includes:
{C n …C m …C 1 And (3), whereinThe C is m Represents 0, 1, or a single quantum logic gate V, m represents a qubit, m is [1, n ]]And there is and only one C m Representing a single quantum logic gate V, a unitary matrix of which is determined by the unitary matrix U;
when C m When the quantum state of the quantum bit of the bit is 0 state before the quantum circuit runs to the single quantum logic gate V, executing the single quantum logic gate V;
when C m When the quantum state of the quantum bit of the bit is 1 state before the quantum circuit runs to the single quantum logic gate V, executing the single quantum logic gate V;
when C m When this is true, it means that the single quantum logic gate V is implemented when the quantum state of the qubit of the bit is arbitrary before the quantum wire runs to the single quantum logic gate V.
Another embodiment of the application provides a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of the above when run.
Another embodiment of the application provides an electronic device comprising a memory having a computer program stored therein and a processor configured to run the computer program to perform the method described in any of the above.
Compared with the prior art, the method for decomposing the quantum circuit provided by the invention firstly obtains the unitary matrix U corresponding to the quantum circuit, wherein the order number N=2 of the unitary matrix n N is the total number of quantum bits contained in the quantum circuit; decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein, satisfy U r …U i …U 1 U＝I N ，U i Representing the unitary matrix corresponding to the ith single quantum logic gate carrying controlled information, i is more than or equal to 1 and less than or equal to r,I N is an N-order identity matrix; finally, the output contains rQuantum wires of single quantum logic gates carrying controlled information. The number of quantum logic gates in the output quantum circuit is limited, and the multi-bit quantum logic gates with complex unitary matrix form are eliminated, so that the quantum logic gate form is simplified, the calculated amount can be reduced, the simulation efficiency of the quantum circuit is improved, and meanwhile, the occupation of hardware resources is reduced.
Drawings
Fig. 1 is a hardware block diagram of a computer terminal according to an embodiment of the present invention, which is a method for decomposing a quantum wire;
fig. 2 is a flow chart of a method for decomposing a quantum circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating execution timing of a quantum circuit according to an embodiment of the present invention;
Fig. 4 is a schematic diagram of a quantum circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a specific quantum logic gate in a quantum circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a device for decomposing a quantum circuit according to an embodiment of the present invention.
Detailed Description
The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
The embodiment of the invention firstly provides a method for decomposing a quantum circuit, which can be applied to electronic equipment such as a computer terminal, in particular to a common computer, a quantum computer and the like.
The following describes the operation of the computer terminal in detail by taking it as an example. Fig. 1 is a hardware block diagram of a computer terminal according to an embodiment of the present invention. As shown in fig. 1, the computer terminal 10 may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing data, and optionally, a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the configuration shown in fig. 1 is merely illustrative and is not intended to limit the configuration of the computer terminal described above. For example, the computer terminal 10 may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum computing simulation method in the embodiment of the present application, and the processor 102 executes the software programs and modules stored in the memory 104 to perform various functional applications and data processing, i.e., implement the method described above. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the computer terminal 10 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission means 106 is arranged to receive or transmit data via a network. The specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal 10. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module for communicating with the internet wirelessly.
It should be noted that a real quantum computer is a hybrid structure, which includes two major parts: part of the computers are classical computers and are responsible for performing classical computation and control; the other part is quantum equipment, which is responsible for running quantum programs so as to realize quantum computation. The quantum program is a series of instruction sequences written by a quantum language such as the qlunes language and capable of running on a quantum computer, so that the support of quantum logic gate operation is realized, and finally, quantum computing is realized. Specifically, the quantum program is a series of instruction sequences for operating the quantum logic gate according to a certain time sequence.
In practical applications, quantum computing simulations are often required to verify quantum algorithms, quantum applications, etc., due to the development of quantum device hardware. Quantum computing simulation is a process of realizing simulated operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to construct a quantum program corresponding to a specific problem. The quantum program, namely the program for representing the quantum bit and the evolution thereof written in the classical language, wherein the quantum bit, the quantum logic gate and the like related to quantum computation are all represented by corresponding classical codes.
Quantum circuits, which are one embodiment of quantum programs, also weigh sub-logic circuits, are the most commonly used general quantum computing models, representing circuits that operate on qubits under an abstract concept, the composition of which includes qubits, circuits (timelines), and various quantum logic gates, and finally the results often need to be read out by quantum measurement operations.
Unlike conventional circuits, which are connected by metal lines to carry voltage or current signals, in a quantum circuit, the circuit can be seen as being connected by time, i.e., the state of the qubit naturally evolves over time, as indicated by the hamiltonian operator, during which it is operated until a logic gate is encountered.
One quantum program is corresponding to one total quantum circuit, and the quantum program refers to the total quantum circuit, wherein the total number of quantum bits in the total quantum circuit is the same as the total number of quantum bits of the quantum program. It can be understood that: one quantum program may consist of a quantum circuit, a measurement operation for the quantum bits in the quantum circuit, a register to hold the measurement results, and a control flow node (jump instruction), and one quantum circuit may contain several tens to hundreds or even thousands of quantum logic gate operations. The execution process of the quantum program is a process of executing all quantum logic gates according to a certain time sequence. Note that the timing is the time sequence in which a single quantum logic gate is executed.
It should be noted that in classical computation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved by a combination of logic gates. Similarly, the way in which the qubits are handled is a quantum logic gate. Quantum logic gates are used, which are the basis for forming quantum circuits, and include single-bit quantum logic gates, such as Hadamard gates (H gates, ada Ma Men), bery-X gates (X gates), bery-Y gates (Y gates), bery-Z gates (Z gates), RX gates, RY gates, RZ gates, and the like; multi-bit quantum logic gates such as CNOT gates, CR gates, iSWAP gates, toffoli gates, and the like. Quantum logic gates are typically represented using unitary matrices, which are not only in matrix form, but also an operation and transformation. The effect of a general quantum logic gate on a quantum state is calculated by multiplying the unitary matrix by the matrix corresponding to the right vector of the quantum state.
Referring to fig. 2, fig. 2 is a flow chart of a method for decomposing a quantum circuit according to an embodiment of the present invention, which may include:
s201, obtaining a unitary matrix U corresponding to a quantum line; wherein the unitary matrix has an order n=2 n N is the total number of quantum bits contained in the quantum circuit;
specifically, for a quantum circuit, execution timing may be divided into quantum logic gates included in the quantum circuit; and calculating the unitary matrix U corresponding to the quantum line according to the unitary matrix information corresponding to each execution time sequence and each quantum logic gate.
In practical application, for each execution time sequence, tensor product operation is performed on the unitary matrix corresponding to each quantum logic gate in the execution time sequence according to the number sequence of the quantum bits, matrix multiplication operation is performed on each matrix obtained by the tensor product operation according to the sequence before and after the execution time sequence, and finally the unitary matrix U corresponding to the quantum line is obtained. Wherein the tensor product is the operation between two matrices of arbitrary size, expressed asAlso known as direct product, kronecker product, or tensor multiplication. The matrix belongs to second-order tensors, and the tensor product can play a role in dimension expansion.
And if the space quantum logic gate is simply referred to as a space gate in the specific quantum circuit, in order to keep the dimension after dimension expansion the same, the unitary matrix corresponding to the space quantum logic gate is set as a unitary matrix I of 2 x 2. The unitary matrix of the existing single-quantum logic gate is a matrix of 2×2, the unitary matrix of the two-quantum logic gate is a matrix of 4*4, for example, the unitary matrix of the H gate is The unitary matrix of the X gate is +.>The unitary matrix of the CNOT gate is +.>Etc.
And multiplying each matrix obtained by tensor product operation according to the sequence of execution time sequence to obtain the matrix corresponding to the specific quantum circuit.
Fig. 3 is an example, and fig. 3 is a schematic diagram illustrating a division of an execution timing of a quantum circuit according to an embodiment of the present invention, and a dotted line indicates the division of the execution timing. In the 1 st time sequence, q3 has no quantum logic gate operation, and actually performs a blank gate operation in the program, and the blank gate can be regarded as a single quantum logic gate of an identity matrix with unitary matrix of 2 x 2. Sequentially right multiplying (tensor multiplying) unitary matrices in order of bit numbers from low order to high order to obtain 2 n *2 n N is the number of qubits. In this fig. 3, the qubit numbering order is 0-4, and n is 5. Similarly, the other 5 timings also respectively obtain a matrix of 32×32.
And then, sequentially performing matrix multiplication on the 6 matrixes according to the sequence corresponding to the matrixes, and finally obtaining a matrix of 32 x 32, namely the matrix corresponding to the specific quantum circuit. Matrix multiplication here refers to a generic matrix product, namely: let a be a matrix of h×p, B be a matrix of p×q, then let C be the product of a and B, denoted as c=ab, where the ith row and jth column element in C can be expressed as:
The unitary matrix of each quantum logic gate in each execution time sequence is subjected to tensor product operation to expand dimension, so that the matrixes corresponding to each execution time sequence obtained by the tensor product operation are in the same dimension, and the accuracy of space-time evolution of the quantum state of the quantum bit for carrying out matrix multiplication and characterization on each matrix in the next step is ensured.
Before the execution time sequence is divided, if a part of quantum circuits in a transposed conjugated dagger state exists in the quantum circuits, at least one quantum logic gate contained in the part of quantum circuits is reversely ordered, and a transposed conjugated matrix of a unitary matrix of the quantum logic gate is obtained and used as new unitary matrix information. Wherein a portion of the quantum wire may comprise a succession of one or more quantum logic gates, or even the entire quantum wire.
For example, the quantum wire of fig. 3 includes: h q0, H q, RY q2, H q4, RX q0, X q1, CNOT q4q3, Z q0, H q1, CNOT q2q3, H q4, CNOT q1q0, H q2, CNOT q3q4, RZ q3, Y q4, RX q4, wherein q0, q1, q2, q3, q4 refer to qubits with bits from 0 to 4.
Assuming that partial quantum wires H q0, H q1, RY q2, H q4, RX q0, X q1, CNOT q4q3, Z q0 are in dagger, the logic gates in the partial quantum wires are reverse ordered: z q0, CNOT q4q3, X q1, RX q0, H q4, RY q2, H q1, H q0, and performing transposed conjugation operation on the unitary matrix of each logic gate to obtain a new transposed conjugated matrix, where the quantum circuit can be expressed as: dagger q0, cnot.dagger q4q3, x.dagger q1, rx.dagger q0, h.dagger q4, ry.dagger q2, h.dagger q1, h.dagger q0, H q1, CNOT q2q3, H q4, CNOT q1q0, H q2, CNOT q3q4, RZ q3, Y q, RX q4. Dagger is only a form reference, and represents a Z gate at dagger, wherein the unitary matrix is a transposed conjugate matrix of an original unitary matrix of the Z gate, and the rest is the same.
For another example, a quantum circuit schematic diagram is shown in fig. 4, and after the time sequence is divided:
first time sequence: h q0, CNOT q2q1;
second timing: x q2.
Calculating unitary matrix in first time sequence:
the method comprises the following steps:
calculating unitary matrices in a second time sequence:
then, a matrix multiplication operation is performed:
the following 8-order matrix is obtained, namely the unitary matrix corresponding to the quantum line segment:
s202, decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein, satisfy U r …U i …U 1 U＝I N The U is i For the i-th unitary matrix corresponding to the single quantum logic gate carrying the controlled information, i is more than or equal to 1 and less than or equal to r, whereinThe I is N Is an N-order identity matrix;
specifically, it may include:
s2021, determining the ordering of the non-diagonal elements to be set 0 below the diagonal elements in the unitary matrix U;
in one implementation, the ordering of the non-diagonal elements to be placed 0 below the diagonal elements in unitary matrix U may be: the first column is arranged to the last column according to the column number, the non-diagonal elements of each column are ordered from top to bottom according to the row number, and an ordering example of a 4-order unitary matrix of a two-bit quantum line is shown in table 1.
TABLE 1 unitary matrix element ordering for two-bit Quantum circuits
| 00 | 01 | 10 | 11 | |
| 00 | (1,1) | |||
| 01 | (2,1)1 | (2,2) | ||
| 10 | (3,1)2 | (3,2)1 | (3,3) | |
| 11 | (4,1)3 | (4,2)2 | (4,3)1 | (4,4) |
Wherein 00, 01, 10, 11 represent binary representations corresponding to rows or columns, and binary bits are in one-to-one correspondence with qubit bits; (1, 1), (2, 2), (3, 3), (4, 4) represent diagonal elements corresponding to coordinates, such as (2, 1), (3, 1), (4, 1) represent off-diagonal elements corresponding to coordinates, and numerals 1, 2, 3 at the back of brackets represent the corresponding ordering.
It should be emphasized that, since the matrix forms of the quantum logic gates are unitary matrices, that is, the product of the unitary matrix and the transposed conjugate of the unitary matrix is a unitary matrix, and the product between the unitary matrices is also a unitary matrix, only the operation of setting 0 of the non-diagonal element below the diagonal line of the matrix is needed to be concerned, and the non-diagonal element in the same column above the diagonal element is set 0 while the diagonal element is set 1, which is determined by the characteristics of the unitary matrix and will not be described again. Similarly, a 0-setting operation focusing only on non-diagonal elements above the matrix diagonal is also possible.
Preferably, in order to facilitate subsequent matrix construction, in another implementation, the ordering of the non-diagonal elements to be set to 0 below the diagonal elements in the unitary matrix U may be:
when n=1, the non-diagonal elements to be placed 0 below the diagonal elements in the unitary matrix U are ordered as (2, 1); wherein (2, 1) represents a non-diagonal element having coordinates of row 2 and column 1;
When n is greater than 1, determining a first column ordering of non-diagonal elements to be placed 0 below diagonal elements in the unitary matrix U corresponding to the n-bit quantum lines according to the first column ordering of the unitary matrix corresponding to the (n-1) bit quantum lines; wherein the ordering of the off-diagonal elements of coordinates (N/2+1, 1) in the first column is located at the last of the first column;
based on the first column ordering corresponding to the N-bit quantum circuit, determining ordering of non-diagonal elements to be placed 0 below diagonal elements in the 2 nd column to the N/2 nd column corresponding to the N-bit quantum circuit respectively;
and correspondingly determining the ordering of the non-diagonal elements to be placed 0 below the diagonal elements in the (N/2+1) th column to the N th column corresponding to the N-bit quantum lines according to the ordering of the non-diagonal elements to be placed 0 below the diagonal elements in the unitary matrix corresponding to the (N-1) bit quantum lines.
For example, for a 2-order unitary matrix of a 1-bit quantum line, there is only one element (2, 1) below the diagonal element, so the non-diagonal elements ordered and only the first column are: (2,1).
For a 4-order unitary matrix of 2-bit quantum lines, the first column ordering adopts a recursive idea, namely, the first column ordering of 1-bit quantum lines is referred to, and the off-diagonal elements of the 1 st column of the (N/2+1) th row are arranged at the last of the columns, namely, (2, 1) th and (3, 1) th are arranged at the last 1, so that the (4, 1) th is determined to be arranged at the 2 nd, and finally, the 1 st column ordering can be obtained as follows: (2, 1), (4, 1), (3, 1).
For an 8-order unitary matrix of a 3-bit quantum circuit, the first column ordering refers to the first column ordering of a 2-bit quantum circuit, namely, the 1 st to 3 rd are (2, 1), (4, 1), (3, 1), and (5, 1) is located at the last 1, and the rest of (6, 1), (7, 1), (8, 1) refers to the ordering of (2, 1), (3, 1), (4, 1) as (6, 1), (8, 1), (7, 1), and finally the 1 st column ordering can be obtained as: (2, 1), (4, 1), (3, 1), (6, 1), (8, 1), (7, 1), (5, 1).
By analogy, the 1 st column ordering of the 4-bit quantum circuits refers to the 1 st column ordering of the 3-bit quantum circuits, as: (2, 1), (4, 1), (3, 1), (6, 1), (8, 1), (7, 1), (5, 1), (10, 1), (12, 1), (11, 1), (14, 1), (16, 1), (15, 1), (13, 1), (9, 1), and so on, more bit quantum circuits can be obtained in column 1 order.
Then, taking the 4-order unitary matrix of the 2-bit quantum line as an example, determining the rank 2 ordering:
acquiring the sequences of elements (3, 1) and (4, 1) in the same row as the columns (3, 2) and (4, 2) in the first column, namely (4, 1) and (3, 1), wherein the binary representations of the corresponding rows are 11 and 00, and performing exclusive OR operation with binary representation 01 corresponding to the column 2 respectively:
11⊕01＝10＝(3,2)
10⊕01＝11＝(4,2)
the 2 nd column ordering of the 4 th order unitary matrix of the 2 bit quantum line is available as follows: (3, 2), (4, 2).
Determining the rank of columns 3 to 4: unitary matrix ordering of analog 1-bit quantum lines is: (4, 3), the resulting ordering is shown in Table 2.
Table 2 unitary matrix ordering of another 2-bit quantum circuit
| 00 | 01 | 10 | 11 | |
| 00 | (1,1) | |||
| 01 | (2,1)1 | (2,2) | ||
| 10 | (3,1)3 | (3,2)1 | (3,3) | |
| 11 | (4,1)2 | (4,2)2 | (4,3)1 | (4,4) |
Similarly, taking a 3-bit quantum circuit as an example, the sequence of the 2 nd column to the 4 th column is determined first:
the non-diagonal elements in column 1 that are in the same row as column 2 are ordered as: the binary of the corresponding row is exclusive-ored with the binary of the 2 nd column respectively, (4, 1), (3, 1), (6, 1), (8, 1), (7, 1), (5, 1), and the ordering of (3, 2), (4, 2) is unchanged as known from the 2-bit quantum circuit, and the exclusive-ored operation can be omitted here, namely:
101⊕001＝100＝(5,2)
111⊕001＝110＝(7,2)
110⊕001＝111＝(8,2)
100⊕001＝101＝(6,2)
the 8-order unitary matrix of the 3-bit quantum line is available with the 2 nd rank ordering: (3, 2), (4, 2), (5, 2), (7, 2), (8, 2), (6, 2);
the non-diagonal elements in column 1 that are in the same row as column 3 are ordered as: the binary of the corresponding row is exclusive-ored with the binary of the 3 rd column respectively (4, 1), (6, 1), (8, 1), (7, 1), (5, 1), and the ordering of (4, 3) is unchanged as known from the 2-bit quantum circuit, and the exclusive-ored operation can be omitted here, namely:
101⊕010＝110＝(8,3)
111⊕010＝101＝(6,3)
110⊕010＝100＝(5,3)
100⊕010＝110＝(7,3)
the 3 rd order unitary matrix of the 3-bit quantum line is available with the 3 rd order: (4, 3), (8, 3), (6, 3), (5, 3), (7, 3);
the non-diagonal elements in column 1 that are in the same row as column 4 are ordered as: (6, 1), (8, 1), (7, 1), (5, 1), the binary of the corresponding row is exclusive-ored with the binary of column 4, respectively, i.e.:
101⊕011＝110＝(7,4)
111⊕011＝100＝(5,4)
110⊕011＝101＝(6,4)
100⊕011＝111＝(8,4)
The 8 th order unitary matrix of the 3 bit quantum line is available with the 4 th order: (7, 4), (5, 4), (6, 4), (8, 4).
Next, for the 5 th to 8 th order unitary matrix of the 3-bit quantum line, the 1 st to 4 th order unitary matrix of the 4-order analog 2-bit quantum line can be obtained:
column 5 ordering: (6, 5), (8, 5), (7, 5);
column 6 ordering: (7, 6), (8, 6);
column 7 ordering: (8, 7);
column 8 ordering: and no.
The same can determine the unitary matrix rank 2 to last of more bit quantum lines. From the above, a partial column ordering of the unitary matrix of a 3-bit quantum wire is shown in table 3.
TABLE 3 partial column ordering of unitary matrix for 3-bit Quantum circuits
| 000 | 001 | 010 | 011 | ... | |
| 000 | (1,1) | ... | |||
| 001 | (2,1)1 | (2,2) | ... | ||
| 010 | (3,1)3 | (3,2)1 | (3,3) | ... | |
| 011 | (4,1)2 | (4,2)2 | (4,3)1 | (4,4) | ... |
| 100 | (5,1)7 | (5,2)3 | (5,3)4 | (5,4)2 | ... |
| 101 | (6,1)4 | (6,2)6 | (6,3)3 | (6,4)3 | ... |
| 110 | (7,1)6 | (7,2)4 | (7,3)5 | (7,4)1 | ... |
| 111 | (8,1)5 | (8,2)5 | (8,3)2 | (8,4)4 | ... |
S2022, for the ith off-diagonal element in the ordering, constructing an N-order unitary matrix U of a specific quantum logic gate i So that matrix U i …U 1 The element in U that is co-located with the off-diagonal element is set to 0 and the off-diagonal element that has been set to 0 is not changed. And, when the order of the ith off-diagonal element is the last one of the columns, simultaneously making the matrix U i …U 1 Diagonal elements in the same column of U are set to 1.
For convenience of distinction, a single quantum logic gate carrying controlled information can also be understood as a specific quantum logic gate, since its unitary matrix is no longer a 2-order unitary matrix of a single quantum logic gate in the ordinary sense, but an N-order unitary matrix U i The representation of the particular quantum logic gate may be:
{C n …C m …C 1 }
wherein C is m Represents 0, 1, or single quantum logic gate V, m represents a quantum bit, m is [1, n ]]And there is and only one C m Representing a single quantum logic gate V. The single quantum logic gate V is a single quantum logic gate operating one qubit in a common sense, but can be additionally controlled by the rest of the qubits in the quantum circuit. The particular quantum logic gates constructed may be different for the off-diagonal elements of the different entries to be set to 0.
When C m When the quantum state is 0, the quantum circuit is operated before the single quantum logic gate V (namely, the logic gate V is about to be executed in the next step), and when the quantum state of the quantum bit of the bit is judged to be 0 state, the single quantum logic gate V is executed, and is controlled for short by 0;
when C m When the quantum state of the quantum bit of the bit is 1 state before the quantum circuit runs to the single quantum logic gate V, executing the single quantum logic gate V, namely 1 control;
when C m When the quantum state of the quantum bit of the bit is any state before the quantum circuit runs to the single quantum logic gate V, the single quantum logic gate V is executed, and is simply uncontrolled.
For example, one particular quantum logic gate is represented in {10 x V }, indicating that a single quantum logic gate V acts on the lowest order qubit, indicating that logic gate V is not controlled by the qubit of bit 2 (no control), 0 indicating that logic gate V is controlled by the qubit of bit 3 (0 control), and 1 indicating that logic gate V is controlled by the qubit of bit 4 (1 control). It is also known that the quantum circuit is a 4-bit quantum circuit, and the unitary matrix of the specific quantum logic gate is 2 4 =16 th order unitary matrix.
Specifically, i is a positive integer, and the value range is: i is more than or equal to 1 and r is more than or equal to r. When i=1, the unitary matrix of the single quantum logic gate V is determined by the elements of the unitary matrix U of the quantum line; when 1<When i is less than or equal to r, the unitary matrix of the single quantum logic gate V is formed by a matrix U i-1 …U 1 Element determination of U.
For example, for a 2-bit quantum circuit, on the basis of Table 2, the representation of a specific quantum logic gate is correspondingly added, as shown in Table 4, U 1 ＝{*V}，U 2 ＝{1V}，U 3 ＝{V*}，U 4 ＝{1V}，U 5 ＝{V1}，U 6 ＝{1V}。
TABLE 4 specific Quantum logic Gate corresponding to 2-bit Quantum Circuit
The specific matrix form is as follows:
wherein,it is added that the matrix form of {0V } and { V0} associated with the 2-bit quantum wire is as follows: />
A schematic diagram of a specific quantum logic gate {0V }, {1V }, { V0}, { V1} in a quantum circuit can be shown in fig. 5, with the open dots and the connection to V representing a 0 control, the solid dots and the connection to V representing a 1 control, the upper horizontal line representing the low-order quantum bit timeline, and the lower horizontal line representing the high-order quantum bit timeline.
Suppose that the unitary matrix of a 2-bit quantum wire is as follows:
first step, u is 21 Co-located off-diagonal elements set 0:
in the case of a 1-bit quantum wire,
v 21 *u 11 +v 22 *u 21 ＝0，v 11 *u 11 +v 12 *u 21 ＝1，the calculation can be as follows:
it can be seen that the element determination of V is related to the (1, 1) term and the (2, 1) term, and that the (2, 1) term is eliminated by the (1, 1) term so that the (2, 1) term after matrix multiplication is 0. In a similar manner, for a 2-bit quantum circuit, the (2, 1) term is also first eliminated with the (1, 1) term, V for each element V in V 11 、v 12 、v 21 、v 22 Determining from the (1, 1) and (2, 1) items:
/>
second step, u is 41 Co-located off-diagonal elements set 0:
the (1, 1) term is used to eliminate the (2, 1) term, the lower left half is used to U 1 The (3, 1) term in U eliminates the (4, 1) term, from which V is determined:
third step, u is as follows 31 The co-located off-diagonal element is set to 0 while the column of diagonal elements is set to 1:
by U 2 U 1 The (1, 1) term in U eliminates the (3, 1) term, from which V is determined:
/>
due toAnd->All are unitary matrices, and the product of the unitary matrix and the transpose conjugate of the unitary matrix is a unit matrix, and can be calculated by the condition:
similarly, for column 2, the (3, 2) and (4, 2) terms are eliminated by analogically eliminating the (4, 1) and (3, 1) terms, while the element 0 term in the first column is unchanged. Then, the matrix is in the form of the sum of a second-order identity matrix and a second-order matrix, and the second-order matrix can be regarded as a 1-bit quantum circuit, and is processed by adopting a specific quantum logic gate {1V }, so that the first two columns with 0 are not affected.
For unitary matrices of 3-bit quantum circuits, for the first column, the (2, 1), (4, 1), (3, 1) terms are eliminated in the same way as in the case of 2-bit quantum circuits, except that the specific quantum logic gates used are different; for the lower half, the term (6, 1), (8, 1), (7, 1) can be analogically the term (2, 1), (4, 1), (3, 1) and finally the term (5, 1) is eliminated by the term (1, 1). For the second column, the (3, 2), (4, 2) term is eliminated in analogy to the (6, 1), (8, 1), (7, 1), (5, 1) term to eliminate the (5, 2), (7, 2), (8, 2), (6, 2) term as in the case of the 2-bit quantum wire. The rest of the columns are the same.
More specifically, the term of element b is eliminated with the term of element a, and if the position of the term a is above the term b:
/>
otherwise, in case item a is below item b:
wherein a is * 、b * Represents the conjugation of a and b.
For a 3-bit quantum circuit, the representation of the corresponding particular quantum logic gate is shown in table 5 below, based on table 3:
TABLE 5 specific Quantum logic Gate corresponding to 3-bit Quantum Circuit
First column, (2, 1): u (U) 1 ＝{**V}；(4,1)：U 2 ＝{*1V}；(3,1)：U 3 ＝{*V*}；(6,1)：U 4 ＝{1*V}；(8,1)：U 5 ＝{*1V}；(7,1)：U 6 ＝{1V*}；(5,1)：U 7 ＝{V**}；
Second column, (3, 2): u (U) 8 ＝{*1V}；(4,2)：U 9 ＝{*V1}；(5,2)：U 10 ＝{1*V}；(7,2)：U 11 ＝{*1V}；(8,2)：U 12 ＝{1V*}；(6,2)：U 13 ＝{V*1}；
Third column, (4, 3): u (U) 14 ＝{*1V}；(8,3)：U 15 ＝{1*V}；(6,3)：U 16 ＝{10V}；(5,3)：U 17 ＝{1V*}；(7,3)：U 18 ＝{V1*}；
Fourth column, (7, 4): u (U) 19 ＝{1*V}；(5,4)：U 20 ＝{10V}；(6,4)：U 21 ＝{1V*}；(8,4)：U 22 ＝{V11}；
Fifth column, (6, 5): u (U) 23 ＝{1*V}；(8,5)：U 24 ＝{11V}；(7,5)：U 25 ＝{1V*}；
Sixth column, (7, 6): u (U) 26 ＝{11V}；(8,6)：U 27 ＝{1V1}；
Seventh column, (8, 7): u (U) 28 = {11V }; the eighth column is absent.
It will be appreciated by those skilled in the art that the ordering of off-diagonal elements to be set to 0 and the N-th unitary matrix U of a particular quantum logic gate i Is not limited to the above manner, in particular to realize U r …U 1 U＝I N To be accurate.
There are some basic rules for matrix construction. For example, a 2-bit quantum line, where rows and columns of the original unitary matrix U are binary coded according to the corresponding number of quantum bits (binary representation described above), i.e., from 00 to 11, and a {0V } matrix acts on the left side of the 4-order unitary matrix U, only the 00 and 01 parts of U (i.e., the first two rows and the first two columns) are affected, and similarly {1V } affects only the 10 and 11 parts of U, { V0} affects only the 00 and 10 parts of U, and { V1} affects only the 01 and 11 parts of U. For the { V } and { V } matrices, which do not contain any controls, the matrix form is such that the left multiplication of the original matrix affects all rows and columns of the original matrix.
The construction rules of a matrix representation of a particular quantum logic gate can be summarized as follows:
1. first, a matrix structure corresponding to a first column of a unitary matrix of quantum lines is described:
1, one bit quantum wire:
the unitary line matrix has only one element (2, 1) to be set to 0, and a specific quantum logic gate { C 1 It is sufficient that { V }.u=i } = { V } N ；
2, two-bit quantum wire:
by adopting a recursion idea, referring to a 1-bit quantum circuit, a unitary circuit matrix is provided with a specific quantum logic gate { C corresponding to the last element (3, 1) to be placed in 0 n …C m …C 1 }＝{C 2 C 1 }＝{C 2 V}；
For the upper half of the unitary matrix (2, 1), the highest order quantum bit is set to uncontrolled, i.e., (2, 1): [ C 2 V}＝[*V}；
For the lower half (4, 1), C corresponding to the low-order qubit is judged 1 Whether 1 is present or not, and if not, then (4, 1): [ C 2 V = [1V }, otherwise [ C ] 2 V = { V }; the judgment can be obtained:
(4, 1) corresponds to (2, 1) of a 1-bit quantum wire: { C 2 C 1 }＝{C 2 V}＝{1V}；
The last element to be placed 0 (3, 1) is set directly as: { C 2 C 1 }＝{V*}；
3, three-bit quantum circuit:
specific quantum logic gate { C n …C m …C 1 }＝{C 3 C 2 C 1 Referring to the 2-bit quantum line in the upper half of the unitary line matrix, the highest-order quantum bit is still set to be uncontrolled, i.e., { C 3 C 2 C 1 }＝{*C 2 C 1 -the method comprises the steps of:
(2, 1) corresponds to (2, 1) of a 2-bit quantum wire: { C 3 C 2 C 1 }＝{*C 2 C 1 }＝{**V}；
(4, 1) corresponds to (4, 1) of a 2-bit quantum wire: { C 3 C 2 C 1 }＝{*C 2 C 1 }＝}*1V}；
(3, 1) corresponds to (3, 1) of a 2-bit quantum wire: { C 3 C 2 C 1 }＝{*C 2 C 1 }＝{*V*}；
C corresponding to the lower 2-bit qubit of the upper half part is judged according to the sequence of the lower half part except the last element (5, 1) to be placed in the lower half part 2 、C 1 Whether they are not 1, if they are not 1, { C 3 C 2 C 1 }＝{1C 2 C 1 }, otherwise { C 3 C 2 C 1 }＝{*C 2 C 1 -a }; the judgment can be obtained:
(6, 1) corresponding { C 3 C 2 C 1 In }, C 2 、C 1 C corresponding to (2, 1) 2 、C 1 The same is true for V, and neither is 1, the following can be obtained: { C 3 C 2 C 1 }＝{C 3 *V}＝{1*V}；
Similarly, (8, 1) corresponds to (4, 1): { C 3 C 2 C 1 }＝{C 3 1V = {1V }; (7, 1) corresponds to (3, 1): { C 3 C 2 C 1 }＝{C 3 V*}＝{1V*}；
The last element to be placed 0 (5, 1) is set directly as: { C 3 C 2 C 1 }＝{V**}；
Similarly, a matrix structure corresponding to the first column of the unitary matrix of any bit quantum line can be realized;
2. matrix construction corresponding to the second column to the N/2 th column of the unitary matrix of quantum lines:
1, two-bit quantum wire, n=2:
column 2, column subscript l=2, binary 01, binary low l 1 =1, high level l 2 =0; according to preset inequality 2 x-1 <l≤2 x Obtaining x=1; the lower half corresponds in order to the lower half of the preceding column, matrix { C 2 C 1 The construction is as follows:
(3,2): reference (4, 1) corresponds to {1V }: if j=n, and C in {1V }, then n ,…,C x+1 All are not 1, the corresponding { C 2 C 1 C in } j =1; if j is not less than 1 and not more than x, and C is corresponding to {1V }, then j ＝l j =1, then (3, 2) corresponds to { C 2 C 1 C in } j =0; otherwise, (3, 2) corresponding C j C corresponding to {1V } j Keeping consistency; the judgment can be obtained:
j=1, satisfy C j C corresponding to {1V } j Maintaining consistent conditions, i.e. C 1 ＝V；
j=2, satisfy C j C corresponding to {1V } j Maintaining consistent conditions, i.e. C 2 ＝1；
Available, (3, 2) corresponding { C 2 C 1 }＝{1V}；
(4,2): it is the last element to be placed 0 in this column, referring to { V }) corresponding to the first column (3, 1): taking the X in the { V X } as 0, performing binary addition 1 operation, changing the X into 1, and obtaining { C corresponding to (3, 2) 2 C 1 }＝{V1}；
2, three-bit quantum wire, n=3:
column 2, column subscript l=2, binary indicates 001, l 1 ＝1、l 2 ＝0、l 3 =0; according to 2 x-1 <l≤2 x Solving for x=1, the upper half (3, 2), (4, 2) referring to the two-bit quantum wire:
(3, 2) corresponding { C 3 C 2 C 1 In }, C 2 C 1 { C { corresponding to (3, 2) of two-bit quantum circuit 2 C 1 Identical } = {1V }, C 3 Let be: (3, 2) corresponding { C 3 C 2 C 1 }＝{*1V}；
(4, 2) corresponding { C 3 C 2 C 1 In }, C 2 C 1 { C { corresponding to (4, 2) of two-bit quantum circuit 2 C 1 Identical } = { V1}, C 3 Let be: (3, 2) corresponding { C 3 C 2 C 1 }＝{*V1}；
The lower half part corresponds to the lower half part of the first column in sequence, and the matrix { C 3 C 2 C 1 The construction is as follows:
(5,2): reference (6, 1) corresponds to {1*V }: if j=n, and C in {1*V }, then n ,…,C x+1 All are not 1, the corresponding { C 3 C 2 C 1 C in } j =1; if j is not less than 1 and not more than x, and C is corresponding to {1*V } j ＝l j =1, then (5, 2) corresponds to { C 3 C 2 C 1 C in } j =0; otherwise, (5, 2) corresponds to { C 3 C 2 C 1 C in } j C corresponding to {1*V } j Keeping consistency; the judgment can be obtained:
j=1, satisfy C j C corresponding to {1*V } j Maintaining consistent conditions, i.e. C 1 ＝V；
j=2, satisfy C j C corresponding to {1*V } j Maintaining consistent conditions, i.e. C 2 Equal to;
j=3, satisfy C j C corresponding to {1*V } j Maintaining consistent conditions, i.e. C 3 ＝1；
Available, (5, 2) corresponding { C 3 C 2 C 1 }＝{1*V}；
Similarly, corresponding { C 3 C 2 C 1 } = {1V }; (8, 2) corresponding { C 3 C 2 C 1 }＝{1V*}；
(6,2): it is the last element to be placed 0 in this column, referring to { V }, corresponding to the first column (5, 1): taking the value of V as 0, performing binary addition 1 operation to obtain a value of 00 to be 01, namely, converting the value of V to be 1, and obtaining a value of C corresponding to (6, 2) 3 C 2 C 1 }＝{V*1}；
Similarly available, column 3:
the upper half: (4, 3) corresponds to {1V }; the following half: (8, 3) corresponds to {1*V }, (6, 3) corresponds to {10V }, and (5, 3) corresponds to {1V }; the last element (7, 3) to be placed in this column corresponds to { V1 };
column 4 is not described in detail; it can be seen that, in the lower half, except for the last element to be placed 0 in each column, the matrix structure of even columns is correspondingly the same as that of the previous column (odd columns), and the matrix of odd columns is determined by referring to the first column;
3. Matrix construction corresponding to (N/2+1) th column to last column of unitary matrix of quantum line:
referring to the upper half of columns 1 to N/2, the highest order is changed to 1 in one-to-one correspondence, and the rest is unchanged, taking the 3-bit quantum circuit as an example, it is possible to obtain:
column 5: (6, 5) corresponds to (2, 1), and {1*V }; (8, 5) corresponds to (4, 1), and {11V }; (7, 5) corresponds to (3, 1), yielding {1V };
column 6: (7, 6) corresponds to (3, 2), and {11V }; (8, 6) corresponds to (4, 2), and {1V1};
column 7: (8, 7) corresponds to (4, 3), and {11V }; column 8 none;
similarly, matrix construction corresponding to all columns of the unitary matrix of any bit quantum line can be realized, and the description thereof is omitted here.
In particular, the method comprises the steps of,wherein V is m Equal to:
|0><0, if C m ＝0；|1><1, if C m ＝1；V-I 2 If C m ＝V；I 2 If C m Is.
S203, outputting a quantum circuit containing r single quantum logic gates carrying controlled information.
Specifically, by U r …U 1 U＝I N The method can obtain: is U (U) 1 、U r The resolved r single quantum logic gates (specific quantum logic gates) carrying controlled information are in a transposed conjugate dagger state.
After the matrix form of the particular quantum logic gate is determined, the particular quantum logic gate is determined (e.g., the particular quantum logic gate is shown in fig. 5 as being in a quantum circuit) according to the slave Sequentially to->Is constructed and outputs the decomposed execution sequence including +.>To->Is provided. Compared with a complex quantum circuit which comprises hundreds to thousands of quantum logic gates and has a larger number of multi-bit quantum logic gates, the novel quantum circuit structure is greatly simplified, and the computational complexity and the resource occupation when the quantum circuit is operated are remarkably reduced.
Therefore, the number of quantum logic gates in the output quantum circuit is limited, and the multi-bit quantum logic gates with complex unitary matrix form are eliminated, so that the quantum logic gate form is simplified, the calculated amount can be reduced, the simulation efficiency of the quantum circuit is improved, and meanwhile, the occupation of hardware resources is reduced.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a quantum circuit decomposition device according to an embodiment of the present invention, which corresponds to the flow shown in fig. 2, and may include:
an acquisition module 601, configured to acquire a unitary matrix U corresponding to a quantum line; wherein the unitary matrix has an order n=2 n N is the total number of quantum bits contained in the quantum circuit;
the decomposition module 602 is configured to decompose the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein, satisfy U r …U i …U 1 U＝I N The U is i For the i-th unitary matrix corresponding to the single quantum logic gate carrying the controlled information, i is more than or equal to 1 and less than or equal to r, whereinThe I is N Is an N-order identity matrix;
and the output module 603 is used for outputting a quantum circuit containing r single quantum logic gates carrying controlled information.
Specifically, the decomposition module includes:
a determining unit, configured to determine a ranking of non-diagonal elements to be set 0 below diagonal elements in the unitary matrix U;
a construction unit for constructing an N-order unitary matrix U of a specific quantum logic gate for the ith off-diagonal element in the ordering i So that matrix U i …U 1 The element at the same position as the non-diagonal element in U is set as 0, and the non-diagonal element with set 0 is not changed;
the specific quantum logic gate comprises a single quantum logic gate for operating one bit, wherein the single quantum logic gate carries controlled information controlled by the rest bits, and i is more than or equal to 1 and less than or equal to r; when i=1, the unitary matrix of the single quantum logic gate is determined by the elements of the unitary matrix U corresponding to the quantum line; when 1<When i is less than or equal to r, the unitary matrix of the single-quantum logic gate consists of a matrix U i-1 …U 1 Determining elements of U; and, when the order of the ith off-diagonal element is the last column, simultaneously making the matrix U i …U 1 Diagonal elements in the same column of U are set to 1.
Specifically, the determining unit is specifically configured to:
when n=1, the non-diagonal elements to be placed 0 below the diagonal elements in the unitary matrix U are ordered as (2, 1); wherein (2, 1) represents a non-diagonal element having coordinates of row 2 and column 1;
when n is greater than 1, determining a first column ordering of non-diagonal elements to be placed 0 below diagonal elements in the unitary matrix U corresponding to the n-bit quantum lines according to the first column ordering of the unitary matrix corresponding to the (n-1) bit quantum lines; wherein the ordering of the off-diagonal elements of coordinates (N/2+1, 1) in the first column is located at the last of the first column;
based on the first column ordering corresponding to the N-bit quantum circuit, determining ordering of non-diagonal elements to be placed 0 below diagonal elements in the 2 nd column to the N/2 nd column corresponding to the N-bit quantum circuit respectively;
and correspondingly determining the ordering of the non-diagonal elements to be placed 0 below the diagonal elements in the (N/2+1) th column to the N th column corresponding to the N-bit quantum lines according to the ordering of the non-diagonal elements to be placed 0 below the diagonal elements in the unitary matrix corresponding to the (N-1) bit quantum lines.
Specifically, the representation form of the single quantum logic gate carrying the controlled information comprises:
{C n …C m …C 1 -wherein said C m Represents 0, 1, or a single quantum logic gate V, m represents a qubit, m is [1, n ]]And there is and only one C m Representing a single quantum logic gate V, a unitary matrix of which is determined by the unitary matrix U;
when C m When the quantum state of the quantum bit of the bit is 0 state before the quantum circuit runs to the single quantum logic gate V, executing the single quantum logic gate V;
when C m When the quantum state of the quantum bit of the bit is 1 state before the quantum circuit runs to the single quantum logic gate V, executing the single quantum logic gate V;
when C m When this is true, it means that the single quantum logic gate V is implemented when the quantum state of the qubit of the bit is arbitrary before the quantum wire runs to the single quantum logic gate V.
Therefore, the number of quantum logic gates in the output quantum circuit is limited, and the multi-bit quantum logic gates with complex unitary matrix form are eliminated, so that the quantum logic gate form is simplified, the calculated amount can be reduced, the simulation efficiency of the quantum circuit is improved, and meanwhile, the occupation of hardware resources is reduced.
The embodiment of the invention also provides a storage medium in which a computer program is stored, wherein the computer program is arranged to perform the steps of the method embodiment of any of the above when run.
Specifically, in the present embodiment, the above-described storage medium may be configured to store a computer program for executing the steps of:
s1, acquiring a unitary matrix U corresponding to a quantum line; wherein the unitary matrix has an order n=2 n N is the total number of quantum bits contained in the quantum circuit;
s2, decomposing the unitary matrix U into r unitary matrices corresponding to single quantum logic gates carrying controlled information; wherein,meet U r …U i …U 1 U＝I N The U is i For the i-th unitary matrix corresponding to the single quantum logic gate carrying the controlled information, i is more than or equal to 1 and less than or equal to r, whereinThe I is N Is an N-order identity matrix;
s3, outputting a quantum circuit containing r single quantum logic gates carrying controlled information.
Specifically, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
Therefore, the number of quantum logic gates in the output quantum circuit is limited, and the multi-bit quantum logic gates with complex unitary matrix form are eliminated, so that the quantum logic gate form is simplified, the calculated amount can be reduced, the simulation efficiency of the quantum circuit is improved, and meanwhile, the occupation of hardware resources is reduced.
An embodiment of the invention also provides an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of the method embodiment of any of the above.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
s1, acquiring a unitary matrix U corresponding to a quantum line; wherein the unitary matrix has an order n=2 n N is the total number of quantum bits contained in the quantum circuit;
s2, decomposing the unitary matrix U into r unitary corresponding to single quantum logic gates carrying controlled informationA matrix; wherein, satisfy U r …U i …U 1 U＝I N The U is i For the i-th unitary matrix corresponding to the single quantum logic gate carrying the controlled information, i is more than or equal to 1 and less than or equal to r, whereinThe I is N Is an N-order identity matrix;
s3, outputting a quantum circuit containing r single quantum logic gates carrying controlled information.
Therefore, the number of quantum logic gates in the output quantum circuit is limited, and the multi-bit quantum logic gates with complex unitary matrix form are eliminated, so that the quantum logic gate form is simplified, the calculated amount can be reduced, the simulation efficiency of the quantum circuit is improved, and meanwhile, the occupation of hardware resources is reduced.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (10)
1. A method of decomposing a quantum wire, comprising:
obtaining unitary matrix corresponding to quantum lineThe method comprises the steps of carrying out a first treatment on the surface of the Wherein the order of the unitary matrix +.>Said->A total number of qubits contained for the quantum wire;
by targeting the unitary matrixIs building a specific quantum logic gate for the off-diagonal elements of (a)>Order unitary matrix->-providing said unitary matrix->Break down into->Unitary matrixes corresponding to the single quantum logic gates carrying the controlled information; wherein the specific quantum logic gate comprises a single quantum logic gate for operating one bit, and the single quantum logic gate carries controlled information controlled by the rest bits, so that the requirement of the single quantum logic gate is satisfiedSaid->For the i-th unitary matrix corresponding to the single quantum logic gate carrying the controlled information,said->Said- >Is->A rank identity matrix;
the output contains thePersonal carry controlled informationIs provided.
2. The method of claim 1, wherein the passing is for the unitary matrixIs building a specific quantum logic gate for the off-diagonal elements of (a)>Order unitary matrix->-providing said unitary matrix->Break down into->The unitary matrix corresponding to the single quantum logic gate carrying the controlled information comprises:
determining the unitary matrixOrdering of non-diagonal elements to be placed 0 below the mid-diagonal elements;
constructing a specific quantum logic gate for the ith off-diagonal element in the orderingOrder unitary matrix->So that the matrixThe element at the same position as the non-diagonal element is set as 0, and the non-diagonal element with set 0 is not changed;
wherein, when saidWhen the unitary matrix of the single quantum logic gate is formed by the unitary matrix corresponding to the quantum circuit>Element determination of (2); when->The unitary matrix of the single quantum logic gate consists of a matrix + ->Element determination of (2); and, when the order of the ith off-diagonal element is the last one of the columns, simultaneously making the matrix +.>The diagonal element in the same column of (1) is set to 1.
3. The method of claim 2, wherein the determining the unitary matrix Ordering of the off-diagonal elements to be placed 0 below the mid-diagonal elements, comprising:
when n=1, the non-diagonal elements to be placed 0 below the diagonal elements in the unitary matrix U are ordered as (2, 1); wherein (2, 1) represents a non-diagonal element having coordinates of row 2 and column 1;
when n is greater than 1, determining a first column ordering of non-diagonal elements to be placed 0 below diagonal elements in the unitary matrix U corresponding to the n-bit quantum lines according to the first column ordering of the unitary matrix corresponding to the (n-1) bit quantum lines; wherein the ordering of the off-diagonal elements of coordinates (N/2+1, 1) in the first column is located at the last of the first column;
based on the first column ordering corresponding to the N-bit quantum circuit, determining ordering of non-diagonal elements to be placed 0 below diagonal elements in the 2 nd column to the N/2 nd column corresponding to the N-bit quantum circuit respectively;
and correspondingly determining the ordering of the non-diagonal elements to be placed 0 below the diagonal elements in the (N/2+1) th column to the N th column corresponding to the N-bit quantum lines according to the ordering of the non-diagonal elements to be placed 0 below the diagonal elements in the unitary matrix corresponding to the (N-1) bit quantum lines.
4. The method of claim 1, wherein the representation of the single quantum logic gate carrying controlled information comprises:
Wherein the C m Represents a 0, a 1, or a single quantum logic gate V, said m represents a qubit,and there is and only one C m Representing a single quantum logic gate V, a unitary matrix of which is determined by the unitary matrix U;
when C m When the quantum state of the quantum bit of the bit is 0 state before the quantum circuit runs to the single quantum logic gate V, executing the single quantum logic gate V;
when C m When the quantum state of the quantum bit of the bit is 1 state before the quantum circuit runs to the single quantum logic gate V, executing the single quantum logic gate V;
when C m When this is true, it means that the single quantum logic gate V is implemented when the quantum state of the qubit of the bit is arbitrary before the quantum wire runs to the single quantum logic gate V.
5. A quantum wire decomposition device, comprising:
an acquisition module for acquiring unitary matrix corresponding to quantum circuitThe method comprises the steps of carrying out a first treatment on the surface of the Wherein the unitary matrix has an order/>Said->A total number of qubits contained for the quantum wire;
a decomposition module for decomposing the unitary matrixIs building a specific quantum logic gate for the off-diagonal elements of (a)>Unitary matrix of order-providing said unitary matrix- >Break down into->Unitary matrixes corresponding to the single quantum logic gates carrying the controlled information; wherein,the specific The quantum logic gate comprises a single quantum logic gate operating one bit, the single quantum logic gate carrying a controlled bit controlled by the rest of the bits The control information is used to control the operation of the mobile phone,satisfy->Said->For the i-th unitary matrix corresponding to the single quantum logic gate carrying the controlled information,/for the i-th unitary matrix>Said->Said->Is->A rank identity matrix;
an output module for outputting the data including the dataQuantum wires of single quantum logic gates carrying controlled information.
6. The apparatus of claim 5, wherein the decomposition module comprises:
a determining unit for determining the unitary matrixOrdering of non-diagonal elements to be placed 0 below the mid-diagonal elements;
a construction unit for constructing a specific quantum logic gate for the ith off-diagonal element in the orderingOrder unitary matrix->So that the matrix->The element at the same position as the non-diagonal element is set as 0, and the non-diagonal element with set 0 is not changed;
wherein, when saidWhen the unitary matrix of the single quantum logic gate is formed by the unitary matrix corresponding to the quantum circuit>Element determination of (2); when->The unitary matrix of the single quantum logic gate consists of a matrix + - >Element determination of (2); and, when the order of the ith off-diagonal element is the last one of the columns, simultaneously making the matrix +.>The diagonal element in the same column of (1) is set to 1.
7. The apparatus according to claim 6, wherein the determining unit is specifically configured to:
when n=1, the non-diagonal elements to be placed 0 below the diagonal elements in the unitary matrix U are ordered as (2, 1); wherein (2, 1) represents a non-diagonal element having coordinates of row 2 and column 1;
when n is greater than 1, determining a first column ordering of non-diagonal elements to be placed 0 below diagonal elements in the unitary matrix U corresponding to the n-bit quantum lines according to the first column ordering of the unitary matrix corresponding to the (n-1) bit quantum lines; wherein the ordering of the off-diagonal elements of coordinates (N/2+1, 1) in the first column is located at the last of the first column;
based on the first column ordering corresponding to the N-bit quantum circuit, determining ordering of non-diagonal elements to be placed 0 below diagonal elements in the 2 nd column to the N/2 nd column corresponding to the N-bit quantum circuit respectively;
and correspondingly determining the ordering of the non-diagonal elements to be placed 0 below the diagonal elements in the (N/2+1) th column to the N th column corresponding to the N-bit quantum lines according to the ordering of the non-diagonal elements to be placed 0 below the diagonal elements in the unitary matrix corresponding to the (N-1) bit quantum lines.
8. The apparatus of claim 5, wherein the representation of the single quantum logic gate carrying controlled information comprises:
wherein the C m Represents a 0, a 1, or a single quantum logic gate V, said m represents a qubit,and there is and only one C m Representing a single quantum logic gate V, a unitary matrix of which is determined by the unitary matrix U;
when C m When the quantum state of the quantum bit of the bit is 0 state before the quantum circuit runs to the single quantum logic gate V, executing the single quantum logic gate V;
when C m When the quantum state of the quantum bit of the bit is 1 state before the quantum circuit runs to the single quantum logic gate V, executing the single quantum logic gate V;
when C m When this is true, it means that the single quantum logic gate V is implemented when the quantum state of the qubit of the bit is arbitrary before the quantum wire runs to the single quantum logic gate V.
9. A storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of claims 1 to 4 when run.
10. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of the claims 1 to 4.
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| CN112651509B (en) * | 2020-10-14 | 2022-04-22 | 腾讯科技（深圳）有限公司 | Method and device for determining quantum circuit |
| CN112232513A (en) * | 2020-10-28 | 2021-01-15 | 合肥本源量子计算科技有限责任公司 | Quantum state preparation method and device |
| CN114418105B (en) * | 2020-10-28 | 2023-08-08 | 本源量子计算科技（合肥）股份有限公司 | Method and device for processing quantum application problem based on quantum circuit |
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| CN112633508B (en) * | 2020-11-30 | 2024-02-09 | 本源量子计算科技（合肥）股份有限公司 | Quantum circuit generation method and device, storage medium and electronic device |
| CN112561069B (en) * | 2020-12-23 | 2021-09-21 | 北京百度网讯科技有限公司 | Model processing method, device, equipment and storage medium |
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| CN114372539B (en) * | 2022-03-22 | 2022-07-15 | 合肥本源量子计算科技有限责任公司 | Machine learning framework-based classification method and related equipment |
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