KR100442434B1 - Accumulation Method of Array Structure node for Pre-trained Neural Network Design - Google Patents

Abstract

The present invention relates to an efficient design of a trained neural network. The present invention relates to a simplified structure of a complex computational process using a fixed weight and to simplify it. An array structure calculation method for a trained neural network design according to the present invention. Is a first step of expressing a processing element (PE) operation of a neural network by matrix-vector multiplication, and expressing a weight hexahedron (m, n, l) in a bit-level array structure representing a relationship between fixed weights and input data; A second step of calculating an input value and a weight of each node from a weighted hexahedron by a logical product, performing an addition with the previously calculated nodes sequentially, and outputting the total sum up to the final output node; An output layer having an index representing each processing element and an extension index (m, l) receives the output value of the weighted cube and adds it in the l direction, shifts to the right, and adds according to the clock to output the final output value. Characterized in that it comprises a third step.

According to the present invention, the relationship between the fixed weight and the input data is represented by a bit-level array structure, and the node elimination, addition-tree representation, and optimization of the weight bit-pattern are performed without affecting the result. By making the nodes common, we can minimize the nodes required for the entire operation.

Description

Accumulation method of array structure node for pre-trained neural network design

The present invention relates to the efficient design of a pre-trained neural network. In particular, the learned neural network is implemented by expressing a complex computational process in an array structure using a fixed weight and simplifying it. The present invention relates to an array structure calculation method for trained neural network design that minimizes the number of nodes required to reduce hardware cost.

In general, neural networks provide a variety of solutions for solving voice and image recognition, prediction, adaptive processing and optimization problems. To this end, processing elements (PEs), which are artificial models of neurons, are connected in various forms for each application to perform appropriate computational processes. These various network models are not actually implemented because of the lack of optimal means of implementation and the vast computational process, and they are only utilizing the simulation level. Neural networks have high hardware cost and low operation speed due to complex arithmetic.

Processing elements (PEs), which are models of nerve cells, are called artificial models of neurons, units, or cells. In most neural networks, multi-input, one-output elements are commonly used. .

1 is a structure of a processing element, the operation process of the processing element can be expressed as Equation (1).

Where I _n represents the synapse connection between neurons and neurons, and w _{n, m} represents the weight, which is the combined load of the neural network. In addition, n (n = 0,1,2N-1) is the input index of the processing element, and m (m = 0,1,2M-1) is the index representing each PE. O _m is the sum of the inputs, f is the response function, and y _m is the final output value of the processing element transformed and output by the response function.

As can be seen from Equation 1, multiplication of the input vector and the weight vector is required to obtain the output of the processing element. This is a direct problem that raises hardware costs and requires an effective algorithm to solve it. In the past, various multiplier structures are applied to increase efficiency in digital signal processing (DSP) fields such as MAC (Multiply Accumulator), Wallace Tree, Baugh-Wooley, distributed computation, Canonical Signed Digit (CSD), and Multi Constant Multiplication (MCM). Can be. Of these, most algorithms are implemented at the bit-level for speed-up and implementation taking into account the details of parallelism. To this end, if the input value I _n in Equation 1 is expressed at the bit level as in Equation 2, it can be expressed as Equation 3.

The conventional MAC structure for implementing Equation 3 is shown in FIG. The adders 102 and 103 of the N number of MAC (101 ~ 101n) and large (log ₂ N) is required to constitute one of the processing elements. Each MAC 101-101n has an input value ((I _{0, t} ), ..., (I _{N-1, t} )) and a feedback weight ((w _{o, m} ), ..., (w) _{N-1, m} )) is added in the adder 111 and shifted through a shift register 112, and outputted. Two MACs are added in one adder 102 and 103, respectively. Since the outputs of the two different adders 102 and 103 are designed to be added and output again by the adder 104 of the next step, there is a problem in that hardware overhead becomes large.

The learned neural network has a fixed weight. As a more efficient hardware construction method using this, there is a design using distributed computation and CSD. Since the variance operation has a fixed weight, the output value is determined by the input value. Therefore, the output value is calculated in advance and stored in a read only memory (ROM). 3 is a structure of distributed operation using a ROM.

Here, since the address of the ROM 120 is 2 ^N and the maximum bit width is w _{n, m} bit width + log ₂ N, the size of the ROM required for the implementation is 2N * (w _{n, m} bits). Width + log ₂ N) bits. Since distributed operations require a ROM that is exponentially increased by N, it is inefficient for neural network implementations with many interconnections of processing elements.

On the other hand, in the CSD, the weight (w _{n, m} ) rather than the input (I _n ) is extended to the bit-level as shown in Equation (4). In Equation 5, the addition operation for the portion of the fixed weighted bit value of '0' can be eliminated, and if the weighted bit representation is expressed in CSD, the number of portions having the bit value of '1' can be up to L / 2. Since it can be reduced to below, more efficient implementation is possible. 4 shows an example of a PE design using CSD coding. In the case where the weight w _{n, m} is 15, the 6-bit binary and CSD representations are '001111' and '01000-1', respectively. As shown in FIG. 4A, it can be seen that three adders 141 to 143 may be implemented by one subtractor 152 using CSD coding as shown in FIG. 4B.

However, the PE design method using the distributed operation of FIG. 3 requires ROM which is exponentially increased by N, and thus is inefficient for implementing a neural network having many interconnections of processing elements. In addition, the design method using FIG. 4 and the CSD coding has a disadvantage in that an appropriate pipeline design is difficult and an input value is a word unit, and thus the time required for the addition operation is long.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problem, and represents a computational form of processing elements as a set matrix-vector multiplication by using a fixed weight for a learned neural network, which is computed in parallel at the bit-level. It is an object of the present invention to provide an array structure calculation method for trained neural network design.

Another feature is to express the relationship between fixed weights and input data in a bit-level array structure, to make the nodes common through node elimination and addition-tree representations that do not affect the result, and optimization according to the bit-pattern of weights. The purpose is to provide an array structure calculation method for trained neural network design that can minimize the nodes required for the entire operation.

1 is a structure of a processing element which is an artificial model of a general neural network.

2 illustrates a processing element design using a conventional MAC.

3 is a design diagram of a processing element using conventional distributed computing.

4 is a design diagram of a processing element using a conventional CSD.

5 is a diagram illustrating an example of a learned neural network according to an embodiment of the present invention.

6 illustrates an example of bit-level extension of a weight according to an embodiment of the present invention.

7 illustrates an input plane, a weighted hexahedron, and an output plane according to an exemplary embodiment of the present invention.

8 illustrates a structure of a shift adder for bit level addition according to an embodiment of the present invention.

9 is a view showing a structure of an n, 1 weight plane according to an embodiment of the present invention.

10 illustrates an erase structure of a node according to an embodiment of the present invention.

11 is a view showing the structure of an addition tree according to an embodiment of the present invention.

12 illustrates an example of setting a shared node according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

201 ... weighted cube 202 ... input plane

203 ... output plane 210,220 ... node

211 ... Andgate 212,222 ... Adder

221 ... light shift

To achieve the above object, the array structure calculation method for the learned neural network design according to the present invention,

A first step of expressing a processing element (PE) operation of a neural network by matrix-vector multiplication, and expressing a weight cube (m, n, l) in a bit level array structure representing a relationship between fixed weights and input data;

A second step of calculating an input value and a weight of each node from a weighted hexahedron by a logical product, performing an addition with the previously calculated nodes sequentially, and outputting the total sum up to the final output node;

An output layer having an index representing each processing element and an extension index (m, l) receives the output value of the weighted cube and adds it in the l direction, shifts to the right, and adds according to the clock to output the final output value. Characterized in that it comprises a third step.

Preferably, in the first step, after the input value is extended in the l direction to form an input plane, the lowest bit of the input value input to the weighted hexahedron is input first and the most significant bit is input to the last clock. It features.

Preferably, in the second step, when the fixed weight value is 0 or 1 so that all nodes of the input index and the extension index weighting plane of all the processing elements can obtain one output, Erasing step; An add-tree setting step of mapping one to one row of one n, l weight plane; And forming a shared node by expressing the formed predetermined addition trees as a single addition tree for the same output of the same portion in which the bit patterns of the same input weights are received.

Preferably, the node erasing step is characterized in that the weighted value input to each node is 0 or 1, and the AND gate and the flip-flop of the pass path having the input value irrespective of operation are erased and output.

Preferably, the threshold path of the addition tree setting step is configured with all adders equal to the depth of the addition tree, and the carry generated at each node is stored in a flip-flop of the node and added to the all adders at the next clock. do.

Referring to the accompanying drawings, an array structure calculation method for learning neural network design according to the present invention as described above is as follows.

5 shows an example of a learned neural network. A hierarchical network with a single direction from input to output, consisting of input layer nodes (I ₀ , ..., I _N-1 ) and output layer nodes (O ₀ , ..., O _M-1 ), w _{n, m} is a weight obtained through learning. In FIG. 5, a calculation such as Equation 6 is required to obtain the sum value of each processing element corresponding to the dotted line, that is, O _m . In this case _, only the relationship between the input vector I _n , the weight matrix w _{n, m} , and the calculation result O _m is excluded except for the nonlinear function f. This relationship is expressed by the equation (7).

In Equation 6, the weights w _{n and m} and the input I _n are expressed in bit-level using Equation 2 and Equation 4, respectively. In Equation 8, the weight may be extended to a hexahedral shape 201, 202, 203 having three indices of m, n, l as shown in FIG.

FIG. 7 is a detailed structure of FIG. 6 in consideration of parallelism and a black node represents a node having a final output in each array structure.

FIG. 7A illustrates an input plane in which the input bit extends in the l direction so that I _{n and t} are input. The index has n, t but extends in the l direction to fit the input of the weighted cube. Each clock increases t, and at this time, the corresponding I _{n, t} values are extended in the l direction to make n, l input planes, and are input to the weighted cube. At this time, the LSB (Least Signation Bit) is input first and the Most Significant Bit (MSB) is input to the last clock T-1.

7 (b) is a weight hexahedron, each node 210 calculates an input overweight value I _{n, t} * w _{n, m, l} as an AND gate 211, and the calculated value and The adder 212 adds the previously calculated input and weight value I _{n-1, t} * w _{n-1, m, l} . So the final node Is outputted, and each node 210 is composed of one AND gate 211 for bit multiplication and an adder 212 for adding an output value of the previous node.

7C has an index of m, l as an output plane. The output value of the weighted hexahedron is input to add in the l direction. At this time, because the direction is extended to 2 l ^-l old node 220 is a 1-bit right shift (right shift), shifted by 221 light becomes the addition is taken. In FIG. 7, the final output is configured by shift adders 231 and 232 as shown in FIG. 8 and inputs inputs I _{n and t} according to a clock.

In order to simplify the array structure of FIG. 7B, the following three steps are required. The first process of erasing a non-operating node, the second process of forming an addition tree structure, and the third process of reducing the number of shared nodes by sharing a pattern of receiving the same input and outputting the same result are performed.

A first process for erasing the node;

In order to obtain one output O _m in FIG. 7B, related operations for all indexes n and l are required. That is, as shown in FIG. 9, all nodes of one 'n, l-weightplane 240' having an index of n, l are calculated to obtain one output O _m .

In FIG. 9, each node includes one AND gate, an adder, and a flip-flop FF for storing w _{n, m, and l} . Since w _{n, m, and l} are fixed, if the value is '0', the input value of the node is passed as it is. In other words, it can be omitted because it does not operate. In addition, when the value is '1', the input value of the node becomes the result value of the AND gate, and thus the AND gate and the flip-flop of each node may also be erased. 10 shows an example of node erasure, and the number under the node becomes the w _{n, m, l} bit value of the node. FIG. 10A illustrates a structure before erasing a node, and FIG. 10B illustrates a structure after erasing a node.

A second process for addition-tree representation;

Conventionally, the addition result of the left node in the n, l-weight plane has to be added to the right continuously. Therefore, the capacity of the adder required and the signal lines between the nodes increase. In order to solve this problem, an add-tree structure as shown in FIG. 11 is configured. Here, the add-trees are mapped one by one in the n, l-weight plane.

(A) of FIG. 11 is a structure before addition tree mapping, and (b) is a structure after addition tree mapping. In this case, each node is composed of one full-adder (FA) and flip-flop (FF) and all nodes are connected by 1 bit. Carry from each node is stored in the flip-flop (FF) and added to the next clock, so the clock needed for the entire operation is rather long.

A third step for establishing a shared node;

(A) of FIG. 12 is a structure before a pattern shares the same part, (b) is a structure after a pattern shares the same part. Referring to FIG. 12, M add-trees are generated in one n, l-weight plane. Since they receive the same input (I _{n, t} ), where the patterns of w _{n, m, l} are the same, the same result is output. Therefore, as shown in FIG. 12, if the same pattern is expressed by one add-tree and the result value is shared, the total number of nodes can be reduced.

As a result, the fixed weight value is expressed in bit-level by minimizing the nodes of the array structure required for the operation through the node elimination, the addition-tree representation, and the shared node configuration proposed above. have.

Another embodiment of the present invention has a multiplication operation of an input vector and a fixed coefficient matrix as shown in Equation 7 in various algorithms in the signal processing field. Therefore, by expressing this in an array structure and applying the proposed node cancellation, add-tree representation, and shared node configuration, hardware cost required for implementation can be reduced.

As described above, according to the array structure calculation method for trained neural network design according to the present invention, the complex arithmetic operation of each PE of the trained neural network is represented by an array structure and optimized for the configuration node. On-chip neural network implementation of FPGA is possible by minimizing hardware cost and enabling small chip implementation.

Claims (5)

A first step of expressing a processing element (PE) operation of the neural network by matrix-vector multiplication, and expressing a weight hexahedron (m, n, l) in a bit level array structure representing a relationship between fixed weights of the neural network and input data; A second product for calculating bitwise multiplication of the input values and weights of each node from the weighted hexahedron for bit multiplication of each node, sequentially performing addition with the previously calculated node, and outputting the total sum up to the final output node step; A third step of receiving the output value of the weighted hexahedron from the output layer having an index representing each processing element and an extension index (m, l), adding in the l direction, and performing shift addition according to a clock to output the final output value; Including; The second step is the erasing step of the node passing the input value of the node as it is if the fixed weight value is 0 or 1 so that all nodes of the input index and the extension index weighting plane of all processing elements can obtain one output. ; An add-tree setting step of mapping one to one row of one n, l weight plane; And setting a shared node by expressing the formed constant addition trees as a single addition tree for the same output of the same portion in which the bit patterns of the weights of the same inputs are minimized. Array structure calculation method for trained neural network design. The method of claim 1, In the first step, in order to match the input of the weighted hexahedron, the input value is extended in the l direction for each clock to make an input plane, and then the lowest bit of the input value input to the weighted hexahedron is input first, and the most significant bit is input. The array structure calculation method for trained neural network design, characterized in that the input to the last clock. delete The method of claim 1, In the node erasing step, an array structure calculation for the learned neural network design, wherein the weight value input to each node is 0 or 1, and the output value is erased by eliminating the AND gate and the flip-flop of the pass path whose input value is irrelevant to the operation. Way. The method of claim 1, The threshold path of the addition tree setting step includes a full adder as much as the depth of the addition tree, stores the carry generated at each node in a flip-flop of the node, and adds the full adder to the next clock. Array structure calculation method for neural network design.