KR20210105109A - Vector-matrix Multiplication Method and System for using NAND Array - Google Patents

Abstract

Disclosed are a vector-matrix multiplication method and system using a NAND array. In one aspect of the present invention, the vector-matrix multiplication method using a NAND array proposed in the present invention includes the steps of: correcting a mismatch between a reference array and a main array; programming weights into the main array; applying a bit line voltage vector to perform vector-matrix multiplication; and performing a learning algorithm by modifying the weights by further programming cells of the main array to modify a threshold voltage. Accordingly, the present invention can be utilized as an elemental technology of edge computing.

Description

Vector-matrix Multiplication Method and System for using NAND Array}

The present invention relates to a vector-matrix multiplication method and system using a NAND array.

Data movement suppression and localization trends in computing systems include in-memory computing or near data processing. The most efficient data localization can be achieved if the vector-matrix multiplication operation inside the NAND flash with the highest data density can be performed. As an implementation method, a NAND array-using multiplier referring to an array-using vector-matrix multiplication scheme of a cross-point architecture may be used.

A method and system for high-speed vector-matrix multiplication operation are needed in an operation system to which a deep learning algorithm is applied.

An object of the present invention is to provide a vector-matrix multiplication method and system using a NAND array for performing a high-speed vector-matrix multiplication operation in an operation system to which a deep learning algorithm is applied.

In one aspect, the vector-matrix multiplication method using a NAND array proposed by the present invention includes correcting a mismatch between a reference array and a main array, and programming a weight in the main array. , performing vector-matrix multiplication by applying a bit line voltage vector, and performing a learning algorithm by modifying weights by further programming cells of the main array to modify threshold voltages.

When the address of the weight to be modified and the size to be modified are determined, the threshold voltage of a specific cell is modified using the ISPP method.

If the sign of the modified weight change is positive, the threshold voltage of the reference array is programmed.

If the sign of the modified weight change is negative, the threshold voltage of the main array is programmed.

The step of performing the learning algorithm by modifying the weights by further programming the cells of the main array to modify the threshold voltage may be performed by a processor external to the NAND flash.

In another aspect, the vector-matrix multiplication system using the NAND array proposed in the present invention is a reference array and a main array coupled in the word line direction, and each of the reference array and the main array. It includes a control logic and a correction unit for correcting a mismatch by using a difference in output current obtained from the array, and the reference array and the main array are vector-matrix multiplication by programming a weight to the main array and then applying a bit line voltage vector. , and the control logic and correction unit perform a learning algorithm by modifying the weight by further programming the cells of the main array to correct the threshold voltage.

According to embodiments of the present invention, a vector-matrix multiplication method using a NAND array for performing a high-speed vector-matrix multiplication operation in an operation system to which a deep learning algorithm is applied and a computing technology combining a calculation function with a data storage device through the system It is expected to contribute to the development and can be utilized as an element technology of edge computing.

1 is a diagram illustrating a vector-matrix multiplication system using a NAND array according to an embodiment of the present invention.
2 is a diagram illustrating circuits of a reference array and a main array according to an embodiment of the present invention.
3 is a flowchart illustrating a vector-matrix multiplication method using a NAND array according to an embodiment of the present invention.
4 is a graph illustrating dynamic ranges of current and voltage values according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a vector-matrix multiplication system using a NAND array according to an embodiment of the present invention.

A vector-matrix multiplication system using a NAND array includes a data register & D/A converter 110 , a control logic & correction unit 120 , a colum decoder 130 , a rhodecoder 141 and 142 , a reference array 150 , and a main The array 160 includes an A/D converter & data register 170 .

A reference array 150 and a main array 160 are coupled in a word line direction. The control logic and correction unit 120 corrects the mismatch by using the difference in output currents obtained from the respective arrays of the reference array 150 and the main array 160 .

The reference array 150 and the main array 160 perform vector-matrix multiplication by programming a weight in the main array and then applying a bit line voltage vector.

The control logic and correction unit 120 performs a learning algorithm by correcting the weight by further programming the cells of the main array 160 to correct the threshold voltage. According to an embodiment of the present invention, when the address of the weight to be modified and the size to be modified are determined, the threshold voltage of a specific cell may be modified using the ISPP method.

The reference array 150 programs the threshold voltage of the reference array when the sign of the modified weight change is positive.

The main array 160 programs the threshold voltage of the main array when the sign of the modified weight change is negative.

When the main array 160 performs a learning algorithm by modifying the weights by modifying the threshold voltage by further programming the cells, the feed forward algorithm can be performed in a processor external to the NAND flash.

2 is a diagram illustrating circuits of a reference array and a main array according to an embodiment of the present invention.

In the read operation of the NAND array, I _BL represents the read current in the MOSFET linear operation region. The cell enclosed by the dotted line is the selected cell and V _BL is less than _{V WL} -V _{th .}

와 같이 나타낼 수 있고, V_ST는 탑에서의 스위치 전압, V_SB는 바텀에서의 스위치 전압을 나타낸다. I_BL은 하기식과 같이 나타낼 수 있다: Here, the linear mode of operation is

It can be expressed as , where V _ST represents the switch voltage at the top, and V _SB represents the switch voltage at the bottom. I _BL can be expressed as:

와 같이 나타낼 수 있다. 전체 어레이에 인가된 V_BL은 벡터(V_{BL_i}) 로 표현한다. 즉, 각 스트링에 별도의 전압을 인가한다. Referring to FIG. 2 , a NAND array in which a ground terminal of each string is bundled is shown. _{The output current I BL_j} with the sum of the currents of each string is

can be expressed as _{V BL} applied to the entire array is expressed as a vector (V _{BL_i ).} That is, a separate voltage is applied to each string.

After combining the two NAND arrays 210 and 220 in the word line direction, the difference between the output currents obtained from each array is taken. In this case, the left NAND array is referred to as a reference array 210 , and the right NAND array is referred to as a main array 220 . The difference in current obtained in each array is expressed as:

V _th of the vector when the reference array 210 to _{thr_i} V, V _th vector of the main array 220 is shown as V _{th_i.} Consequently, the output current I _{out_j} is proportional to the product of the vector V _{thr_i} -V _{th_i} and the vector V _{BL_i .}

NAND 어레이 두 개를 이용하여

크기의 행렬과 크기

의 벡터 곱을 m 회의 리드 동작을 통해 구현할 수 있음을 나타낸다. 이 때 딥러닝 알고리즘에서 가중치(weight)로 표현되는 행렬의 각 성분은 위 두 개 NAND 어레이 내 대응 되는 셀V_th 들의 차로 구현되고, 여기에 곱해지는 벡터는 비트라인(bitline) 전압을 성분으로 가지는 n 차원 벡터로 구현된다.2 is

using two NAND arrays

size matrix and size

It indicates that the vector product of can be implemented through m read operations. At this time, each component of the matrix expressed as a weight in the deep learning algorithm is _{implemented as the difference between the corresponding cells V th in} the above two NAND arrays, and the vector multiplied therewith has a bitline voltage as a component. It is implemented as an n-dimensional vector.

3 is a flowchart illustrating a vector-matrix multiplication method using a NAND array according to an embodiment of the present invention.

The proposed vector-matrix multiplication method using a NAND array includes correcting mismatch between a reference array and a main array (310), programming a weight in the main array (320), and a bit line It includes applying a voltage vector to perform vector-matrix multiplication ( 330 ) and performing a learning algorithm by modifying weights by further programming cells of the main array to correct a threshold voltage ( 340 ).

In step 310, the mismatch between the reference array (Reference Array) and the main array (Main Array) is corrected.

In step 320, the weights are programmed into the main array.

In step 330, a vector-matrix multiplication is performed by applying a bit line voltage vector.

In step 340, a learning algorithm is performed by modifying the weights by further programming the cells of the main array to modify the threshold voltage.

Since the feed forward algorithm for step 340 is an operation using a small amount of data, it may be performed by a processor outside the NAND flash.

If the address of the weight to be modified and the size to be modified are determined, the V _th of a specific cell can be modified by applying the ISPP method commonly used in NAND flash. At this time, if the sign of the weight change to be corrected is positive _{, program V th} of the reference array, and if the sign is negative, program _{V th of the main array.}

을 증가시킨다. 수정해야 할 가중치 변화의 부호가 음수라면 메인 어레이의 (i, j) 셀을 프로그래밍하고,

을 증가시킨다. For example, if the sign of the weight change to be corrected is positive, program the (i, j) cell of the reference array,

to increase If the sign of the weight change to be corrected is negative, program the (i, j) cell of the main array,

to increase

The above operation is possible in the operating range of the linear region, and the operating range can be designed sufficiently wide considering the reported current-voltage characteristics of the NAND cell.

4 is a graph illustrating dynamic ranges of current and voltage values according to an embodiment of the present invention.

와 같이 나타낼 수 있고, NAND 어레이의 리드 동작에 있어서, I_BL은 MOSFET 선형 동작 영역에서의 리드 전류를 나타낸다. I_BL의 동적 범위는 아래와 같이 나타낼 수 있다: The linear mode of operation is

In the read operation of the NAND array, I _BL represents the read current in the MOSFET linear operation region. The dynamic range of I _BL can be expressed as:

In the selected cell, V _BL is _{less than V WL_S} -V _{th_max} and can be expressed as:

According to embodiments of the present invention, a vector-matrix multiplication method using a NAND array for performing a high-speed vector-matrix multiplication operation in an operation system to which a deep learning algorithm is applied and a computing technology combining a calculation function with a data storage device through the system It is expected to contribute to the development and can be utilized as an element technology of edge computing.

The above description is for a one-time vector-matrix multiplication method. Multiple sequential operations are possible, and detailed design review is required for efficient sequential operation.

Since NAND flash usually has a large capacity of several tens to several hundreds of Gbits, there is a high possibility of improving computational performance through parallel operation of vector-matrix multiplication that fully utilizes the capacity.

Storage computing can lead innovation in big data high-speed computing systems through products that combine NAND flash and computing.

By combining non-volatile data, efficient calculation method using memory array, and parallel operation concept, it is possible to pioneer a new area of technology development in the NAND field.

The device described above may be implemented as a hardware component, a software component, and/or a combination of the hardware component and the software component. For example, devices and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), It may be implemented using one or more general purpose or special purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For convenience of understanding, although one processing device is sometimes described as being used, one of ordinary skill in the art will recognize that the processing device includes a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that can include For example, the processing device may include a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as parallel processors.

The software may comprise a computer program, code, instructions, or a combination of one or more thereof, which configures a processing device to operate as desired or is independently or collectively processed You can command the device. The software and/or data may be any kind of machine, component, physical device, virtual equipment, computer storage medium or device, to be interpreted by or to provide instructions or data to the processing device. may be embodied in The software may be distributed over networked computer systems, and stored or executed in a distributed manner. Software and data may be stored in one or more computer-readable recording media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the embodiment, or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic such as floppy disks. - includes magneto-optical media, and hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible from the above description by those skilled in the art. For example, the described techniques are performed in a different order than the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (10)

correcting a mismatch between a reference array and a main array;
programming weights into the main array;
applying a bit line voltage vector to perform vector-matrix multiplication; and
performing a learning algorithm by modifying the weights by further programming the cells of the main array to modify the threshold voltage.
A vector-matrix multiplication method using a NAND array comprising According to claim 1,
When the address of the weight to be modified and the size to be modified are determined, the threshold voltage of a specific cell is modified using the ISPP method.
A vector-matrix multiplication method using a NAND array. According to claim 1,
If the sign of the modified weight change is positive, the threshold voltage of the reference array is programmed.
A vector-matrix multiplication method using a NAND array. According to claim 1,
If the sign of the modified weight change is negative, the threshold voltage of the main array is programmed.
A vector-matrix multiplication method using a NAND array. According to claim 1,
Performing the learning algorithm by modifying the weight by modifying the threshold voltage by further programming the cells of the main array,
The feed-forward algorithm can be run on a processor outside of the NAND flash.
A vector-matrix multiplication method using a NAND array. a reference array and a main array coupled in a word line direction; and
Control logic and correction unit that corrects the mismatch by using the difference in output currents obtained from the respective arrays of the reference array and the main array
including,
The reference array and the main array are
After programming the weights into the main array, vector-matrix multiplication is performed by applying a bit line voltage vector,
The control logic and correction unit,
By further programming the cells of the main array to modify the threshold voltage, the weight is modified to perform the learning algorithm.
A vector-matrix multiplication system using NAND arrays. 7. The method of claim 6,
When the address of the weight to be modified and the size to be modified are determined, the threshold voltage of a specific cell is modified using the ISPP method.
A vector-matrix multiplication system using NAND arrays. 7. The method of claim 6,
The reference array is
If the sign of the modified weight change is positive, the threshold voltage of the reference array is programmed.
A vector-matrix multiplication system using NAND arrays. 7. The method of claim 6,
The main array is
If the sign of the modified weight change is negative, the threshold voltage of the main array is programmed.
A vector-matrix multiplication system using NAND arrays. 7. The method of claim 6,
The main array is
When performing the learning algorithm by modifying the weights by further programming the cells to modify the threshold voltage, the feed-forward algorithm is
A vector-matrix multiplication system using NAND arrays.

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