RU2006931C1 - System for commutation of processors - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has three commutator matrixes which sizes are Hx(H+1), memory unit matrix which size is Hx(H+2), H devices for input-output control, H multiplexers, H output units, H input units, second group demultiplexers matrix which size is Hx(H+1) and H NOT gates. EFFECT: increased speed due to processing tasks which are partially parallel. 14 dwg

Description

 The invention relates to computer technology and can be used in the development of multiprocessor systems, in particular multimiprocessor.

 A known processor switching system [1], containing a matrix N, (N + 1) data switches, where N is the number of switched processors, a matrix of address multiplexers, a matrix of control multiplexers and a matrix N, (N + 2) memory blocks.

 A disadvantage of the known device is the complexity of its technical implementation.

 The closest in technical essence to the claimed (prototype) is a processor switching system [2], containing a matrix N, (N + 1) of data switches, where N is the number of switched multiplexers, an address multiplexer matrix, a control multiplexer matrix, an N matrix, (N +2), memory blocks, N exchange controllers, two mode control blocks and an element I.

 The disadvantage of the prototype is limited functionality, which consists in the impossibility of solving problems that are not completely amenable to parallelization, that is, tasks in which N microcomputers perform only part of the necessary operations, the rest of the operations can be performed by only one microcomputer. The prototype system, solving completely parallelized tasks, cannot realize the unparalleled mode of operation due to the lack of hardware for synchronizing the beginning of data transfer from the microcomputer, which carries out the unparalleled mode of operation, to the remaining microcomputers of the system when switching to the parallel mode of operation of the system. This narrows the scope of the prototype system; in addition, it is impossible to constructively complete the execution of individual microcomputers included in the prototype system, which does not allow the use of individual microcomputers in stand-alone mode to solve simple problems. This limitation is associated, on the one hand, with the presence of only one clock generator and one reset unit for the entire system and, on the other hand, with the presence of elements that are difficult to attribute to any microcomputer without violating the identity of the technical implementation of these microcomputers (this makes it difficult to manufacture and the use of such microcomputers). These elements include elements I. The specified restriction also narrows the scope of the prototype system.

 There are difficulties in preparing the problem for solution, due to the fact that the program must be created (compiled) in one of the microcomputers of the system and only then manually entered into the remaining microcomputers, since the prototype system does not have hardware to synchronize the start of program transfer from one microcomputer of the system to other microcomputers.

 The purpose of the invention is to improve performance by solving incompletely parallelizable tasks.

 In FIG. 1 shows a functional diagram of a switching system with n = 3; i is 1-3; j is 1-5; in FIG. 2, 3 - schematic diagram of the used demultiplexers; in FIG. 4 is a functional diagram of an exchange control device; in FIG. 5 is an example of a specific implementation of the switches for the three matrixes of switches; in FIG. 6 - the functioning algorithm of the i-th microcomputer system; in FIG. 7 is a block diagram of an interrupt service routine ACCEPT A PROGRAM (PP); in FIG. 8 is a block diagram of an interrupt service routine. CONTINUE SOLUTION (OL); in FIG. 9 is a block diagram of an interrupt service routine START ITERATION (NO); in FIG. 10 - structure of the Fth fragment of the program in parallel operation of the microcomputer system; in FIG. 11 is a block diagram of an interrupt service routine EXIT ITERATION (VI); in FIG. 12 - structure of the Fth fragment of the program with unbranched operation of the microcomputer system; in FIG. 13 is a block diagram of an interrupt service routine ERROR; in FIG. 14 is a timing diagram of an exchange control device.

 Consider an example of a specific implementation of the claimed object for the number of switched processors equal to three (N = 3).

The processor switching system (see Fig. 1) contains the first 3x4 switch matrix 1 processors 2 ₁ , 2 ₂ , 2 ₃ , the second 3x4 switch matrix 3 addresses, the third 3x4 switch matrix 4, the 3x4 matrix of 5 memory blocks, the control device 6 ₁ , 6 ₂ , 6 ₃ exchanges, blocks 7 ₁ , 7 ₂ , 7 ₃ outputs, blocks 8 ₁ , 8 ₂ , 8 ₃ inputs, demultiplexers 9 ₁ , 9 ₂ , 9 ₃ groups, inverters 10 ₁ , 10 ₂ , 10 ₃ , nodes for generating 11 ₁ , 11 ₂ , 11 ₃ signals MASTER / SLAVE (VDSH / VDM), nodes for generating 12 ₁ , 12 ₂ , 12 ₃ signals AUTONOMOUS / SYSTEM (AUT / SIS), matrix Hx (H + 1) demultiplexers, clock generators 15 ₁ , 15 ₂ , 15 ₃ and blocks 16 ₁ , 16 ₂ , 16 ₃ reset.

The system works as follows. Each row of the first matrix of switches, for example, 1 _1.1 , 1 _1.2 , 1 _1.3 , 1 _1.4 , the second matrix of 3 _1.1 , 3 _1.2 , 3 _1.3 , 3 _{1.4 of the} switches, the third matrix of switches 4 _1.1 , 4 _1.2 , 4 _1.3 , 4 _1.4 , blocks 5 _1.1 , 5 _1.2 , 5 _1.3 , 5 _1.4 , 5 _1.5 memory, together with the processor 2 ₁ and the controller 6 ₁ exchange forms the 1st microcomputer. The remaining microcomputers are completely identical to the 1st one, finished in the circuitry sense, and can be made in the form of separate constructs that can be used for autonomous operation outside the system. The completeness of such a microcomputer (in contrast to the prototype) gives the presence of individual sync generators 15 ₁ , 15 ₂ , 15 ₃ and blocks 16 ₁ , 16 ₂ , 16 ₃ reset, which leads to an increase in synchronization inputs in the system and reset inputs. To translate, for example, the 1st microcomputer in the stand-alone mode, it is enough to generate a single signal at the output of the AV ₁ / AVS signal shaper 12 ₁ . The value of this signal can be read by the 1st microcomputer via the input of the third category of input blocks 8 ₁ . In addition, the signal ABT / SIS = 1 disconnects all system lines from the 1st microcomputer, which allows you to go offline without physically disconnecting system lines, that is, without destroying the cable connections of the system.

In standalone mode, each of the 3 microcomputers can be used as a personal one, since it is assumed (as in the prototype) that they all contain standard external devices: keyboard, video terminal, printer, disk drives, etc., which allow enough use all the resources of these microcomputers simply and fully. The node 12 ₁ (12 ₂ or 12 ₃ ) signal generation ABT / SIS (like node 11 ₁ (11 ₂ , 11 ₃ ) signal generation VDSH / VDM) is a series-connected resistor and toggle switch with position lock, connected between the power bus and common bus. The output signal is formed at the junction of these elements. When the toggle switch is on, a zero signal is generated at the output, and when it is off, a single signal is generated. Another feature of the microcomputers under consideration is the presence in their composition of disconnectable memory segments (OSB), which include blocks 5 _1.1 . . . 5 _1.4 , 5 _2.1 . . . 5 _2.4 , 5 _3.1 . . . 5 _3.4 memory. Blocks 5 _1.5 , 5 _2.5 , 5 _3.5 memory are not disconnected and completely belong to the first, second and third microcomputers, respectively. According to the principle of operation, all OSPs are random access memory (RAM), while non-disconnectable memory blocks 5 _1.5 , 5 _2.5 or 5 _3.5 contain both RAM and read-only memory (ROM), which contains parts of the operating system (for example , boot program, external device drivers, etc.). OSB connection / disconnection to processors 2 ₁ , 2 ₂ or 2 ₃ through the corresponding data, address and control lines is carried out using the first matrix of switches 1 _1.1 . . . 1 _1.4 , 1 _2.1 . . . 1 _2.4 , 1 _3.1 . . . 1 _3.4 , the second matrix of commutators 3 _1.1 . . . 3 _1.4 , 3 _2.1 . . . 3 _2.4 , 3 _3.1 . . . 3 _3.4 and the third matrix of commutators 4 _1.1 . . . 4 _1.4 , 4 _2.1 . . . 4 _2.4 , 4 _3.1 . . . 4 _3.4 , which are controlled by the signal generated at the output of the first discharge of the corresponding block 7 ₁ , 7 ₂ or 7 ₃ output (in Fig. 1 is transmitted via wire 4 ₁ ). This signal can be conditionally called EXCHANGE / WORK (O / P). If O / P = 0, then blocks 5 _1.1 . . . 5 _1.4 , 5 _2.1 . . . 5 _2.4 , 5 _3.1 . . . 5 _3.4 memory connected to the internal backbones of their processors 2 ₁ , 2 ₂ , 2 ₃ . So, for example, the information inputs of blocks 5 _1.1 . . . 5 _1.4 memory through the first matrix of switches 1 _1.1 . . . 1 _{1.4 are} connected to the highway 19 ₁ data, address inputs of blocks 5 _1.1 . . . 5 _1.4 memory through the second matrix of switches 3 _1.1 . . . 3 _{1.4 are} connected to the highway 20 ₁ addresses, inputs for writing / reading control units 5 _1.1 . . . 5 _1.4 memory through the third matrix of switches 4 _1.1 . . . 4 _{1.4 are} connected to the control line 21 ₁ . Moreover, blocks 5 _1.1 . . . 5 _1.4 memory (together with RAM, which is part of block 5 _1.5 ) form a single module of the RAM of processor 2 ₁ , all of which cells are available for addressing by their processor 2 ₁ . If the signal is O / P = 1, then the memory blocks 5 _1.1 , 5 _1.2 , 5 _1.3 , 5 _1.4 are disconnected from the internal highways of the processor 2 ₁ , and it becomes possible to exchange data with external devices simultaneously on three channels at once. In the system under consideration, such external devices are other microcomputers, for which they are connected using cables. No other hardware is needed for integrating microcomputers in the system.

In the exchange mode (O / P = 1), blocks 5i, j of the matrix memory through the switches 1i, j and switches 3i, j and 4i, j are connected to each other, forming a chain of blocks 5i, j, where (i = 1.. . N, j = 1... N + 1), of memory. Exchange is allowed only within a certain chain of memory blocks 5i, j and only as follows: one memory block 5i, j of this chain works for reading, the rest for writing. During data exchange during the parallel solution of the problem, the system for reading works in the first chain of memory block 5 _1.1 , and the remaining memory blocks 5 _1.2 , 5 _2.1 , 5 _3.1 - for writing; in the second chain - block 5 _2.2 memory, and the remaining blocks 5 _1.3 , 5 _2.3 , 5 _3.2 - for recording; in the third chain - block 5 _3.3 , and the remaining 5 _1.4 , 5 _2.4 , 5 _3.4 - for recording, as in the prototype, this data exchange mode in the chains of memory blocks 5i, j is provided by the supply of clock pulses that determine the beginning and duration of writing / reading, which are formed at the outputs 23 ₁ , 23 ₂ , 23 ₃ of the write / read control of the corresponding exchange controllers 6 ₁ , 6 ₂ , 6 ₃ , to the read input of the memory blocks 5 _1.1 , 5 _2.2 , 5 _3.3 , from which the data are read, and on recording input of blocks 5 _1.2 , 5 _1.3 , 5 _1.4 , 5 _2.3 , 5 _2.4 , 5 _3.1 , 5 _3.2 , 5 _3.4 memory, in which data is recorded x Data transfer in the 1st, 2nd or 3rd chain of blocks 5 _1.1 , 5 _1.2 , 5 _2.1 , 5 _3.1 ; 5 _1.3 , 5 _2.2 , 5 _2.3 , 5 _3.2 or 5 _1.4 , 5 _2.4 , 5 _3.3 , 5 _3.4 is controlled by control devices 6 ₁ , 6 ₂ or 6 ₃ exchange, the functions of which include:
a) the formation of the rewrite address (generated at the output 22 ₁ , 22 ₂ or 22 ₃ ) for all blocks 5i, j of the memory of the 1st, 2nd or 3rd chain;
b) the formation of clock pulses that determine the beginning and duration of recording / reading (are formed at the output 23 ₁ , 23 ₂ or 23 ₃ );
c) the implementation of a strictly defined number of dubbing cycles, the code of the number of dubbing cycles is loaded into the corresponding controller 6 ₁ , 6 ₂ or 6 ₃ exchange before the start of the exchange;
d) the formation of the signal "END OF EXCHANGE (KO)" when the required number of rewriting clocks is implemented (such a signal with the level of a logical unit is generated at the output of 24 ₁ , 24 ₂ or 24 ₃ signs of the end of the exchange).

In FIG. 4 shows a functional diagram of one of the variants of the control device 6 ₁ exchange that meets the above requirements.

 The circuit includes an output unit 33, a comparison circuit 34, a counter 35, first and second triggers 36, 37, an AND-NOT element 38, an AND-NOT element 39 with an open collector.

Timing diagrams of the operation of the unit are shown in FIG. 14. Before starting the exchange, the first microcomputer (in general, the i-th) must output a code for the number of transmitted data bytes to the output block 33, which is installed on the first information input of the comparison circuit 35; signal O / P = 0. The zero value of the signal O / P provides the zero state of the first trigger 36 (signal a = 0), the zero state of the counter 35 (signal c = 0) and the zero state of the second trigger 37. The signal a zero value closes the And element -NOT 38, which provides an inactive (single) value of signal b at the output 23 ₁ of the write / read control. The zero state of the counter 35 (there is a zero code at the output 22 _{1 of the} rewrite address) provides overwriting from the zero address. The zero state of the second trigger 37 provides an inactive signal value at the output 24 _{1 of the} sign of the end of the exchange. The start of the controller 6 ₁ exchange is provided by a single signal O / P (see time point t _o in Fig. 14).

By cutting the first after the O / P signal transitions to the single state of the clock pulse (see time t ₁ ), the first trigger 36 goes into the single state, which opens the AND-NOT 38 element, at the output of which the write / read control pulses of zero values. On the front of these pulses, the contents of the counter 35 are incremented (see time instants t ₂ ... T ₃₎ , which ensures the sequential formation of rewrite addresses. When the contents of the counter 35 are compared with the code of the number of data bytes transmitted, the signal at the output of the comparison circuit 34 will go to unity (see time point t ₃ in diagram d). This will ensure the transition of the second trigger 37 to a single state after the formation of the last necessary pulse control write / read (see time t ₄ ). In this case, the zero signal at the inverting output of the second trigger 37 closes the NAND element, which prevents the further formation of write / read control signals, and also closes the NAND 39 element with an open collector, which removes the bypass line of the end of exchange sign (it means that moment t ₄ exchange control devices 6 ₂ and 6 ₃ set signs of the end of the exchange). When the O / P signal goes to zero (see time t ₅ ), the initial mode of the device 6 _{1 is} restored.

In FIG. 5 is a functional diagram of one of the embodiments of the node 1.1 of the disconnected memory segment, to which the data switch 1 _1.1 is assigned; multiplexer 3 _1.1 addresses; control multiplexer 4 _1.1 and memory block 5 _1.1 . The multiplexer 3 _1.1 contains a decoder 40, the first and second multiplexers 41, 42. The multiplexer 4 _1.1 contains the first and second multiplexers 43, 44. The data switch 1 _1.1 contains the first and second trunk transceivers 45, 46 (for example, type 589АП26), element NOT 47 and the OR element 48. The decoder 40 (address selector) generates a selection signal for block 5 _1.1 memory and switch 1 _1.1 data. This signal is supplied to the first information input of the multiplexer 41, to the second information input of which a logic zero signal is supplied. The output of the multiplexer 41 is the output of the selection of the multiplexer 3 _1.1 addresses. When the O / P = 0 at the output of the multiplexer 41 there is a signal output from the decoder 40, which may be zero if there has been a coincidence senior six address bits of code generated Process 2 ₁ address unit 5 _1.1 memory (block 5 _1.1 Memory Set) or single otherwise (block 5 _1.1 memory is not selected). When O / P = 1, a zero signal is present at the output of multiplexer 41, which corresponds to the selected state of block 5 _1.1 during data exchange between microcomputers.

The multiplexer 42 commutes the ten least significant bits of the address code of the highway 20 ₁ processor address 2 ₁ (MA9... MA0) or highway 22 ₁ controller address 6 ₁ (KMA9... KMA0). The output of the multiplexer 42 is the output address of the multiplexer 3 _1.1. When O / P = 0 at the output of the multiplexer 42 there is an address set by the processor 2 ₁ , and when O / P = 1 - by the controller 6 ₁ . The multiplexer 43 commutes the write signals to the memory block 5 _1.1 generated by the processor 2 ₁ (the RAM signal on the line 2 ₁ ) or the exchange controller 6 ₁ (the RAM signal passing through the first reverse node 13 _1.1 ). The output of the multiplexer 43 is the recording output of the control multiplexer 4 _1.1 . When O / P = 0, the output of the multiplexer 43 is the signal of the RAM, and when O / P = 1 - KZZZU. The multiplexer 44 switches the read signals from the memory block 5 _1.1 generated by the processor 2 ₁ (the CHTZU signal on the line 2 ₁ ) or the exchange controller 6 ₁ (the KCHTZU signal passing through the first reverse node 13 _1.1 ). The output of the multiplexer 44 is the read output of the control multiplexer 4 _1.1 . When O / P = 0, the output of the multiplexer 44 has a CTZU signal, and when O / P = 1 - KCHTZU. The first information input / output of the data switch 1 _1.1 is the input D1, D0 of the trunk transceivers 45, 46. The second information input / output of the data switch 1 _1.1 is the input / output DB of the main transceiver 45 connected to the processor data line 19 ₁ 2 ₁ (MD7... MD0). The third information input / output of the data switch 1 _1.1 is the input / output DB of the trunk transceiver 46 belonging to the first exchange chain (KMD7... KMDO, harness 26 in Fig. 1). When G / P = 0 information input / output unit 5, a memory _1.1 can be connected to the pipeline data processor ₁₉ January ₁ 2, if the memory unit 5 _1.1 is selected. In this case, a zero signal is generated at the output of the OR element 48, which opens the transceiver 45. If the memory unit 5 _1.1 is not selected, that is, a single signal acts at the output of the address multiplexer 3 _1.1 selection, then the transceiver 45 cannot be opened that eliminates the conflict on the highway 19 ₁ data. At O / P = 0, the transceiver 46 is closed by a single output signal of the element NOT 47. At O / P = 1, the transceiver 45 is closed and the transceiver 46 is open, which ensures the connection of the information input / output of memory block 5 _1.1 to the data highway the first chain of exchange (KMD7.. KMD0, harness 26 in Fig. 1). The direction of data transmission through the open transceiver 45, 46 is determined by the value of the signal at the read output of the multiplexer 4 _1.1 control.

Thus, it is clear that during data exchange during parallel operation of all microcomputers of the system, the information source in the ith chain is the memory block 5i, i, in a specific example, these are blocks 5 _1.1 , 5 _1.2 , 5 _1.3 . The remaining memory blocks 5i, j are information receivers. In the proposed device, this exchange order can be changed (reversed), then all disconnected memory blocks 5i, j of the memory of one microcomputer (we call such a microcomputer master) become sources of information, and information receivers become disconnected blocks 5i, j of the memory of other microcomputers of the system (slaves), belonging to the corresponding chain. The need for reverse arises when transferring programs from a host microcomputer to slave ones, and also when transferring data, when the system switches from an unbranched mode of operation (the task is solved by the host microcomputer) to a parallel mode of operation (the problem is solved by all microcomputers of the system or, in general, by more than one microcomputer). The reverse is carried out using the matrix of demultiplexers 13ii (13 _1.1 , 13 _2.2 , 13 _3.3 ) of the reverse and nodes 14ij (14 _1.3 , 14 _1.4 , 14 _2.1 , 14 _2.4 , 14 _3.1 , 14 _3.2 ). During operation, all microcomputers generate service signals (most of which are for i-th processors: 2 ₁ , 2 ₂ or 2 ₃ interrupt requests):
a) O / P (formed at the output of the first discharge of the output unit 7i of the i-th microcomputer) - determines the operation mode of individual microcomputers of the system. When O / P = 0, an autonomous (independent of other microcomputers) solution of the main or background problem occurs, when O / P = 1, data is exchanged between all microcomputers via N channels at once (memory block chains 5i, j). The exchange is controlled by control devices 6i exchange, and microcomputers without OSB continue to solve the background problem, since they contain both RAM and ROM (memory blocks 5i, ₅ ; 5 _1.5 , 5 _2.5 , 5 _3.5 ). When O / P = 1, not only the OSBs are disconnected from their internal highways, but also the exchange control devices 6i are started, since this signal is supplied to their start inputs;
b) THE DECISION IS COMPLETED (RE, is formed at the output of the second discharge of the i-th microcomputer output port 7i) - determines the degree of completion of the process of solving the problem when executing the next fragment of the program with parallel operation of the microcomputer system. When RE = 0, the conditions for exiting the process of iterative calculations were not satisfied in at least one microcomputer, when RE = 1, the conditions for exiting the process of iterative calculations were satisfied in all microcomputers of the system. The RE signal acts on the control input of the demultiplexers 9i, which allows, depending on the value of the RE signal, to form two requests to interrupt the NR or VI. When RE = 0, a request is generated to interrupt the NR, which is physically created by the KO signal supplied to the information inputs of the demultiplexers 9i. The TO signal is initiated by the signal O / P = 1, which is always generated together with the RE signal (see Fig. 6... 13). Such use of the O / P and RH signals allows one to go to the next fragment of the program only after exchanging the results of the solution by the previous fragment of the program. With РЗ = 1, a request is generated to interrupt the VI;
c) software (is formed at the output of the third discharge of the output port 7i of the i-th microcomputer) - initializes the process of transferring programs from the leading microcomputer to the slave. When PP = 1, a request is generated for interruption of the software, during the course of servicing of which the programs for solving the problem are recorded in the slave microcomputers, which are compiled in the host microcomputer. The value of PP = 0 is passive;
d) PR (formed at the output of the fourth discharge of the i-th microcomputer output port 7i) - initiates the process of transitioning the slave microcomputers to the beginning of a new program fragment when the system transitions from unbranched to parallel operation. When PR = 1, a request is generated to interrupt the PR, during which the slave microcomputers go to the beginning of a new fragment of the program for solving the problem. The value of PR = 0 is passive;
d) OSH (formed at the output of the fifth discharge of the output port 7i of the i-th microcomputer) - initializes the stop of the solution of the problem if an error occurs during the operation of the slave microcomputers. When OS = 0, a request is made to interrupt OS, since it is fed to the inputs of inverters 10i (when OS = 0, a single signal is generated at the output of inverters 10i, which is considered valid for the interrupt input of processor 2i). During the maintenance of the OS interrupt, the host microcomputer receives diagnostic information from the slave microcomputers, analyzes it and informs the operator about the source and type of the error;
e) REVERSE (is formed at the sixth bit output of the i-th microcomputer output block 7i) - sets the reverse mode of operation of the i-th chain of memory blocks 5i, j. With REVERSE = 1 - in the i-th chain the reverse mode of operation is established, with REVERSE = = 0 - the usual mode of operation.

 It must be remembered that the first five outputs of the output blocks 7i (as well as the outputs of the signs of the end of the exchange of the control devices 6i exchange) have an open collector, which makes it easy to integrate individual microcomputers into the system, as well as to unify the composition of individual microcomputers (eliminate the elements that are in the prototype belong to the system as a whole, and not to the microcomputer separately).

 A simplified algorithm for the operation of each individual microcomputer system is shown in FIG. 6. When power is applied (or after pressing "RESET", which is part of the reset unit 16i), the i-th microcomputer prohibits interrupts in order to initialize, then the passive state of the signals is established (block 50): ПП = ПР = О / P = P3 = 0, OR = 1, which is the initial mode for the system. Block 51 checks the value of the AVT / SIS signal, for which it reads the input port 8i and checks the third bit of the entered code. If the value of this discharge is 1, then this means that the microcomputer under consideration should work autonomously and control is transferred to block 57, which allows all interrupts. In this case, the microcomputer operates (block 58) similarly to a personal computer (PC). When solving problems in this mode, the OSBs are connected to the internal buses and are used like regular RAM. Programs of the tasks to be solved can be located anywhere in the address space of the i-th processor 21, taking into account the features of the operating system. If the signal AUT / SIS = 0, then this means that the microcomputer under consideration is connected to the system and control is transferred to block 52, in which the VDSH / VDM signal is checked (in this case, the input block 8i is also read, but the second bit of the entered code is checked) . If the signal VDSH / VDM = 0 (this signal is generated by the VDSH / VDM signal generation block 11i), then the considered microcomputer in the system will be slave and control will be transferred to block 60, in which the active state of the signals PP = PR = 1 is set. This will release the lines PP and PR and allows the host microcomputer to be the only source of these signals in the system. Block 61, allowing interrupts, allows you to proceed to the solution of the background problem (block 62), which may be the user's user task of the i-th microcomputer. The solution of the main task for the system in the slave microcomputers occurs during the processing of the corresponding interrupts (see figures 7. ... 11).

 For the user of the i-th microcomputer, which is slave, the work in the system will manifest itself in a slightly lower speed of solving his task, since the resources of this microcomputer will sometimes be used (in parallel operation of the system) to solve the main problem. To jointly solve the main and background tasks, their programs and working cells should not overlap in the RAM address space, system interruptions should have a higher priority than interruptions necessary to solve the background task, and system interrupt service should begin by storing the general purpose processor registers 2i in the stack , its counter of commands and ends with the return of these values (in Fig. 7... 11 these blocks are not shown conditionally). If the signal VDSH / VDM = 1, then this means that the host in question is the host and control is transferred to block 53, in which the interruptions of the PC and the PR are masked in order to exclude the reaction to requests that the host microcomputer generates only for the slaves. After resolving (block 54) of the remaining interrupts (NI, VI, OS), the host microcomputer begins to receive the task (block 55) from the user of the entire system as a whole. It is assumed that the leading microcomputer's operating system includes a compiler from a high-level algorithmic language that allows for parallel calculations (compilation of the program is part of the functions of block 56). After compiling the program (creating complete programs in machine codes for all N microcomputers of the system), the leading microcomputer transmits the work programs to the slave microcomputers using the request signal to interrupt the software. To transmit programs, chains of memory blocks 5i are used, which in this case are in reverse mode. So, if the host is the microcomputer with number 1, then the program for the i-th microcomputer, respectively, is transmitted along the i-th chain (i = 2. ... N).

 The volume of the transmitted program in one transmission session cannot exceed the volume of the OSP-M. If it is necessary to transmit a sufficiently large program, then the PP signal is transmitted several times, which corresponds to several transmission sessions. The transition to parallel operation occurs after the formation of the leading microcomputer of the PR signal, the exit from parallel operation (transition to the unbranched mode) occurs when all microcomputers generate the signals O / P = 1 and RE = 1. If in the Fth fragment during parallel operation of the system the iterative task is solved and the next iteration is completed, but the condition for exiting the iterative computation process is not satisfied in at least one microcomputer, then this microcomputer generates signals O / P = 1, РЗ = 0, and the system continues the iterative process after exchanging data Islenyev.

 If the problem is solved by the system, then in the absence of a sign of the end of work, that is, with a signal of PRK = 0, a new task for the system is received and solved according to the algorithm described above. In FIG. 7 shows a more detailed algorithm for service interrupt PP. In block 66, the NR interrupt is maximized, which is always formed after the end of the exchange in the system, that is, when the signal KO = 1. This interrupt usually causes a transition to the beginning of the current program fragment. In the case under consideration, when programs are transferred from the host microcomputer to the slave, such a transition is undesirable, if only because a different number of transmission sessions may be required to transfer programs to different microcomputers. In this case, the transition to the beginning of work should occur after the formation of the leading microcomputer of the signal PR = 1, when all sessions of the program transfer are completed.

 In block 67, the REVERSE = 1 signal is issued by all the slave microcomputers at the output of the sixth bit of the output port 7i. These signals are fed through the i-th chains of memory blocks 5i, j to the corresponding inputs of the nodes 13i, j and reverse nodes 14i, j belonging to these chains, preparing them for the reverse transmission of information, i.e., from the host microcomputer to the slave ones. This is achieved by the fact that at nodes 13i, j the reverse signal is fed to the control input of multiplexer 30. When REVERS = 0, the write / read control pulses of the ith exchange controller 6i pass through the output of multiplexer 30, which is connected to the read input of memory block 5i, j (through the inputs KCHTZU multiplexer 44, which is part of the multiplexer 4i, j control). This corresponds to the normal operation of the i-th cell, when the memory block 5i, j is the source of information for the remaining OSBs of the i-th chain. When REVERSE = 1, the write / read control pulses of the ith exchange controller 6i pass through the output of the demultiplexer 30, which is connected to the write input of the memory unit 5i, j (through the input of the RAM of the multiplexer 43, which is part of the control multiplexer 4i, j). This corresponds to a reverse mode of operation, when the source of information in the chain is an SIR belonging to the host microcomputer and a program is recorded in the memory unit 5i, i of the slave microcomputer memory. In nodes 14i, j reverse the REVERSE signal is fed to one of the inputs of the element And 32, the second input of which receives the signal VDSH / VDM. If REVERSE = 1 and VDSH / VDM = 1, then at the output of the And 32 element appears a single level that programs the demultiplexer 31 to transmit write / read pulses of the i-th exchange controller 6i through the output, which is connected to the read input (through the input KCHTZU multiplexer 44, which is part of the control multiplexer 4i, j).

 That is, the SCE belonging to the leading microcomputer (VDSH / VDM = 1) in the reverse mode (REVERSE = 1) is the source of program information for all other SCEs of the i-th chain. In other cases (i.e., when VDShch / VDM = 0) or REVERSE = 0) OSB is a receiver of information. In block 68, the signal O / P = 1 is output at its output, i.e., at the output of the first discharge of the i-th microcomputer output port 7i. When all the microcomputers of the system set this signal, it will appear on the entire line (the operation “mounting AND” will be performed) and all the OSBs will be disconnected from the internal lines and connected in chains, and the exchange controllers 6i will begin to control the exchange process. All microcomputers of the system programmatically monitor the end of this process (blocks 69, 70 in Fig. 7). If the exchange process is completed, then there is a transition to block 71, in which a signal O / P = 0 is issued, which connects all the SCEs to their internal highways. In block 72, the program is rewritten from the OSB to RAM, while the format of the transmitted message is strictly defined, for example, the length of the program -m is placed in the very first cell of the OSB, the start address in the second, and the program package in the next (m-2) cells. If m = M, then the program can be continued, that is, it is not completely entered, if m <M, then it is necessary to analyze the contents of (m + 1) cells. If the contents of the (m + 1) cell is not equal to zero, then this is the code for the length of the next fragment of the program, followed by the starting address and program package of this fragment. If the sum m of all fragments of the program recorded in the OSB is equal to M, then the program is not fully entered. Otherwise, the program is fully entered. All this is checked in block 73. If the program is not completely entered, the slave microcomputer exits the interrupt and continues to solve the background problem, waiting for the next program transfer session.

 If the program is completely transmitted, then the PC interrupt is maximized (block 74), since programs can still be entered into the remaining microcomputers and the PP = 1 signals can be repeated (the reaction of microcomputers that have already finished receiving programs to this interrupt signal is undesirable). In block 75, the reverse signal is taken (i.e., REVERSE = 0), since such a signal is no longer needed in the chain with the completed program transfer process. In block 76, the initial value is set to the counter of program fragments F = 0.

 The value of the counter selects the starting address of the Fth fragment from the table, which is transmitted to the slave microcomputer when transmitting the program. After transferring programs to all slave microcomputers, the host microcomputer executes a program related to the unbranched part of the solution process (if it exists before parallel computing), issues a PR signal, and switches to solving the background problem. Such a task for the leading microcomputer may be a survey of the keyboard. The PR signal for the slave microcomputers is an interrupt request, the service algorithm of which is shown in FIG. 8.

 In block 77 of this algorithm, the O / R and RE signals are reset to set the initial state of the signals on these lines. In block 78, a reverse signal is generated, since it is assumed that before the start of parallel calculations, the initial data for the Fth fragment is prepared in the host microcomputer and must be transferred from there to the slave microcomputer. In block 79, PP and NI interrupts are prohibited that are prohibited in the PP interrupt service routine, after which all microcomputers again become susceptible to these interrupt requests. In block 80, the i-th slave microcomputer transmits to the i-th exchange control device 6i a code for the number of transmitted data (the maximum value of this code is M). In block 81, the signal O / P = 1 is output and the subprogram is exited. When such a signal is issued by all the microcomputers of the system, the system signal is O / P = 1 (the operation "mounting AND" is performed) and the exchange mode appears in the system, which ends with the output of the signal KO = 1 by all exchange controllers 6i. This signal causes a request to interrupt NR (since the signal RE = 0) in all microcomputers of the system, the maintenance of which (see FIG. 9) consists in transferring control to the beginning of the Fth fragment of the program, the structure of which is shown in FIG. 10. In block 82, the reverse signal is taken (that is, REVERSE = 0) since, after solving the Fth fragment, the exchange is carried out in the usual manner. In block 83, the O / R and RE signals are taken - the first to connect the OSB to the internal highways, and the second - since the solution to the fragment is not yet complete. Actually, the decision is made in block 84 and, if there are no errors, the control is transferred to block 86, in which the end of the iteration is checked.

 If the iteration is not completed, then the solution continues; otherwise, it checks (in block 87) that the condition for exiting the iterative computation is satisfied. If the conditions for exiting the iterative calculation process are not fulfilled (the necessary accuracy of the calculation has not been achieved), then there is a transition to block 89, in which the signal О / Р = 1 is generated. When such a signal is set by all the microcomputers of the system, data will be exchanged and, after exchange, at the beginning of the Fth (current) fragment of the program of all microcomputers, i.e., the system begins a new iteration. The process described above proceeds through the following chain of events: O / P = 1 -> exchange -> KO = 1-> request to interrupt NI, since RZ = 0. If the conditions for exiting the iterative calculation process are fulfilled, then RZ = 1 ( block 88) and O / P = 1 (block 89), which causes the exit from the current program fragment by the following chain of events: O / P = 1 -> exchange -> KO = - VI, since RP = 1. It should be noted that after block 89 is executed, the subprogram is exited, i.e., it returns to the solution of the background (user) problem, which is solved, at least in the course of e total exchange time.

 The iterative computation process described above is completely identical to the similar process in the prototype, except for processing computational errors (division by zero, etc.). The prototype lacks hardware to stop computing when errors occur. In the inventive device, in the presence of calculation errors, control is transferred to block 90, in which an error is detected in the host or slave microcomputer. If an error is detected in the slave microcomputer, then control is transferred to block 91, in which the error code is sent to the memory block 5i, i (i-th number of the failed microcomputer) for transmission to the slave microcomputer. After this (block 92), requests to interrupt OSH and NI are masked, the first is because self-interruption is undesirable, i.e., the error code has already been sent to OSPi, i, and this is the content of the routine for processing the request for interruption of OSh, and the second is to so that after exchanging the status codes of the microcomputer (performed during the maintenance of the OS interruption), one should not go to a new iteration, because there are already errors in the solution. In block 93, a signal O / P = 1 is issued to initiate the exchange of microcomputer status codes. In block 94, the signal OSH = 0 is output (at the output of the fifth bit of the output port 7i). This signal immediately triggers a request for interruption of the OSH (the operation "mounting OR" is implemented at the outputs of the fifth category of the output ports 7i). If an error is detected in the host microcomputer, a message about this is issued to the operator immediately after its occurrence (block 95). In this case, the slave microcomputers perform an iteration, and after its completion, having established the corresponding values of the O / P and RE signals, they proceed to solve the user problem.

 It can be seen from the foregoing that parallel computations end with almost simultaneous installation of the signals O / P = 1 РЗ = 1. When these signals are installed by all the microcomputers of the system, a request for interruption of the VI is generated, the service algorithm of which is shown in FIG. 11. In block 96, the counter of fragments F is incremented. In block 97, the status of the microcomputer is checked. If the microcomputer is slave, then the subroutine exits; if the lead, then go to the beginning of the next fragment, the structure of which is shown in FIG. 12. Such a difference in the response to the request for interruption of the VI is due to the fact that the slave microcomputers participate only in parallel computing, and the host microcomputer also performs unbranched parts of the program for solving the system problem. The structure of fragments during parallel operation of the system basically coincides with the structure of fragments that solve unbranched parts of the problem, so blocks 99.. . 101 of FIG. 12 are completely identical to blocks 84.. . 86 of FIG. 10.

 The difference is that after solving the fragment in the program of FIG. 12 (block 102), the end of the solution to the entire system program as a whole is checked, and not the end of the iterative process (block 87 of Fig. 10). If the system problem is not solved, then there is a transition to block 104, in which the counter of program fragments F is incremented; a signal O / P = 1 is issued (block 105), since a transition to parallel operation of the system and the exchange associated with it are assumed. In block 106, the signal PR = 1 is produced, which initiates the transition to parallel operation of the system with new program fragments. If the solution to the system problem is completed, then in block 103, the results of the solution are output. If errors occur during the solution process, control is transferred to block 107, in which an error message is issued to the operator.

 In FIG. 13 shows an algorithm for processing a request for interruption of an OS. In block 108, the request to interrupt the NI is masked, because if an error is detected when solving a system problem, it makes no sense to continue the calculation. The slave microcomputers then react (block 114) by sending the error code to the memory block 5i, i, where the i-number of the slave microcomputer and issuing the signal O / P = 1 to create conditions for exchange in the system. The host microcomputer generates a signal O / P = 1 (block 110), and then programmatically (blocks 111, 112) checks the end of the exchange. Next, in block 113, a signal O / P = 0 is issued, which connects the OSBi, j to the internal lines and analyzes the source and the error code, which informs the operator. (56) 1. USSR author's certificate N 1012232, cl. G 06 F 15/16, 1979.

 2. USSR copyright certificate N 1242977, cl. G 06 F 15/16, 1984.

Claims (1)

 PROCESSOR COMMUTATION SYSTEM, containing from the first to the third matrix of commutators of size H · (H + 1) each, where H is the number of switched processors, a matrix of size H · (H + 2) memory blocks, H exchange control devices and the first group demultiplexer, the first an input unit and an output unit, the first synchronization input of the system being connected to the synchronization input of the first exchange control device, information input-output, address input, and the write write input of the memory block of the ith row of the sixth column of the matrix of memory blocks (where a = 1, ... H, b = 1,..., H + 1) connected, respectively, to the first information input-output of the switch of the ith row of the sixth column of the first matrix of switches, to the first output of the switch of the ith row of the sixth column of the second matrix of switches and to the first output of the switch of the ith row of the sixth column of the third matrix of switches, the a-th information input-output of the system is connected through the a-th data line to the first information input of the a-th exchange control device, to the second information inputs-outputs of the switches of the a-th row of the first matrix of switches and to the inform the memory input and output of the ith row (H + 2) th column of the matrix of memory blocks, the ith address input of the system is connected via the ith address highway to the second information input of the ith exchange control device, to the first information inputs switches of the ith row of the second matrix of switches and to the address input of the memory block (H + 2) of the ith column of the ith row of the matrix of memory blocks, the ith input of the system mode is connected through the ith control line to the first control input of the ith exchange control devices, to the first information inputs to ommutators of the a-th row of the third matrix of switches and to the input of writing / reading memory blocks of the (H + 2) -th column of the a-th row of the matrix of memory blocks, the third information input-output switch of the a-th row of the first column of the first matrix of switches is connected to the third information inputs and outputs of the switches of the kth row of the ith column and the switches of the ith row of the (a + 1) th column of the first matrix of switches (where k = a,. . . , H, b = 1,. . . , a), the second outputs of the switches of the ath row of the sixth column of the third matrix of switches are connected respectively to the inputs of the mode of the switches of the ath row of the sixth column of the first matrix of switches, the second outputs of the switch of the ath row of the sixth column of the second matrix of switches connected respectively to the synchronization inputs of the memory blocks of the ith row of the sixth column of the first matrix of switches, the first output of the ith exchange control device is connected to the second information inputs of the switches of the kth row of the ith column and the switches of the ith row (a + 1)- of the second column of the second matrix of switches, the second output of the a-th exchange control device is connected to the second information input of the switch of the a-th row (a + 1) of the third column of the third matrix of switches, characterized in that, in order to improve performance due to the solution is not completely tasks to be parallelized, it contains second to Hth input blocks, second to Hth output blocks, second to Hth group demultiplexers, a matrix of size H · (H + 1) group 2 demultiplexers and H elements NOT , and the system synchronization inputs from second to Hth to are connected respectively to the synchronization inputs of the exchange control devices from the second to the Hth, the first information inputs of the a-th input block and the a-th output block through the a-th data line are connected to the a-th information input-output of the system, the second information inputs a of the nth input unit and the a-th output unit via the a-th output highway are connected to the a-th information input of the system, the first control input of the a-th input unit and the control input of the a-th output unit through the a-th control line are connected to a - mu system mode input, first output output units are combined according to the "mounting OR" scheme and are connected to the control inputs of the switches of the first, second and third matrixes of switches and to the second control inputs of all exchange control devices, the third outputs of which are connected via the INSTALL OR circuit to the second control inputs of all input units and to information the inputs of all the demultiplexers of the group, the second outputs of all output blocks through the circuit OR OR connected to the control inputs of all the demultiplexers of the group, the first and second outputs of the a-th demultiplexer PPs are connected respectively to the a-th inputs of the first and second groups of the system interruption, the third outputs of all output blocks through the INSTALL OR connected to the outputs from the first to the H-third third group of the system interruption, the fourth outputs of all output blocks through the circuit OR connected to the outputs with the first through the Hth fourth group of the system interruption, the fifth outputs of the first through Hth output blocks through the MOUNTING OR circuit are connected to the inputs of the NOT elements from the first to the Hth, the outputs of which are connected respectively to the outputs from the first to the Hth fifth group interruption of the system, the second output of the a-th exchange control device is connected to the information input of the demultiplexer of the a-th column of the a-th row of the matrix of demultiplexers and to the information inputs of the demultiplexers of the k-th row of the s-th column and p-th row (s + 1) - th column of the matrix of demultiplexers (where c = 1,. . . , H; . . . K = a. . . H, p = 1,. . . , a), the sixth output of the a-th output unit is connected to the control input of the demultiplexer of the a-th row of the a-th column of the matrix of demultiplexers and to the first control inputs of the demultiplexers of the k-th row of the c-th column of the matrix of demultiplexers and to the first control inputs of the demultiplexers of k- of the row of the cth column and the rth row (c + 1) of the column of the demultiplexer matrix, the ith input of the “Master / slave” sign of the system is connected to the third control input of the a-th input unit and to the second control inputs of the demultiplexers a th row of the Tth column of the matrix multiplexers (where T-1, ..., H + 1; T ≠ a, T ≠ a + 1), the nth input of the “Offline / system” sign of the system is connected to the fourth control input of the a-th input unit, the first and the second outputs of the demultiplexer of the ith row of the ith column of the matrix of demultiplexers are connected respectively to the second and third information inputs of the switch of the ith row of the ith column of the third matrix of switches, the first and second outputs of the demultiplexer of the ith row of the Tth column of the matrix of demultiplexers connected respectively to the second and third information inputs of the switch Ator of the ith row of the Tth column of the third matrix of commutators.

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