SU1070536A1 - Swapping device - Google Patents

Abstract

DEVICE FOR INFORMATION EXCHANGE, containing a processor, an element OR NOT, the output of which is connected through a shaper of clock pulses to a synchronizing input of the processor, which specifies a generator, a program memory block, a data memory block, a query storage block, and the first and second elements AND and the first trigger the input-output of the program memory block is connected via the first line to the first input of the processor output, the second input-output of which is connected via the second line to the input-output of the data memory block and input-output In the device storage unit, the output of the first element I is connected to the zero input of the first trigger, and the first input of the second element I is connected to the output of the master oscillator and the first input of the OR-NOT element, characterized in that, in order to speed up the device, A suspend block containing two AND elements and an OR element is entered, and a second trigger is entered in the query storage block, and in the Suspension block the output of the first OR element is connected to the second input of the OR element, and the first and second inputs correspond to In fact, with the outputs of the first and second elements I, the first inputs of which are connected respectively to the first and second controlling outputs of the controller, and the second inputs respectively to the single outputs of the first and second triggers and the request buses of the first and second highways are connected respectively with the first and second outputs of the processor requests, the first input of the first element I is connected to the output of the master oscillator, and the second input - to the readiness bus of the first line, the second input and the course of the second element I is connected respectively to the readiness bus of the second highway and the zero input of the second trigger, and the processor contains the current instruction address register, the first adder, the microoperation decoder, two transition address registers, two exchange operation code registers, seven AND elements, two triggers, two OR elements, bu .ferner register of instructions, two nodes of bus drivers, two commuta-. torus, two switching-elements, a storage register of the current instruction and a microprogram memory, a buffer data register, an arithmetic logic node and a register node: this is operational information, the first information inputs of the first and second adders are connected respectively to the output of the register the current instruction and the output of the operational information register node, the outputs — respectively, with the information inputs of the first and second transition address registers, the information input / output of arithmetic nodes a processor connected via an internal line to an information input-output unit registers the operational information, to the outputs of a storage register TEKU

Description

instruction and a buffer data register, with the second information inputs of the first and second adders, the first input of the first element AND is connected to the output of the first element, OR, and the output is a single input of the first trigger whose output is the first controlling output of the processor, the first input the first OR element is connected to the first output of the micro-operation decoder and the first inputs of the second and third AND elements, the output of which is the first output of processor requests, the second input of the first OR element is connected to the second the output of the micro-operation decoder and the control register input of the address of the current instruction, whose information input is connected to the output of the first register of the transition address, the control input connected to the output of the second And element, the control input of the first code register, the exchange operation and the first information input of the first switching element, whose control input is connected to the output of the first register of the exchange operation code and the control inputs of the first node of the bus drivers and the first switch, the first The information inputs of the first and second switches are connected to the information input / output of the operational information register node, the second information inputs are respectively to the outputs of the first and second bus driver nodes, the information inputs of which are connected respectively to the outputs of the buffer instruction register and the buffer data register, whose information inputs are connected respectively, with the outputs of the first and second switches, and control cadia inputs, respectively, with the outputs of the first and second switches informational inputs of the first and second registers of the exchange operation code are connected respectively to the first and second group of outputs of the micro-operation decoder; the second output of which is connected to the first input of the fourth element AND, the third and fourth outputs - respectively to the first and second inputs of the second element OR and the first the inputs of the fifth and sixth elements, the output of which is connected to the control inputs of the second register of the transition address, the register of the exchange operation code and the first information input of the second the switching element, the control input connected to the control inputs of the second switch and the second node of the bus drivers, the output of the second element OR is connected to the first input of the seventh element AND, the output connected to the single input of the second trigger, the output of which is Poro and the output of the fifth element AND are respectively the second controlling output and the output of processor requests, the output of the second register of the transition address and the second register of the exchange operation code, the information input-output of the second bus node is formed The second information input of the second switching element and the second input element of the processor, the control inputs of the operational information register, the second adder, the arithmetic logic node, the control input group and the output group of the arithmetic node, are connected to the fifth-seventh outputs, the third a group of outputs and the first group of inputs of the micro-operation decoder, the seventh output of which is connected to the control input of the first adder, and the fourth group of outputs and the second group of inputs - respectively to the first address input of the microprogram memory and the output of the storage register of the current instruction, the control input of which is connected to the output of the fourth AND element, and the information input to the second address input of the microprogram memory and output of the buffer register of instructions, outputs of the first register of the transition address register and the exchange operation code register, the information input / output of the first node of the bus drivers and the second information input of the first: switching element form the first input-output of the processor, the second The inputs of the first to seventh And elements, the zero inputs of the first and second triggers, the synchronization inputs of the program memory and the micro-operation decoder are connected to the processor's synchronizing input, the output of the microprogram memory is connected to the third group of micro-operations decoder inputs.

The invention relates to computing and can be used in computer systems with asynchronous exchange.

information between system complexes.

Devices for information exchange are known, containing an encoder, an exchange synchronization unit, an information register, an OR element, and a group of exchange channels, each of which consists of a channel preparation unit, a request processing unit, a current address counter, and an SP control unit,

The disadvantages of these devices are high hardware costs and low performance.

The closest in technical essence to the present invention is an information exchange device comprising a processor, the input-output of which is connected via a trunk to the input-output of the device and the input-output of the memory unit, the driver of clock pulses, the first input connected to the output of the switch, and the first output with a processor input, a master oscillator connected by the first output to the first input of the switch, and a control unit consisting of a trigger, two AND elements and an OR element, with the first input of the first AND element dinene processor output, the second input and output, respectively, with the second output and input of the clock generator and the first trigger input, the output connected to the second input of the switch, and the second input to the output of the second element And, the first input of which is connected to the second output of the master oscillator, and the second input - with the output of the element OR; the first and second inputs of which are connected respectively with the output of the memory block and the readiness input of the device G21.

The purpose of the invention is to increase the speed of the device.

The goal is achieved in that a device containing an OR-NOT element, the output of which is connected through a clock generator to the synchronization of the processor inputs, specifies a generator, a program memory, a data storage unit, a query storage unit, including the first and second elements AND the first trigger, the input / output of the program memory block is connected via the first line to the first input-output of the processor, the second input-output of which is connected via the second line to the output-output of the block, the data memory and the input-to the output of the device, in the query storage unit, the output of the first element I is connected; with the zero input of the first trigger, and the first input of the second element AND is connected to the output of the master oscillator. and the first input of the element OR NOT, a pause block is inserted, containing two

And element and OR element, and the second trigger is entered in the query storage unit, and in the block suspending the output of the first element OR is connected to the second input of the OR-NOT element, and the first and second inputs are corresponding to the first and second elements AND, the first inputs of which are connected respectively to the first and second controlling outputs of the processor, and the second inputs - respectively to the single outputs of the first and second triggers and the query theories. the first and second highways, the single inputs of the first and second triggers are connected respectively to the first and second outputs of the processor requests, the first input of the first element I is connected to the output of the master oscillator, and the second input is from the first readiness of the first | and the output of the second element And connected respectively to IjFHe readiness of the second line and, zero input of the second trigger, and the processor contains the address register of the current instruction, the first adder, the decoder of microoperations, two registers of the transition address, two registers of the exchange operation code, seven. And elements, two triggers, two OR elements, an instruction buffer register, two bus generators, two switches, two switching elements, the current instruction storage register, a microprogram memory, a buffer data register, an arithmetic logic node, and an operative information register node, the information inputs of the first and second adders are connected respectively with the output of the current instruction address register and the output of the operational information register node, the outputs are respectively with information 5 "1 and I The first and second addresses of the transition address registers, the information input / output of the arithmetic logic node are connected via the processor's internal trunk to the information input / output of the operational information registers node, with the outputs of the storage register of the current instruction and the buffer register, with the second information inputs of the first and second adders , the first input of the first element AND is connected to the output of the first element OR and the output is connected to the single input of the first trigger, the output of which is the first controlling output% row, the first input of the first OR gate is connected to the output of the decoder pervt micro and first inputs of the second and third AND elements, whose output is the first output terminal of the queries, the second input of the first OR gate is connected

with the second output of the micro-operation decoder and the control input of the current instruction address register, whose information input is connected to the output of the first register; the transition address that controls the input connected to the output of the second And element, the control input of the first register of the exchange operation code and the first information input of the first switching element whose control input is connected to the output of the first register of the code of exchange operations and the control inputs of the first node of the bus drivers and the first switch, the first information inputs of the first and second switches are connected to the information input / output of the operational information register node, the second information inputs are respectively with the outputs of the first and second bus driver nodes, the information inputs of which are connected respectively to the outputs of the buller register of instructions and the buffer register of data, whose information inputs connected to the outputs of the first and second switches respectively, and the control inputs respectively with the outputs of the first and second The switching elements, the information inputs of the first and second registers of the exchange operation code are connected respectively to the first and second group of outputs of the micro-operation decoder, the second input is connected to the first input of the fourth element AND, the third and fourth outputs - respectively to the first and second input of the second element OR and the first inputs of the fifth and sixth elements And, the output of which is connected to the control inputs of the second register of the transition address, the register of the code of operations of the exchange and the first information input of the second the switching element, the control input connected to the control inputs of the second switch and the second node of the bus driver, the output of the second element OR is connected to the first input of the seventh element AND, the output connected to the single input of the third trigger, whose output and output of the fifth element AND are respectively, the second controlling output and the output of processor requests, the outputs of the second register of the transition address and the second register of the exchange operation code, the information input-output of the second bus node form ovateley and second information input of the second switching element constitute the second input-output processor, the node control inputs operational information of registers, the second adder, Arithmetic logs

the arithmetic node, the group of control inputs and the group of outputs of the arithmetic unit are connected respectively to the fifth-seventh outputs, the third group of outputs and the first group of inputs of the micro-optocounter, the seventh output of which is connected to the control input of the first adder, and the fourth group of outputs and the second group of inputs correspondingly to the first address input of the microprogram memory and the output of the storage register of the current instruction, the control input of which is connected to the output of the fourth AND element, and the information input the second address input of the microprogram memory and the output of the buffer register of the instruction, the outputs of the first register of the transition address and the register of the exchange operation code, the information I / O input-output of the first node of the bus drivers and the second information input of the first switching element form the first input-output of the processor, the second inputs the first and seventh elements And, the zero inputs of the first and second triggers, the synchronizing inputs of the program memory and the micro-operation decoder are connected to the synchronizing input of the processor, the output n m ti firmware coupled to the third group of inputs of the decoder microoperations.

FIG. 2 is a structural block diagram of the device. FIG. 2 is a functional diagram of the register for storing queries and the blocking suspension. FIG. 3 is a block diagram of the processor; figure 4 is a functional diagram of the processing unit processor; FIG. 5 is a functional diagram of a processor data processing unit; FIG. 6b is a functional diagram of a clock generator; FIG. Fig. 7 is a timing diagram of the operation of the device; Fig. 8 is a block diagram of an instruction execution algorithm; figure 9 - the timing diagram of the device when executing the instructions.

The device contains (figure 1) processor 1 ,. Designed for processing data in accordance with the loaded program (the processor 1 is the master in the device, the master oscillator 2, which provides the generation of high frequency pulses, determined by the speed of the element base; Shaper 3 clock pulses, generating the clock pulses 1, an OR-NOT 4 element that allows blocking the passage of high-frequency pulses to the input of a synchro shaper 3, request block 5 is necessary x for storing requests for the duration of their execution; block 6 suspending, blocking the supply of high-frequency pulses to the driver 3 for the time of verification of the exchange operation by the slave; block 7 of program memory for storing programs written in the instructions of the processor 1; block 8 of the data memory required for receiving user programs, storing intermediate results of processing, as well as the service information required for the operation of the operating system.

The first line 9 provides communication between the processor 1 and the program memory block 7, the second line 10 with the data memory block 8. In addition, through the second line 10, the connection of processor 1 with external devices (magnetic disk drives, tapes, displays with electromechanical input-output devices), the set of which is chosen by the user, is connected. All external devices are connected in parallel to the block 8.

The units and devices connected to lines 9 and 10 are slave. Each of the trunks 9 and 10 includes address buses for transmitting the address to the slave device, bi-directional data buses for transmitting the recorded word to the slave device and sending the requested word to Processor 1, a request for sending the slaves to the slave device, and a readiness bus for transmitting to the processor 1 a ready signal, an operation bus for indicating to the slave device the type of operation to be performed (read or write) and an initial reset bus for resetting the slave device. BJJOK 5 queries contains (figure 2) triggers 11 and 12 elements And 13 and 14. Block 6 suspension consists of elements And 15 and 16 and the element OR 17 (figure 2).

The processor 1 contains two structural blocks (FIG. 3): an instruction processing block 18 and a data processing block 19, an internal highway 20, the register 21 of the address of the current instruction, the first adder 22, a decoder 23 microoperations, the first register 24 of the transition address and the register 25 of the code exchange operations, the first element AND 26, the first trigger 27, the second element AND 28, the first element OR 29, the third element AND 30, the buffer instruction register 31, the first node 32 of the bus driver, the switch 33, the switching element 34, the current register 35 instructions, fourth The second element 36, the microprogram memory 37, consisting of the accumulator 38, the address register 39 and the micro-operation register 40, the microprogram memory output bus 41, form the processor instruction processing unit 18 (Fig. 4). The arithmetic logic unit 42, the operative information register node 43, the second adder 44 and the transition address register 45, the sixth element And 46, the second, the register 47 of the exchange operation code, the node

10 48 bus drivers, switch 49 and switching element 50i buffer data register 51, second element OR 52, fifth element H 53, second trigger 54 and seventh element

5 and 55 form the processing unit 19 of the processor 1 (FIG. 5).

The shaper 3 clock pulses contains (6) the shift register 56 and the elements And 57-59.

Q Register 21 provides storage of the address of the current instruction during its execution. Dp forming the address of the next instruction. adder 22 is used which

5 is connected by the first info1 input (A) to the output of register 21, the second information input (B) to the internal highway 20, and the control input to the eighth output of the bus decoder 23 and the shaping signals

instruction addresses (FII), which provide the sukmator with 22 functions of incrementing the address set at input A by +1 or by the value passed to input B, while the address is equal to one of the input values. Register 24 is used to store instructions in the process of accessing block 7 of program memory. Register 25 provides storage of the exchange operation code (sample, load) and is connected by an information input to the output of the decoder 23 by the OP1 signal bus, set to the type of exchange operation with the unit

5 7. Element And 26 provides the formation of a signal receiving codes in registers 24 and 25. The output of register 24 is connected to the address buses — the first highway 9 and the information window of the NE of the register 21.

The first output of the requests of the processor 1 is the output of the AND 30 element (RFR1), which provides the formation of the exchange request signal via the highway 9, for initiating of which the output of the decoder 23 VCM1 is provided.

To store the instruction during its execution, a register 35 is used, which is connected by an information input to the output of the buffer register 31 and a control input to the output of the AND 36 element connected by the first input to the CONI bus (end of instruction) of the second output

5 decoder 23. Register outputs 35

connected to the inputs of the second group of the decoder 23 to control its operation. And to the internal highway 20 to issue part of the bits instructions to the inputs of other units of processor 1, in particular to the inputs B of the adder 22.

Firmware implementing the instruction set of processor 1 is stored in memory 37, consisting of accumulator 38, address register 39 and microcommand register 40 connected by outputs of the third group to decoder inputs 23, and information inputs to outputs of accumulator 39 connected by address inputs with the outputs of the address register 39, the inputs of which are connected by buses of starting addresses for accessing the micro-command, from which the next instruction starts, to the outputs of the buffer register 31, and by buses of signals for changing the address of the mic command - to the outputs of the fourth group of the decoder 23.

Arithmetic logic unit 42 converts numeric and alphabetic information and is connected to the internal highway 20 by input and output data buses, and outgoing buses of branch condition (SW) to the inputs of the first decoder group 23, the third group of outputs and the seventh output, which is connected by signal buses arithmetic logic microoperations (AL) and microoperation buses of internal exchange (BO1) with a group of control inputs and a control input of the arithmetic logic node 42.

Node 43 is provided for storing operational information in processor 1, connected by input and output data buses to internal backbone 20, output data buses (DAN) to the input of switch 23, control inputs to the fifth output of the decoder 23 buses of internal exchange signals, and the output busses of the base address are connected to the input of the adder 44, which is connected to the input B to the internal highway 20, and the control input to the sixth end of the decoder 23 through the buses of the TA signals that determine the type of addressing (absolute, relative a). The adder 44 provides for the generation of the executive address during the exchange operations on the second highway 10. A register 45 is provided for storing the address during the exchange on this highway, which is connected by an information input k to the output of the adder 44, output. home to the address buses of the second highway 10, and the control input — to the output of the AND 46 element connected to the control input of the register 47 for storing the exchange operation code and the information input connected to the second output of the decoder 23 by the OP2 signal bus (operation code -exchange on the second highway 10 - reception or issue), and output to the bus operation of the second highway 10 and to the control inputs of the bus drivers of node 48, switch 49 and switching element 50. Bus formers of node 48 are connected to bi-directional buses am data of the second highway 10.

Buffer register 51 provides data storage during the exchange of information on the second highway 10. The output of the exchange request on the second highway 10 is the output of the element 53. To initiate the requests, a fourth output of the decoder (OBM2) is connected to the inputs of the elements 53 and 46 and element OR 52.

The second controlling output of processor 1 (KT2) is the output of flip-flop 54, the unit input through which elements 55 and OR 52 receives the signal from the third output of the decoder 23 via the micro-operation bus of outputting the contents of the buffer register 51 to the internal highway 20 ()

For clocking the processor 1, the synchronization inputs of the decoder 23 are connected to the outputs of the imaging unit 3 sync pulses by sync pulses SI1, -Si2, PPE, input elements And 28 and 55 buses sync pulses SI1, zero triggers inputs 27 and 54, as well as the outputs of elements 26, 36 and 46 - buses of sync pulses SI2, control input of register 40 and inputs of elements I 30 and 53 - buses of sync pulses of PPE.

Shaper 3 sync pulses (fg.6) consists of a shift register 56 for three bits and AND 57-59 elements, the outputs of which are the outputs of shaper 3 (CI1, CI2, PPE). The inputs of elements 57-59, interconnected and with the shift input of the right C1 of the shift register 56, are input 60 of the generator 3. For a cyclic shift, the input TO, which is the input of the sequential recording of information in the shift register 56, is connected to the output of its third digit Yes . The first bit input of the shift register 56 D1, as well as the left shift input C2 is connected to the bus of the logical unit, the inputs of the remaining bits D2, D3, Di are connected to the bus of the logical zero, and the parallel splinter input serves to reset the shift register 56 to its initial state equal to binary code 100.

Items 67-70 (Figures 8 and 9) denote the elements of the flowchart.

The device works as follows. The master oscillator 2 continuously receives high-frequency pulses | CIO, psx; stupid to the pulse input of the element OR-NOT 4 and to the inputs of the elements 13 and 14. When the processor 1 executes microcommands that do not require turning to the slave devices, the pulses are high the frequencies from the output of the OR-NOT 4 element are fed to the input of the generator 3, which provides frequency division and generation of a series of clock pulses SI1, SI2, PPE (fig. required for the operation of processor 1. Processor 1 consists in sequentially selecting instructions from block 7 and them in Execution in accordance with the firmware, each of which is a sequence of microcommands that implement the corresponding instruction. The required firmware is called from memory 37 by specifying the code of the starting address entering the address register 39 from the outputs of the buffer register 31. The micro instruction is executed during one clock cycle , shown in Fig. 9. The execution of the micro-command consists in the fact that at the time of generating the synchro impulse SI1 in accordance with the code read into the register 40, on certain buses of microoperations of phon The signals that come to the inputs of the corresponding elements and nodes of processor 1 are generated. During the entire clock cycle, processor 1 performs the actions prescribed by the microcommand. The arrival of the sync pulse SI1 to the input of the decoder 23 initiates the address of the regular microcommand to the input of the address register 39. The code of the next micro command is read from accumulator 3 and with the end of the sync pulse PPI enters the register 40. A sample of the next instruction is initiated during the execution of the current instruction by micro-instructions, in which, in addition to the micro-operations required to fulfill the current instruction, micro-operations MBM1, OP1, and FII are indicated. When such a microcommand is executed, the signal OBM1 is transmitted through the element OR 29 to the input of the element AND 28, and the sync pulse SI1 sets the trigger 27, as a result of which the input of the element 15 enters the level of the logical unit. Usually, at this moment, the precursor call to block 7 is completed, therefore, trigger 11 is reset and blocks the passage of the logical unit signal to the output of the element 15. At the same time, the FAI signals form the address of the requested instruction at the outputs of the adder 22. By synchronizing the pulse CI, trigger 27 reset to the register 24 rewrites the address from the outputs of the Adder 22, and to the register 25 the code O corresponding to the operation of the sample (OP1 0). Thus, the address of the requested instruction is set to the address busses of the first highway 9, and the sample operation code is set to the bus of the operation of this highway. After a time interval sufficient for decoding the set address, using the SIZ sync pulse, element I 30 generates a request signal for PRL1, as a result of which TRL-er 11 is set to one and from the output to block 7, the request signal REQUEST 1 comes in. From At this point, the processor 1 and block 7 work in parallel: after initiating a sample of the next instruction, processor 1 continues to execute the current instruction stored in register 35. After completing the sample, the instructions on the bi-directional data bus of the first meter The lines 9 to the processor 1 from block 7 will receive the read instruction, which by bus drivers of node 32 and switch 33 under the control of the code in register 25 is transferred to the buffer register 31. At the same time, the ready signal (GOT1) will be sent to the input of switching element 34; which ensures that the read instruction is accepted into this register. The readiness signal also arrives at element I 13 and, using the sync pulse of the SIO generated by master oscillator 2, resets trigger 11. The execution of the current instruction, which runs parallel to the sample of the next instruction, ends with a micro instruction, and processor 1 is prepared to execute the next instruction. This preparation is performed by a micro-operation signal (GONI), which is transmitted via the synchro impulse SI1 through the elements OR 29 and AND 28 to the single input of trigger 27, which leads to the development of the level of the logical unit and the input of the element 15. If by this time the instruction has been completed and the trigger 11 is cleared, the signal is not generated and the next instruction is transferred from the buffer register 31 to the register 35 using the clock signal CI2. In addition, the address of this instruction comes from register 24 to register 21, The initial address of the firmware implementing this instruction is transferred from the buffer register 31 to the address register 39, after its processor 1 proceeds to execute the first microcommand of the current instruction.

If by the time the instruction completes, the next instruction is not completed, the level of the logical unit from the output of the trigger 27 is transmitted through the elements AND 15 and OR 17 to the control input of the OR-NOT 4 element, which blocks the passage of the impulse impulse output from the master oscillator 2 to the input shaper 3, and further shaping of synch pulses CI, CI2, PPE is stopped, which leads to processor suspension 1. Formation of clock pulses resumes after resetting trigger 11 with GOT1 ready signal, gated and The impulse of the SIO arriving at the input of the element And 13. The first is formed the sync pulse CI2 which passes through the element 36 and ensures the reception of the Read code into the register 35. Then the starting addresses of the program implementing this instruction are transmitted to the address register 39 and the processor 1 proceeds to execution first microinstructions -instructions.

Suspension also occurs if, by the time the microcommand initiating the instruction is executed, block 7 has not generated the ready signal GOT1 in response to the previous request. Such a situation arises if, when executing a branching microprogram, a proactive request for an instruction was made, the transition to which was not followed, and its sampling time exceeded the time of movement in the microprogram before accessing the instruction required to exit through this branch of the microprogram.

The loading of block 7 is carried out by a special instruction, which operates as follows. The buffer register 51 from the second highway 10 receives the code that needs to be loaded into block 7 and is transmitted to the node 43 via the internal highway 20. Then, a micro-instruction is executed that indicates the microoperations MBC1, FIU and OP1, and the microoperations FII define the output assignment function an adder 22 of the value received at its inputs B. As in the sample instruction, the readiness of block 7 is performed using the synchronization pulse SI1, and the request is fulfilled, using the synchronization pulse SI2 to the register 24 from the internal highway 20 from the adder 2 2 rewrites the address of the instruction being written, and register 24 sets the code 1 corresponding to the load operation, thereby setting the address and operation code on the address buses and on the operation buses of the first line 9. At the same time, using the BO2 microoperations, the code of the instruction being written goes to the output data buses of the registers node 43 and under

control register 25 through the switch 33 is transmitted to the information input of the buffer register 31, signal OBM1, transmitted over the synchronization pulse SI2 through the element And 26 | and switching element 34, the instruction is written to this register and using the bus drivers of the node 32 is exposed to bidirectional data buses the first line 9. Then, on the SIZ sync pulse at the output of the element I 30, a request signal ZPR1 is generated, which sets the trigger 11 into one unit, which provides the transmission from the request signal REQUEST 1 to block 7. After This execution of the loading instruction continues — it checks whether it is necessary to continue loading, and if necessary to continue in the buffer register 51, the next load code is prepared. At the same time, unit 7 executes the initiated loading operation.

If by the time block 7 has not yet responded with a ready signal GOT1 to the previous request, then the generation of clock pulses CI, CI, PPE is stopped until the output of block 6 has reached the level of logical zero. After the transfer of the entire sequence of instructions to block 7 is completed, the operation of the loading instruction ends with a selection of the next instruction and preparation of processor 1 for its execution.

The request for accessing block 8, as well as external devices connected to the second line 10, is specified by the micro-operation MBO2, and the method for determining the effective address is indicated by the TA control code (addressing type), and the register of the node 43 used in determining the effective address is indicated microprocesses of intraprocess exchange B02.

During the operation of loading micro-operations, BO2 also indicates the register containing the data transmitted by processor 1. The OP2 microoperation, which determines the direction of data transfer, has a logical unit value when loaded. Preliminary, the base address is written into the registers of node 43, as a result of which its value is maintained at the inputs A of the totalizer 44 during the execution time of a significant portion of the program.

The word is sampled from block 8, as well as from another device connected to the second line 10, as follows.

in the process of executing instructions, the memory 37 reads a micro-command that specifies the TA, B02 micro-operations, which, together with the base address set in the registers of node 43, ensure the generation of an effective address at the outputs, sum-. torus 44 at the time of termination of the sync pulse SI1. The micro-command also specifies the micro-operation of the exchange OBM2, which ensures the level of the logical unit at the output of the element OR 52, which leads to the passage of the clock pulse SI1 through the element 55 and the installation of the trigger 54, the level of the logical unit from the output of which goes to the second controlling input of the element 16. at this moment is in the single state, which indicates the incompleteness of the previous circulation, then the input of the fs-driver 3 through the elements AND 16 and OR 17 receives the signal of the logical unit, which leads to suspend shaping sync pulses by shaper 3.

After the time required to complete the previous call, the slave device generates a GOT2 ready signal, which, according to the sync pulse generated by master oscillator 2, flushes the trigger 12, which leads to the establishment of a logic zero level at the output of block 6 and continuing to generate synchro pulses SI1, SI2, PPE the first being produced by the sync pulse SI2. This sync pulse resets the flip-flop 54 and generates a signal at the output of the I 46g element providing reception of the executive address with the output of the adder 44 to the register 45 and the opcode of the sample equal to zero in the register 47. The code from the outputs of the registers 45 and 47 goes to the address buses and the bus operation of the second line 10. The sync pulse PPE at the output of the element And 53 produces a pulse exchange request (ZPR2), which sets the trigger 12, which ensures the transmission of the query signal REQUEST 2 via the query bus of the second highway 10. Next, the CPU 1 proceeds to the next microinstruction, and the slave device performs the request.

If at the time of the appeal the previous call is completed, then the trigger 12 c6potaeH and when the trigger 54 is installed, the suspension signal is not generated.

After the sampling is completed, the slave device exposes the requested word to the bi-directional data buses of the second highway 10, through which it enters the bus drivers of node 48. Under the control of register 47, the read code goes through bus drivers of node 48 and switch 49 to the information input of the buffer register 51.

When a microcommand using the requested word is executed, a microoperation VM: D is generated, which transfers the contents of the buffer register 51 to the internal highway 20. This signal also goes to the input of the OR element 62 and causes the SR 54 to be set to one in sync pulse. If the slave device has not fulfilled the request, a suspend signal is generated, and processor 1 stops working until the request is completed. By the time the processor 1 is resumed, the requested word is received in buffer register 51 and arrives at the internal highway 20, and via the CI2 clock and the internal exchange micro-operation (BO1 or BO2} is transmitted to the arithmetic logic node 42 or to the register of the node 43.

If by the time the microcommand is executed using the requested word, the request has been completed, the trigger 12. reset yen and suspension do not occur

Downloading the word to block 8, as well as to external devices connected to the second line 10, is performed as follows. The microinstruction initiating the load, in addition to the source of the address and type of addressing, indicates the micro operation of the OP2 load and the data source — the register of the node 43. When this microcommand is executed via the clock C1, the code 20 is transmitted from the registers of the node 43 to the input that And adder 44, and the control code TA (addressing type) determines the executive address supplied to register 45. The simultaneously recorded word is set to the output I / O data buses of node 43 and is set to trigger 54, which provides control over the execution of the previous request and leads to the suspension of the formation of clock pulses CI1, CI2, PPE, if the request is not completed. Then, using the sync pulse SI2, the register 45 receives the address, the register 47 of the write operation, which is equal to one, which arrive respectively at the address buses and the bus operations of the second highway 10. The level of the logical unit from the output of the register 47 goes to the control input of the switch 49, ensuring that the data passes from the internal master, or 20, to the inputs of the buffer register 51. By the signal of OEM2 transmitted by the sync pulse SI2 from the output of the AND 46 element and the switching element 50 under the control of the register 47, the recorded word is received Buffer register 51, from the outputs of which by bus formers of node 48, also controlled by register 47, is placed on the data bus of the second highway 10. Next, on the PPE sync pulse, output signal I 53 generates a request signal (ZPR2), which establishes trigger 12, from the output of which a request signal is sent to the query bus of the second highway 10; the request is QUESTION 2, which initiates the loading operation in block 8 or in an external device connected to the second highway 10 and recognizes its address; edlagaemogo device when the movement instruction processor 1 word of one block portion 8 in the other. The execution of this instruction, which is typical of the software environment in which the information exchange device operates, illustrates the combination of the execution time of the instruction with the processing of requests by the slave devices. The initial state of the device before starting the execution of the instruction is characterized by the following state of the blocks: the address of the executed (current) instruction obtained as a result of executing the previous instruction is stored in registers 21 and 24, the address of the first microcommand of the current instruction is set in address register 39 by transferring the contents of the corresponding the buffer register 31 field is in the process of completing the previous instruction; the control and information fields of the current instruction are written to the register 35 by transferring the contents of the corresponding fields of the buffer register 31 in the process of completing the execution of the preceding instruction; At the inputs A of the adder 44, the base address code of the shaper 3 arrives in a state preceding the generation of the clock CI. Each gap in the microprogram flowchart that implements the instruction in question (Fig. 8) corresponds to a microprogram microcommand. The algorithm is given below, in accordance with which the instruction is executed, indicating the positions of the microinstructions, the corresponding numbers on the flowchart, the actions performed by the microcommands, and the microoperations required to implement the algorithm. 61. Picking a word from block 8 at the address determined using the first register of node 43 {BO2, TA: OBM2,). 62. Transfer the compared code from the instruction field to the arithmetic-logical node 42 {B01, BO2): under the control of the internal exchange micro-operations, the contents of the required field of the register 35 are transmitted by the internal highway 20 to the subsequent comparison. 63. Distribution of the word read from block 8 to the internal highway 10 (), comparison with the code in the arithmetic logic node 42 (AL). 64. Transition to 65 in the case of non-comparison, otherwise transition to 8 (by means of signals for changing the address of the micro-operation transmitted to the inputs of the address register 39 from the outputs of the decoder 23). 65. Record a word in block 8 at the address determined by the second register of node 43 (В02, ТА, ОБМ2,); the formation of the address of the instruction to which one should proceed in the case of incomparability (FI), the selection of the instruction by the generated address (MBT1); 66. The first modification of the address in the first register of node 43: under the control of the internal exchange micro-operations, the contents of the required register are transmitted via the internal trunk 20 to the arithmetic logic node 42, where they are modified according to the micro-operations code AL, then returned to the same register. 67. The first modification of the address in the second register of node 43 (similarly to 66); end of instruction (KONI): by census from buffer register 31, the codes in address register 39 and register 35 are set up, which are necessary to execute the next instruction. 68. Formation of the address of the instruction to which it should be transferred in the case of comparison (F0, FAY), selection of the instruction at the received address (VCM1,). 69. The second modification of the address in the first register of the block of registers 43 (BO2, BO1, AL) is similar to 66. 70. The second modification of the address in the second register of node 43 (BO2, BO1, AL), the end of the instruction (KONI) is 67. Fig. 9 shows the time diagram of the operation of the device when executing the instruction for moving a word in block 8. On plot A, the rectangles indicate the periods of activity of the program memory block 7. Plot B determines when the processor 1 is active during the execution of two instructions of this type, with branch 654 67 running when the first instruction is executed, branch 68-70 is executed when the second instruction is executed (Fig. 8). On this diagram, the numbers indicate the numbers of the executed microinstructions. On plot C, rectangles indicate the periods of activity of block 8. The shaded part of each rectangle of diagrams A and C corresponds to the processing time of the request from the time of access.

to the device until the development of cVfrHafla readiness. The arrows directed to plot A show the moments of signal generation at the first controlling output of processor 1 (KT1), the moments of generation of the signal at the second controlling output of processor 1 (KT2) are marked by arrows directed toward the plot of C. Near each arrow there is indicated a microoperation that triggers signal (CT1 or CT2). In the considered example, the cycle time for accessing slave devices is no more than three clock cycles, the access time for a sampling operation is no more than two clock cycles. As shown in Fig. 9, with such a ratio of the speeds of the slave devices and processor 1 during the execution of the considered instruction, suspend processor 1 is missing, i.e. Achieves complete alignment of access time to slave devices with the time required by processor 1 to run the firmware. Practically all are suspended. In particular, when using as a block 7 and a block 8 dynamic fields

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erasing devices that require periodic regeneration of the information stored in them.

Thus, the device implements the asynchronous exchange of information between the processor and the slave devices connected to the processor via two trunks, and provide a combination in it.

0 operations performed by the processor and slave devices. It allows the processor to initiate an exchange simultaneously on both mainlines connected to it, after which, without waiting for the completion of initiated swaps, it is possible to continue the execution of the microprogram for some time, using the information contained in the internal registers of the processor. Functions of slave readiness control are performed by the processor without loss of time, simultaneously with the execution of micro-operations specified in the microcommand, while no additional microcommands are required.

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Claims (1)

DEVICE FOR INFORMATION EXCHANGE, comprising a processor, an OR-HE element, the output of which is connected via a clock generator with a synchronizing input of the processor, a master oscillator, a program memory unit, a data memory unit, a request storage unit including the first and second AND elements and the first trigger, moreover the input-output of the program memory block is connected through the first highway to the first input-output of the processor, the second input-output of which is connected through the second highway to the input-output of the data memory block and the input-output of the device two, in the request storage unit, the output of the first AND element is connected to the zero input of the first trigger, and the first input of the second AND element is connected to the output of the master oscillator and the first input of the OR-NOT element, characterized in that, in order to increase the speed of the device, a suspension block containing two AND elements, and an OR element, and a second trigger is introduced into the request storage block, and in the suspension block, the output of the first OR element is connected to the second input of the OR-HE element, and the first and second inputs, respectively, with the outputs of the second and second elements AND, the first inputs of which are connected respectively to the first and second monitoring outputs of the processor, and the second inputs are respectively the single outputs of the first and second triggers and the request buses of the first and second highways, the individual inputs of the first and second triggers are connected respectively to the first and the second outputs of the processor’s requests, the first input of the first AND element is connected to the output of the master oscillator, and the second input is connected to the readiness bus of the first trunk, the second input and output of the second AND element are connected assigned to the readiness bus of the second trunk and the zero input of the second trigger, and the processor contains the address register of the current instruction, the first adder, microoperator decoder, two transition address registers, two exchange operation code registers, seven AND elements, two triggers, two elements OR, buffer register of instructions, two nodes of bus drivers, two commutators. a torus, two switching elements, a storage register of the current instruction and microprogram memory, a buffer data register, an arithmetic-logical unit and a unit of operational information registers, the first information inputs of the first and second adders being connected respectively to the output of the address register of the current instruction and the output of the operational register unit information outputs - respectively, with the information inputs of the first and second registers of the transition address, the information input-output of the arithmetic node is connected through CPU internal line to an information input-output unit registers the operational information, to the outputs of the register storage tekuSU 1070536 boiling instructions and buffer data register, with second data inputs of the first and second adders, the first input of the first AND element is connected to the output of the first element. OR, and the output with a single input of the first trigger, the output of which is the first controlling output of the processor, the first input of the first OR element is connected to the first output of the microoperator and the first inputs of the second and third elements AND, the output of which is the first output of processor requests, the second input of the first the OR element is connected to the second output of the microoperator and the control Input of the address register of the current instruction, the information input of which is connected to the output of the first register of the transition address, a directing input connected to the output of the second element And controlling the input of the first register of the code, the exchange operation and the first information input of the first switching element, the control input of which is connected to the output of the first register of the code of the exchange operation and the control inputs of the first node of the bus drivers and the first switch, the first information inputs the first and second switches are connected to the information input-output node of the registers of operational information, the second information inputs, respectively the outputs of the first and second nodes of the bus drivers, the information inputs of which are connected respectively to the outputs of the buffer register of instructions and the buffer data register, the information inputs of which are connected respectively with the outputs of the first and second switches, and the control inputs, respectively, with the outputs of the first and second switching elements, information inputs of the first and second registers of the exchange operation code are connected respectively to the first and second group of outputs of the microoperation decoder, WTO whose output is connected to the first input of the fourth AND element, the third and fourth outputs, respectively, with the first and second inputs of the second OR element and the first inputs of the fifth and sixth 'AND elements, the output of which is connected to the control inputs of the second register of the transition address , the register code of the exchange operation and the first information input of the second switching element, the control input connected to the control inputs of the second switch and the second node of the bus formers, the output of the second OR is connected to the first the input of the seventh AND element, the output of the second trigger connected to the unit input, the output of the fifth and the output of the fifth AND element are the second control output and the processor request output, the outputs of the second register of the transition address and the second register of the exchange operation code, information input-output of the second bus node shapers and the second information input of the second switching element form the second input-output of the processor, the control inputs of the node of the registers of operational information, the second adder , the arithmetic-logical unit, the group of control inputs and the group of outputs of the arithmetic-unit are connected respectively to the fifth and seventh outputs, the third group of outputs and the first group of inputs of the microoperator, the seventh output of which is connected to the control input of the first adder, and the fourth group of outputs and the second group of inputs - respectively, to the first address input of the firmware memory and the output of the storage register of the current instruction, the control input of which is connected to the output of the fourth element And, and inform an input input — with a second address input of microprogram memory and an output of a buffer register of instructions, outputs of the first register of a jump address and a register of an exchange operation code, information input-output of the first node of bus Formers and the second information input of the first: switching element form the first input-output of the processor, the second the inputs of the first and seventh elements And, the zero inputs of the first and second triggers, the synchronizing inputs of the program memory and the micro-decoder are connected to the synchronizing input process pa, firmware memory output is connected to the third group of inputs of the decoder microoperations.