SU1601614A1 - Multiprocessor system - Google Patents

Abstract

The invention relates to computing and is intended to implement the processing of information in a pipeline mode in real time and in the mode of multiple streams of commands and data, while the interprocessor exchange in the system is asynchronous. The purpose of the invention is to increase productivity while reducing hardware costs and simplifying the interprocessor exchange procedure. The exchange between the processors 1 is carried out through exchange units 2 containing a dual-port memory node. Moreover, for the access time of one processor 1 to the dual-port memory node, access by another processor 1 is blocked. The means of synchronizing access to the dual-port memory node simplify the implementation of the system. 5 il.

Description

1

The invention relates to computing and is intended to implement the processing of information in a pipeline mode in real time and in the mode of multiple streams of commands and data, while the interprocessor exchange in the system is asynchronous.

The purpose of the invention is to increase productivity while reducing hardware costs and simplifying the interprocessor procedure.

exchange

Figo shows a structural scheme of a multiprocessor system; FIGS. 2 and 3 show the functional schemes of the processor and the exchange unit, respectively; Fig O4 - timing charts of the signals generated by the synchronization node; FIGURES diagrams illustrating the mechanism for inducing the positive phase of clock pulses

System (FIGSO contains processors 1-1-1og and blocks 2I-2 from exchange Each processor 1 (fig2) contains synchronization node 3, element OR 4, processing node 5, element OR-NOT 6 and bidirectional bus driver 7 "Each exchange unit 2 (fig ) contains D-triggers 8.1 and 8 „2, JK-triggers 9о1 and 9о2, elements AND lOol and 10о2, elements AND-NOT PI and 11.2 and node 12 of a two-port memory with a capacity of 2 words o In addition, figo 1-3 are marked inputs and outputs 13-30 corresponding signals

Processing node 5 is designed to process information on a given program. It contains an arithmetic logic unit, a control unit, program memory and data. Part of the address space in the format of address commands is reserved for accessing the exchange unit 2 The control unit of the processing unit provides software generation of signals Transmission 1 and Transmission 2 Bus driver 7 is designed for adjusting the unidirectional data input and output of the processing node 5 with the external bidirection ennoy data bus in honors Single node processing uc 5 permissible use of a wide range of devices, from general purpose processor to the individual nodes opertschonnyh type matrix multiplier which

provide the formation of the necessary set of control signals, addresses and operand

Synchronization node 3 forms (Fig4) a sequence of sync pulses (SI) with parameters T and ty and two sequences of strobe signals: reading gates (MF) with parameters 0 0 4 4) 4 recording gates

h т / V л (СЗ) with parameters с and о

srz

Depending on the level of the signal Write - read (G / H), either reading gates 5 () or write gates are formed at the outputs of the synchronization node.

() respectively The active level of gating signals is the logic zero level. In the system of machine commands of each processor 1 0, in addition to a set of arithmetic, logic and control commands, including unconditional and conditional jumps and subroutine commands, commands are generated that generate signals 5 Transmit G and Transmit 2, the purpose of which is to synchronize the exchange process. Each processor i of the system communicates with the processor l (i + l) through the exchange block 30 and with the processor 1. (i-1) through the block 2. () exchange. The processor is addressed to the exchange unit by means of its address commands. Two processors 1 can simultaneously access 35 to a common exchange unit 2 without prior program analysis of its state, but one of the processors 1 will go into standby mode. The active processor 1, the one that 40 Rilly has gained access to the exchange unit 2, having completed operations with it, has to transfer the exchange unit 2 to the waiting processor 1 programmatically. This transmission is carried out under the control of programmatically generated signals. Transmission 1 and Transmission 2 Dp of the implementation of a certain algorithm by the system, the program memory of each processor I must be programmed; the program implements the undefined part of the algorithm of this processor; 1 The software implementation of each processor 1 corresponds to the corresponding part of the system-wide algorithm. 55 differs from the conventionally known only exchange procedure

During the initial installation, each exchange unit 2O1 is transferred to the loii processor. If the implementation of the algorithm requires it, then the loi processor can programmatically transfer the 2D block to the processor l, Ci + l), without performing the last one. When the information capacity of each exchange unit 2 is 2 words for access to two blocks 2 exchange in the address range of the processor 1 is allocated address values

Considering that all the set addresses are

processor 1 is a series of numbers 0,1,000,2 -1, where n is the number of binary bits in the address command format intended for encoding the address, the address range of the processor Ioi.0,1,000,2 is intended for accessing the memory data.

2 -2

Kt

2 -2

“+

address range

+1,000.2 -2 -1 is intended to refer to the 2o (il) exchange unit, the address range is 2-2, oh oh, 2 -1 is intended to refer to the 2oi exchange unit. For example, if the address space is in machine format the command is given I1 binary bits, then with the information capacity of the exchange unit equal to 16 words, the octal address range 3740-3757 is intended for accessing the 2o (il) exchange unit, and the address range of 3760-3777 is for exchanging the exchange 2oi procedure information between two adjacent processors loi and lo (i + l) is to communicate by dresnyh commands to the unit 2 "1 exchange. Suppose that it is necessary to add operands located in the accumulators of the processor Ki and the processor (1 + 1), provided that the exchange unit 2oi is in the multi-field possession of the processor, it is sufficient for processor 1.i to execute instructions ST 3760, POST ONE (I)

where the first instruction is the instruction of loading the contents of the battery to the memory cell with the absolute address 3760, which corresponds to the zero cell of the 2oi exchange unit, and the second instruction is the instruction that records the occurrence of the event (in our case of writing an operand to the block exchange), the performance of which will generate a signal Transmission 1, allowing the processor le (i + l) to the block, 1 exchange after forming sig16016 14

Transmission 1 The repeated appeal of the processor I to block 2, i of the exchange translates it into waiting. The processor I, (i - (- l) in the exchange process will have to execute the instruction

ADD 3740,

ten

15

20

25

thirty

by which the contents of the processor battery lo (i + l) are added to the contents of the memory cell with an absolute address of 3740, which corresponds to the zero cell of the 2oi exchange unit. When these three instructions are executed, the two operands in the accumulators of the neighboring processors add, The processor is loaded into the processor's battery l, (i + l) o. In addition, the processor lo (i + l) can send in block 2, i the exchange of the processor's K operands, after which it has to execute the instruction

POSTTWO

on which the Transmission 2 signal will be generated, which unlocks the access of processor 1.1 to block 2.1 of the exchange.

The hardware to synchronize the exchange process works as follows. During the initial installation, all the 8O1 and 9-1 triggers of all the exchange 2 blocks (figs) are set to one, all the 82 and 9.2 triggers are set to zero. an element into one state means that the signal of the level of a logical unit is set at the direct output of a node or element, and at its corresponding inverse output (if it exists) - a logical zero of

Consider the mode of simultaneous software access of the processor li and Io (i + l) to the exchange unit 2oi at the state of flip-flops 9o1 and 9o2., Fixed by the initial setting. For this it is necessary that the synchronization nodes 3 simultaneously start forming sync pulses, during the operation of which both processors 1 о g and 1 о (i + l) will make calls to the exchange 2oi block, and the timing parameters of the clock pulses (period and 5 duration) may be different. In each of the processors, the clock pulse from the output of the synchronization node goes to the third input ment OR 4 and at output 28, In the initial state of sig5

0

Block 1 and Block 2 are missing, so the first and second inputs of the HJM 4 element are affected by a logic zero level, therefore the leading edge of sync pulses (Fig.5) passes through the OR 4 element both in the Ki processor and in the lc processor (i + l ).

When applying to the inputs 28, 30 and 29 of the element OR 4 sync pulses and potential signals Blocking (B1) and Blocking 2 (B2) at the output of the element OR 4, the resulting signal (SIg) is formed as shown in Fig. 5o in one state, if one of the signals B1 or Each sync pulse is present is divided into two phases: positive, which includes a positive front (transition from zero to one) and a time interval in which it is in a state of one and negative, in which the entrance of the rear front (transition from one Zero) and the time spent in the state of logical zero о From the output of the element OR 4 the positive phase of the synchro-pulse arrives at the input of the node 5 processing-: bokIs. During the positive-acting (the synchrophase phase, the processing node 5 generates their output signals and codes, which are functions of macroinstructions, when performing any addressing operation at the output address of the processing node 5, set to the lower bits of the contents of the address part of the command, the signals at the outputs of the sampling signals (B1 and B2) are generated during the decryption processThe appropriate MSBs komandyo address part of the follow conditions are determined

1 if 2

0 if o (. 2 -2

1 if 2 2

(2) S

AT 2

to +

Oh, if 2 -2, -2

where (x. - the value of the address part

Manda

At the data output of the processing unit 5, an operand is set for writing to the exchange unit 2. At the output of the G / W, a logical zero is set in the write mode and a logical one in the read mode. Logical unit

five

0

0

five

five

is set in the execution of the macroinstructions POST ONE at the output 26 and in the cycle of the execution of the macroinstructions ROSTHAO at the output 27 When performing other operations, the specified outputs remain in the zero state. To implement the POST ONE and POST TWO instructions, it is sufficient to allocate one bit of memory to the memory of the firmware; one of them. The processor 1.1 in the considered positive phase of the clock makes calls to the interchange block 2oi. Let it send the operand to the third cell of the 2oi block. exchange by executing instruction ST 3763 (the work is described for a particular case of memory organization, putting and) о By virtue of conditions (2) and (3) the signal at the output 24 V1 is a logical one, and the signal B2 is a logical zero. node 5 processing processor Ui mustache anavlivayuts following codes and signals: output data - the content of the battery; the output of the address is the binary code of the OOP (four MLEAR bits of the address code 3763); at the output S / H - the level of logical zero / recording mode) ;; - at the outputs of the transmission - logical zero From the output of the S / H node 5 of the processing, a logical zero arrives at the input of the synchronization node 3 and enables the output of the recording strobe to the output 20o 2 is in the unit state. In addition, from the S / H output of the processing unit 5, a logical zero is fed to the input. The transmission direction of the bus driver 7, to the input. Sampling of the chip from the output 24 of the processing unit is transmitted through the OR-HE element 6 B1 (logical zero) This combination of signals provides Information is retrieved from the data input of the bus form 1 of the transmitter 7 at its input / output 23 data At the output 22 of the address four lower bits of the address are set, the output 20 receives a recording strobe, and the output 28 receives sync pulses that are transmitted respectively to the inputs 22-1 20o 1 and 28o1 of the exchange unit 2oi and to the inputs 22, 2, 20o 2 and 28o2 of the unit 2, (il) of the exchange. Similarly, data from the input-output 23 of the loi processor is fed to the input-output

23o 1 block 2 (, i exchange and input-output 23.2 block, 2o (i-1) exchange. At the input

24the signal comes B1 unit

level, and input 26 is a signal of port I (III) transmission of a zero inactive level, which are received in block 2 "1 exchange". In block 2, the operand at input-output 23 ot goes to the first input-output of node 12 of a dual-port memory, which In this case, it performs the function of information input, the recording strobe at input 20 enters the SZ input of node 12. The sync pulse at input 28.1 enters the synchronization inputs of D-flip-flop 8o1 and JK-flip-flop 9o1 while the triggers continue to remain in one state of Units - the signal from the direct output of the JK-flip-flop 9o1 and the signal B1 at the input 24 unit level, arriving at the corresponding inputs of the element AND-NOT 11 "1, form at its output a signal B1 Q1 L B1, which, by entering B1 of the node 12 of the dual-port memory, provides recording of the operand from input-output 23 ,, 1 to the third cell of the node 12; At the output of the element AND lOol, the signal is blocked: Block 1 (B I), and B1 Q L in our case is equal to zero, since Q1 O, where Q1 is the inverse output of the JK flip-flop 9о1о Signal B1 from block 2.1 exchange on input 30 enters the loi processor, in which it acts on the first input of the element OR 4, the Zero (inactive) level of the post The B1 signal does not affect the passage of clock pulses through the OR 4 element, therefore, with the arrival of the negative phase of the clock clock, the microoperation is completed, and if it was final in the sequence of microoperations implementing the recording macrooperation, the next clock pulse increases the content of the comaid counter by one and the processor 1 starts execution of the next macrooperation

We now turn to the processor lo (i + l) o. Let him execute a call to block 2 in the cycle, i exchanging the instruction ADD 3743 ,, In this case, the following signals are generated at the outputs of its node 5: at the second output of the sampling signal, a single level signal B2 by condition (3); on the first or the signal path of the sample, the signal B1 is of the zero level by condition (2); at the output of the address is the binary code 0011 (four lower digits of the octal

ten

20

j

code 3743); at the output S / H - the signal S / H of the unit level (reading mode); the outputs of the signal transmission -.signs P and 112 level logical zero

From the output of the S / H of the processing unit 5, the unit enters the input of the synchronization unit 3 and allows the reading strobe to be output to its output 21 and to the input. The direction of transmission of the bi-directional bus driver 7 to the sample input of which is fed from the output 25 of the processing node 5 inverted signal B2 element SHS-NOT 6o The combination of these signals provides the transmission of the operand from the input of the bus driver 7 data input to its data output. Thus, the operand from input-output 23 is fed to the data input of the processing node 5 Address to output 22, the reading strobe at output 21 and the sync pulse at output 28 are received respectively at inputs 22, 23, 21c, 2 and 28о2 of the exchange unit 25 2oi and to the inputs 22о1, 21.1 and 28.1 of block 2, (i -) - I) exchange Signal B2 level logic unit and logic level zero signal P2 are received via inputs 25 and 27, respectively, into exchange unit 2.1, in which the address is 22о2, and the reading strobe is r- at input 21 o 2, respectively, at the inputs Node 12 of the two-port memory of the sync pulse at input 28о 2 is fed to the inputs of the D-flip-flop 8 "2 and JK-flip-flop 9о2 sync pulses, while the 8.2 and 9.2 flip-flops continue t remain in zero state. At the output of the AND 10.2 element, the signal B2 is generated. Q2 L B2, in our case it is equal to 1, since, where Q2 is the inverse output of the JK-flip-flop 9o2, Signal B2 is input 29 to the corresponding input of the OR element 5 in the K (1 + 1) processor, blocking the passage of the negative phase of the sync pulse, which is equivalent to delaying the negative phase of the sync pulse in time. At that, node 5 of processing 0 goes into standby mode until the moment JK-flip-flop 9o2 changes its state. The zero level from the direct output of JK-flip-flop 9o2 and the signal B2 of a single level at input 25, J and AND-NOT AND „2, form the signal B2 Q2 L B2, the unit level of which arrives at the input B2 of the node 12 of the dual-port memory of the 2о1 unit, does not allow its second sample

thirty

35

40

11 1

the port, while the second data inputs / outputs continue to remain in the third state. Thus, the operand is read delayed, which Hie reflects on the correctness of the processor's function. 1 about (i + 1), whose arithmetic logic unit is a combinatorial circuit, produced the E | OEDIT processing of the operand in accordance with the E | AI with the operation code after reading the latter. Thus, as a result of TJaTB simultaneous access of two 1 loi and 1o processors () to the exchange unit 2oi, the contents of the accumulator of the loi processor's processor are written to the third 4 cell of the 12-port memory node 12, and the lc (i + l) processor goes into fjidani mode, in which it remains for tex until the processor loi does not use the POST ONE instruction. In the POST ONE macroinstructions emission / wave cycle, a signal is generated in the processing 5

| 11, which at input 26 enters the K-input of the JK-flip-flop 9o1 and causes the installation to the zero state of this, at the output of the element And lOol, the signal B1 is generated, provided that the loi processor reverts - 30 moves to the third input of the IL 4 processor element and thus puts it into standby mode. The unit from the inverse output JK-tri-irepa 9.01 enters the D-input of the D-trig-irepa 802, which by the arrival of the front of the first sync pulse input j28c2 from the processor lo (i + l) goes IB unit state and causes installation J K-flip-flop 9о2 at the J-input into the single state Purpose of the D-trhera 8.2 is locked in matching the exchange process with the processor clock frequency lo (i + l) As follows from figoZ, the falling edge of the signal B1 or B2 In the negative phase of the initial sequence of sync pulses, the duration of the negative phase of the resulting SID sequence (shown by dashed lines) decreases as compared to the initial one, which is acceptable. Terminating D-flip-flops 8.2 and 8 "1 provide the necessary delay in the removal of signals B2 and B1, respectively, and ensure the formation of the leading edges of these signals in the positive phase of the corresponding sync pulses

14

12

5 0 5

Let us again consider the functionality of the processor 1 о (i 1), which, when the ADD 3743 operation was performed, went into the standby mode,. After the JK-flip-flop 9o2 triggers, the B2 signal is removed, i.e. the output of the element Yus2 is set to zero, which is transmitted via output 29 to the input of the element OR 4 of the lo (i + l) processor, and the output of the element AND-NOT 11-2 is generated B2 Q2 D B2, the zero level of which, arriving at the input of node 12 of a two-port memory, allows sampling of its second port. In this reading gate, 21 o 2 is fed to the input of node 12 of a two-port memory all the time while the processor lo (i + l) is in standby mode, the address code (0011) at the address input is also not removed, Since the phase of the Cy1 & Pulse has not yet passed to the processing node 5 Therefore, after the JK flip-flop 9о2 is triggered, which occurs only in the positive phase of the clock, the next reading strobe reads the information from the third cell of the node 12 of the dual-port memory and is output at the data output its contents, which at input-output 23 enters the lo processor (i + Oo) The incoming operand from the input-output of the bus driver 7 is transmitted to the data input of the processing node Ь of the processing. Anda with the contents of the battery The negative phase of the next sync pulse passes through the element OR 4 and, arriving at the MI input of the processing unit 5, completes the operation under consideration Further operation of the processor l. (i + l) proceeds in accordance with the program The exchange unit is in the processor’s exclusive possession lo (i + l) until the latter executes the POST TWO instruction, according to which the P2 signal will be generated at its processing node l. (i + l). This signal on input 27 enters the 2D exchange unit at the K-input of the JK-flip-flop and sets it to zero. The unit from the inverse output of the JK-flip-flop 9o2 goes to the D-input of the D-flip-flop 8.1, which, upon the arrival of a clock pulse from the processor 1.1, goes into a single state and causes 10

 1601614

Pa 9 „1 at the J-in entrance ,, As a result of a new succession, the Iner 8o1, 8o2, 9o1 exchange and the initial state

neither should the macroconveyor information be divided into a task, so that each one reads from the 2o (i-i) processing unit only in this case, the pro2 .1 exchange form the advantage of such cycles and branching JQ and acquired self-synchronization

15

on you pc on her way around the way of the second p vy v vy bv stv mats sv the second input the input of the hero and the second, the second input of the entrance of the entrance of the entrance of the ven e ele AND-NOT connect memory inputs in Kirov and exit chrony second

Claims (1)

Invention Formula 25 A multiprocessor system containing m processors, each of which contains a processing node, a synchronization node and a bi-directional bus driver, and a ha of exchange units, 30 each of which contains a memory node, address and control outputs, and 1st processor data input / output (, o, m) are connected with the first similar inputs and inputs-outputs of the 1st exchange unit and with the second like inputs and inputs-outputs (Ll) -ro (with,) of the exchange unit, characterized in that, in order to increase 40 productivity while reducing the apparatus costs and simplify the interprocessor exchange procedure, the OR and RSHI-NOT elements are introduced into each processor, and the first and second D- and JK-flip-flops, the first and second AND and -NE elements, and each to the exchange unit, the memory node is designed as a dual-port memory node, the first outputs of the signal jO sampling and transmission and the input of the signal. The lock of the 1st processor is connected to the first identical inputs and output of the 1st exchange unit, the second inputs of the sampling signals and the transmission and output of the signal Lock 2 are connected to the same output and both inputs (1 + 1) -th (at,) processor, in which each block obme45 55 14 ten in s t - jq 15 25 30 40 jO 45 five To the input of the first JK-flip-flop and the first input of the first element I form the first input of the transmission signals and the sampling of the exchange unit, the first inputs of the address, write and read gates of the dual-port memory node, the synchronization input of the first D-flip-flop and the first input / output data of the node two-port memory, form the first input of the address and control and the first input-output data of the exchange unit, the K-input of the second JK flip-flop and the first input of the second element And form the second input of the transmission signals and the sampling of the exchange unit, the second inputs of the address, gates of writing and reading node d the two-port memory, the second D-flip-flop input and the second data output-output of the dual-port memory node form the second address and control inputs and the second input-output of the exchange unit, the outputs of the first and second And elements are the outputs of the Locking 1 and Locking 2 signals the exchange unit, respectively, the clock input and the information input of the first D-flip-flop are connected to the synchronization input of the first JK-flip-flop and the inverse output of the second JK-flip-flop, respectively, the sync input and the information input of the second D-flip-flop A is connected to the synchronization input of the second JK-flip-flop, the outputs of the first and second D-flip-flops are connected to the J-inputs of the first and second JK-flip-flops, respectively, the direct and inverse outputs of the first JK-flip-flop are connected to the first input of the first AND-N and the second input of the first element And, respectively, the direct and inverse outputs of the second JK-flip-flop are connected to the first input of the second AND-NE element and the second input of the second And element, respectively, the first inputs of the first and second And elements are connected to the second inputs of the first and second el I-NOT copies, respectively, whose outputs are connected to the inputs of Port I and D sampling, port assembly 2 of the dual-port memory, and in each processor the inputs of the signals are blocked. Lock 2 processors are connected to the first and second inputs of the OR element, the output of which connected to the synchronization input of the processing node, the first and second outputs of the sample and transmission signals of which are the first and second processor outputs of the same name, outputs of clock pulses, write and read gates of the synchronization node and output of the processing node address form addresses and controls of the processor whose input / output data is connected to the data input / output of the bi-directional bus driver, the input and output of which are connected to the same output and the input of the processing node, the output signal the writing of which is connected to the input of the synchronization node and to the input. The direction of transmission of the bi-directional bus driver, the input ftj is a chip of the crystal of which is connected to the output of the SH-NOT element, the first and second inputs of which are connected to the processing node sample, the output of clock pulses synchronization node is connected to the third input of the element Fiyo Phi l / cw CV Zl SFC Hz C3 / F, -4n 67 62 Sy l n 1 one Jz-j FI.5