SU1709322A1 - Device for interfacing with microcomputer - Google Patents

Abstract

The invention relates to computing and can be used as an external device to increase the speed of microcomputers of the type "Electronics-60", "Electronics MS 1201" and others with a similar interface. The purpose of the invention is to increase speed by reducing the number of required shipments. The device contains an address selector, an interrupt unit, a microinstructions memory block, two arithmetic logic units, a table functions storage unit, switches, a transceiver, registers, delay elements, OR NAND, AND triggers. 1 il.

Description

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From the output of the first trigger 6, it enters the input element AND 8 and the enable input of the transceiver 17, allowing information to pass through it, since in this output cycle the input signal to the computer interface 12 is not generated, the second trigger 7 remains in the zero state. The zero state of the trigger 7 causes the information from the bus 21 of the computer interface 12 to pass through the receiver 17 to the blocks of the device. On a signal Output from the bus 24 of the computer interface 12, which through the element 11Л1 / 1 3 m element 8 comes to the input of the strobe of microcommand memory 11, block 11 of the memory will read the microcom at the address whose low bits come from the first register 10, the most significant bit (O) - from the second trigger 7, 8, depending on the address, signals (O) will be generated at certain outputs of the microcommand memory 11 and written (or read) into one or several device blocks. The signal from the output of the And 8 element will also go through the second delay element 9 and through the NAND 4 element to the bus 25 of the computer interface 12. The second delay element 9 is necessary so that by the time of the generation of the sync signal the transients occurring during gating of the memory block 11 are completed microinstructions. Having received the sync signal, the computer removes the signal. The output from the bus 24 of the computer interface 12, as a result, the reading of the microcommand from the memory block 11 is stopped and the generation of the sync signal at the output of the NAND 4 element is over. After removing the signal on the bus 25, the microcomputer removes the sync signal on the bus 22 According to the following clock signal on bus 22, the first trigger 6 is set to the zero state if the computer in the next exchange cycle is not addressed to the device, since the information input of the first trigger 6 from the output of the address selector 1 is O. During the input cycle of microcomputer The triplets receive the address, i.e., write to the first register 10 and set the first trigger 6 to the 1 state, similarly to the described output cycle. After that, the bus 23 receives from the computer a signal Input, which sets the second trigger 7 to one state. The output signal from the second trigger 7 arrives at the input of the transceiver mode 17, and it transmits information from the device blocks to the bus 21. Generation of the sync signal on the client I - NO 4 and reading of microcommands from block 11 of microinstructions memory occurs as in the output cycle, except that the input signal from the bus 23 goes to the element OR 3 through the first delay element 2, the delay signal input for the time required for installation with The low-order bit of the address of the memory block 11, coming from the output of the second trigger 7. After the sshnap input from bus 23 and the signal from bus 22, the second trigger 7 is set to the zero state. Consider the operation of the device from the description of the operations performed by block 13. To perform the multiplication, it is required to send operands to the device and read the result. The multiplier is transmitted from the computer in an output cycle. The multiplier coming from the computer through the transceiver 17 is received in the second register 14, since the microcommand memory block 11 will be expressed by the block 11. A negative pulse at the output of the third bit, recording into the second register 14, is then multiplied in the output loop from the computer. The microinstructions memory unit 11 generates negative pulses at the outputs of 4, 14, 15, and 15th bits, reads the second register 14, receives operands and opcode in block 13, after which it multiplies the integers in the additional code. During the execution of multiplication, with a delay of the recording time in block 13 and the generation time of the response signal on the second delay element 9 and the NAND 4 element, the output of Block 13 is output by O, which is removed after the multiplier execution loader by block 13, When the third application of the computer in the Input cycle reads the high word of the product to the second input-output of block 13 and sends it to the computer via the transceiver 17. The high word of the product can also be read at the conditional addresses 1011, 1010, where the high the view of the product into the second AL U 15 and in the second case also a reset of 3 O of the third register 16. If it is necessary to read the least significant bits of the product, the fourth reference of the computer to the device is made in the Input cycle. In this case, a block of 11 pa, mi micro-commands produces low levels at the outputs of 1.15 and 17th bits, and the low-order digits of the first input-output of the block 13 are read and then through the first switch 19 and the transceiver 17 in the computer

The low word of the product can be read in the input cycle and at the conditional addresses 1100, 1110, while additionally, the low bits of the product are recorded in block 15, and in the second case the third register 16 is also reset. If only the value of the high 16 is required the output of the product, the second reading (the last transfer) is not necessary, which reduces the exchange by one transfer.

In the case of a high-speed microcomputer, the third transfer may begin before the completion of multiplication in block 13, but this will not disrupt the operation of the device, since in this case, the output of block 13 is present O until the multiplication is completed. The reception of the code in the first register 10 and the generation of signals at the output of the microcommand memory block 11 will be similar, but O from the output. The readiness of block 13 prohibits the generation of an answer signal on the NAND 4. Element after the multiplication operation is completed in block 13 and the operation 1 occurs. at the Ready of block 13 output, the operation code is received from the two lower bits of the control input of block 13, the high word of the product is read to the second input / output of block 13 and transmitted to the computer via the transceiver 17, and a signal is generated AND-NOT 4, and then the transfer is completed in the standard way (as the output cycle from a computer).

The multiplication of fractional numbers is performed similarly to the multiplication of integers, except that the device is multiplied in the output loop by address 1010.

When squaring the device, send one operand and read the result. When squaring integers, the operand is transferred from the computer in the Output loop. As a result, the microinstructions memory unit 11 generates zero signals at the outputs of bits 3, 4, 14, 15 and 16, and the operand is recorded through the transceiver 17 into the second register 14, read resolution of the second register 14, receiving the operand being squared into the block 13 and the launch of the execution of multiplication is similar to the multiplication considered. Reading the result is also done in the same way as after multiplying.

When squaring fractional numbers, the operand is sent in an output loop to the conditional address 1011.

To perform a division into a device, it is necessary to send the upper and lower words of the dividend, the divisor, read the quotient and

if necessary, also a residue and ensure that there is no overflow during division. Before the division operation is performed, the code 1 is sent to block 5

interrupts in the output loop (enable interrupt bypass). This transfer may be performed once at the start of the operation. When the division operation is executed, the spread word of the dividend is sent to the device in the computer output cycle, the microcommand memory block 11 generates low levels at the 16th bit output and is received via transceiver 17 into block 13 from the second higher input / output

5 words divisible. After that, the lower word of the dividend in the computer output cycle is sent to the device and it is recorded in the second register 14. Then the divider is sent in the computer output cycle, low levels are generated at the outputs of 4.15 and 16th bits of the microcommand memory block 11, reading the second register 14, with the divider 13 low word divisible from the first input-output divider via transceiver 17 and from the second input / output of block 13 of the operation code from the two lower bits of the control input, after which the block 13 is turned on to perform the division operation . During the execution of the division, after the delay of the recording time in block 13 and the generation of a signal on the second delay element 9 and the NAND element 4, the output of the block 13 is on output, which is removed only after completion

5 perform the division operation.

The next time the computer is accessed in the input cycle, the reading of the private will be performed (performed similarly to reading the higher-order product). If nessesary,

0 then the next time the device is accessed, the remainder of the division is read in the output cycle.

If during the execution of the division in block 13 (when the divisor is less than or equal to

5 divisible) overflow occurs, then 1 is generated at the overflow output of block 13, which enters interrupt block 5, which runs a typical interruption cycle with transmission to the computer of the interrupt address vector.

If, after performing multiplication (square) of positive fractional numbers, it is necessary to divide, then after multiplying (square), the divider is sent in a computer output cycle. As a result, a low level is generated at the outputs of the 15th, 16th and 17th bits of the microcommand memory block 11. It will be produced that the low word of the product of block 13 on its first input-output and the record of the low word of the product in block 13, receiving the divider in block 13 through the transceiver 17 from the second input-output and launching to perform the division, Then everything is done similarly to the considered division .

When calculating a table function, the device must send the argument code that is the address for block 18. The argument code is sent in a cycle Output of the computer through the transceiver 17 to the second register 14 (similar to recording the multiplication multiplier). During the transfer, in the input cycle of the computer, one of the table functions is read. In this case, the block 11 of memory of timings commands generates signals at the outputs of 11, 12 and 13 bits, respectively, and the 4th bit (reading the first register 14), after which the corresponding ROM of the block 18 will be read at the address supplied to its input from the outputs of the second register 14.

To perform operations by block 15, it is necessary to send the operation code to the third register 16, the operand to block 15, and read the result from block 15. First, a computer output is sent in a cycle via a transceiver 17 to a third register 16 of an 8-bit operation code (on outputs 7 and The 8th bits of block 11 of the memory of micro-commands will produce low levels arriving at the inputs of the recording of the third register 16). The older four bits specify the type of operation to be performed subsequently, and the younger ones define the operation parameter (how many bits to shift). For the purpose of convenience of programming, it is possible to separately record the upper four and lower four bits of the third register 16 when the computer is accessed in the output cycle.

At the next transfer in the output cycle of the computer to the device at the output of the 10th bit of the microcommand memory block 11 will be O and the operation code from the second register 14 and operand from the first information input / output will be received through the transceiver 17 into block 15 with simultaneous operation (shift). During the next transfer in the input cycle into the computer, generation of O at the output of the 9th bit of block 11 of microcommand memory occurs, reading the result of the operation from block 15 to the first information input-output and transmitting it through the transceiver 17 to the computer.

Normalization of the number using block 15 may occur as follows. At the first transfer of the normalized number in the cycle of output from the computer to the device at the outputs

On the 6th and 10th bits of block 11 of the memory of micro-instructions, low levels will be developed and the third register 16 will be reset to О, the operation code from the second will be received in block 15

inputs and numbers from the first input-output (via transceiver 17).

During the second transfer in the cycle of input into the computer, generation of O at outputs 7, 8, 9 of bits of block 11 of microinstructions memory occurs and reading of binary left 1 from block 15 of the second input-output takes place with its transfer to a computer through a transceiver. 17, and also write this code left 1 to four least significant bits

5 of the third register 16. In the third transfer, in the output loop of the normalized number, in block 15, the operation code is received from the third register 16, the number from the first input-output through the transceiver 17 and

0 is shifted to the left. At the fifth transfer in the cycle of input to the computer from the device from block 15 through its first input-output and transceiver 17 and the computer the normalized number is read.

5 It is possible to perform operations in block 15 on the result of the operation in block 13. This purpose is served by the transfer commands in the computer input cycle. This eliminates the need to receive this code in the computer and send

0 it is in block 15. Additional gain in speed can be obtained by multiplying the array of numbers by a certain coefficient. In this case, the first transfer in the output cycle is to write this

5 coefficient in the second register 14 and then multiply by the first number of the array, as described (multiplication). When multiplying the remaining numbers of the array, the first transfer is h (in the second register 14)

0 it is not necessary, as the coefficient is still stored in the second register 14. Therefore, when multiplying each number of the array by the coefficient, only the last three shipments need to be made (as in the description

5 times).

Claims (1)

Claims An apparatus for interfacing with a microcomputer, comprising a transceiver, an address selector, first and second triggers, element 0 AND, OR element, first delay element, first-third registers, first switch, first arithmetic logic unit, with the address selector input being the device input for connecting to the bus 5 data of the microcomputer address, and the output is connected to the information input of the first trigger, the first input of the first element I with the output of the first trigger, the output of the first switch with the information input of the register and the first information input / output of the transceiver, the second information input-output of which is input -the output of the device for connecting the address of the microcomputer to the data bus; the first information input of the first arithmetic logic unit is connected to the output of the second register and the information input of the first switchboard a, characterized in that, in order to increase speed, a second switchboard, a second arithmetic unit, a table functions storage unit, a microinstructions memory unit, a second delay element, an interrupt unit and an AND-NAND element, the second information input-output the transceiver is connected to the information input-output of the second arithmetic logic unit, the second information input-output of the first arithmetic logic unit, information inputs of the interrupt unit and the third register, the outputs of the second the switch and the storage function of the table functions, the address input of which is connected to the output of the second register, the output of the third register to the information input of the second switch and the input of the operation code of the second arithmetic logic unit, the information input of the first register is the input of the device for connecting the microcomputer address data bus , the synchronous inputs of the first register and the first trigger and the reset input of the second trigger form the input of the device for connection to the microcomputer synchronization bus; the first input of the block request is interrupted , A single input of the second flip-flop and the input of the first delay element form the input of the device for connecting to the input control bus of the microcomputer, the output of the first delay element is connected to the first input of the OR element, the second input which is the input of the device for connection to the microcomputer output control bus, and the output is connected to the second input of the AND element, the output of which is connected to the gating input of the microcommand memory block and through the second delay element to the first input of the NAND element, the second input of which is connected to the readiness output of the first arithmetic logic unit, the outputs of the microinstruction memory block are connected to the synchronous inputs of the second and third registers, the first and second arithmetic logical blocks, the storage block of table functions, the first and the second switch and interrupt unit, the second the request input of which is connected to the overflow output of the first arithmetic logic unit, the output of the first trigger is connected with the enable input of the transceiver, the mode input of which is connected to the output the second trigger connected to the high-order input of the address of the microinstructions memory block, the low-order inputs of the address of which are connected to the output of the first register, the output of the interrupt signal and the third request input of the interrupt unit is the output and input of the device for connecting respectively to the address and interrupt data buses of the microcomputer, and the gate output combined with the output of the NAND element form the output of the device for connection to the microelectric response bus.