RU2012043C1 - Video controller - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: register unit 8, multiplexer 14, memory 6, where state and control data are stored, memory unit 7 and interrupt controller 9 are introduced to accomplish the goal of invention. This results in decreased address space for access to registers and peripheral devices. This also results in possibility of data exchange with direct access to computer memory. EFFECT: increased field of application, simplified design of state registers, control registers and control logic dealt with each bit in registers of peripheral devices. 17 dwg

Description

 The invention relates to computer technology and is intended for data exchange over a communication channel.

 Known devices [1], intended for data exchange via a communication channel, containing control registers and state registers for storing control information, data registers, control encoder.

 A disadvantage of the known devices is the large hardware costs necessary for the implementation of control registers, state registers, control encoder in cases where a significant number of control registers and state registers are required to ensure the functions of known devices.

 Closest to the proposed one is a controller [2], which contains a bus controller, an interface, an address selector, an address counter, an address register, a comparison circuit, a receiver, a transmitter, a control encoder, and the inputs / outputs of the bus controller are connected to the controller’s system bus, the first group the interface inputs and outputs are connected to the controller data bus, the second group of its inputs and outputs is connected to the controller address bus, its data inputs are connected to the controller’s internal bus, its address outputs are connected to the address inputs address lecturers, bit outputs of the address counter are connected to the inputs of the address of the interface and to the first group of inputs of the comparison circuit, to the second group of inputs of which the outputs of the address register are connected, the inputs of the address counter data and the information inputs of the address register are connected to the internal bus of the controller, the recording counter input address, address register entry, second group of interface control inputs, third group of bus controller control inputs, second group of transmitter control inputs, second group of control inputs receiver, the first group of outputs of the control encoder are connected to the control bus of the controller, the output of the bus controller is connected to the counting input of the address counter, the output is “Equal” to the comparison circuit is connected to the first input of the control encoder, the data input of the receiver is connected to the data input of the controller, the output of the transmitter is connected to the output the controller.

 A disadvantage of the known controller is the large hardware costs required to implement control registers, state registers, and a control encoder in cases where the controller requires a significant number of control registers and state registers for storing state and control words. Since the control information contained in the control words and the state words is exchanged through the control registers and state registers between the computer and the known controller, the hardware costs of implementing the control encoder are required to process the control information and generate control signals from the results of processing the state words and control words, executed on the elements of rigid logic, the more, the greater the number of control registers and state registers is used, since each p zryad control registers and status registers connected to a respective control input of the encoder. The use of flexible logic elements, such as microprocessors, for the implementation of a control encoder is limited by the time characteristics of known controllers, for which data exchange should be carried out in real time.

 A disadvantage of the known controller is the limitation of the scope in cases where the use of a large number of control registers and states is impossible due to the limited address space of the computer address bus allocated for addressing external registers. So, when using a computer of the microprocessor of the 580 series, the address space of 256 addresses is allocated for addressing external registers, which limits the possibility of using the controller if it requires more than 256 control registers and state registers.

 The purpose of the invention is the expansion of the scope of the controller while reducing hardware costs for its implementation.

 The goal is achieved by the fact that in the controller containing the bus controller, interface, address selector, address counter, address register, comparison circuit, receiver, transmitter, control encoder, the inputs and outputs of the bus controller are connected to the controller system bus, the first group of inputs the interface outputs are connected to the controller data bus, the second group of its inputs and outputs is connected to the controller address bus, its data inputs are connected to the internal controller bus, its address outputs are to the address inputs of the address selector, times the core outputs of the address counter are connected to the inputs of the address of the interface and to the first group of inputs of the comparison circuit, the second group of inputs of which the outputs of the address register are connected, the inputs of the address counter data and the information inputs of the address register are connected to the internal bus of the controller, the input of the address counter record, the input of the register record addresses, the second group of control inputs of the interface, the third group of control inputs of the bus controller, the second group of control inputs of the transmitter, the second group of control inputs of the receiver, the first The control encoder outputs are connected to the controller control bus, the bus controller output is connected to the counting input of the address counter, the output is “Equal” to the comparison circuit connected to the first input of the control encoder, the receiver data input is connected to the controller data input, the transmitter output is connected to the controller output, input RAM, memory, register device, interrupt controller, multiplexer, while the control outputs of the bus controller are connected to the control inputs of the address selector, to the first group of interface control inputs, the first group of receiver control inputs and the first group of transmitter control inputs, the first group of bus controller control inputs is connected to the transmitter control outputs, the second group of bus controller control inputs is connected to the receiver control outputs, receiver inputs and outputs, inputs - transmitter outputs, inputs / outputs of RAM, inputs / outputs of a register device, the first group of address inputs of a memory device are connected to the outputs of the multiplexer and to the internal bus of the controller, the outputs of the receiver are connected to the inputs of the interface, the inputs of the transmitter are connected to the outputs of the interface, the inputs of the address of the RAM are connected to the first group of outputs of the register device, the outputs of the storage device are connected to the third group of inputs of the register device, the outputs of the states of the storage device are connected to the first group inputs of the control encoder, the second group of address inputs of the storage device is connected to the second group of outputs of the register device, the first the group of inputs of the register device is connected to the second group of outputs of the control encoder, the second group of inputs of the register device is connected to the third group of outputs of the control encoder, the third group of outputs of the register device is connected to the control inputs of the storage device, the control input of the encoder control is connected to the transfer output of the storage device, transfer input which is connected to the first output of the control encoder, the second group of inputs of the control encoder and the first group of request inputs and the interrupt controller is connected to the receiver status outputs, the transmitter status outputs are connected to the third group of inputs of the control encoder and to the second group of request inputs of the interrupt controller, to the third group of request inputs of which and the fourth group of inputs of the encoder control bus controller outputs are connected, the address selector outputs are connected with the fourth group of interrupt controller request inputs, the second control encoder output is connected to the interrupt controller request input, cat control output It is connected to the second input of the control encoder, the synchronization input of the interrupt controller and the synchronization input of the register device are connected to the third output of the control encoder, the outputs of the interrupt controller are connected to the fifth group of inputs, the outputs of the interface address are connected to the first group of inputs of the multiplexer, the second group of inputs of which are connected interface data outputs, the “Equal to” output of the comparison circuit is connected to the receiver control input and to the transmitter input, control priority control inputs interrupt manager, RAM control inputs, multiplexer control inputs, register device control inputs are connected to the controller control bus.

 Introduction to the controller of RAM, memory, register device, interrupt controller and multiplexer in the above relationship allows you to expand the scope of the controller while reducing hardware costs for its implementation.

 The extension of the scope of the controller is expressed in the fact that it can be used in systems that exchange real-time data and use computers with a limited address bus address space reserved for addressing external device registers, which limits the number of control registers and state registers in the device, to which computers can access in program exchange mode. An example of computers having a limited address space for the address bus can be computers built using microprocessors of the 580 series, as well as computers of the Electronics 60 series. The expansion of the controller’s scope is explained by the fact that the exchange of control words and status words between the computer and the controller is carried out not only in the program exchange mode, but also in the mode of direct access to the computer’s RAM from the controller, and the conditions for real-time data exchange as well as the conditions for processing state words and control and formation words according to the results of processing control actions in real time are fulfilled. The use of RAM, storage device, register device, multiplexer and interrupt controller when the controller is in direct access to the main memory of the computer allows the exchange of state words, control words between the main memory of the computer and the main memory of the controller, and also allows for the accelerated processing of state words and the control words and, based on the results of this processing, control the controller operating modes in real-time data exchange. RAM is used to store state words and control words that the computer and the controller exchange in the modes of program exchange and direct access to the computer memory. The use of RAM allows you to reduce the cost of the registers needed to store control words and state words. However, this raises the problem of generating control signals from the processing of state words and control words, since these control signals must be generated in time intervals not greater than necessary to ensure real-time data exchange. The use of a storage device allows processing of bits of state words and control words for limited time intervals and generating control signals from the processing results for transferring the controller to various operating modes, during which real-time processes of exchanging state words, control words in program exchange mode and in direct access to computer memory and data exchange processes. The use of RAM, interrupt controller, memory, multiplexer allows to reduce hardware costs for the implementation of the controller, which operates in real time data exchange while expanding its scope, firstly, by reducing hardware costs for the implementation of state registers and control registers, since state words and control words are stored in RAM, and secondly, by reducing hardware costs for the control encoder, p d which performs machining control words and control words states and running controller which executes processing operations, formation and exchange of data between computers, controller, transmitter and receiver. The use of a storage device, while maintaining the controller’s operability in real-time data exchange between a computer, controller, receiver and transmitter, reduces the hardware costs of a control encoder that uses hard logic elements in the prototype connected by communication lines to each of the bits of control registers and state registers. Instead of hard logic elements, a storage device is used for processing and converting state words and control words, which is achieved by storing the results of arithmetic and logical pressure operations in the memory cells of the storage device, which are supplied to the first and second groups of address inputs of the storage device. A set of non-standard and standard arithmetic and logical operations, the results of which are stored in a storage device, can reduce the data processing time and, at the required time intervals, generate control signals at the outputs of the storage device states that are supplied to the control encoder. The set of operations performed by the storage device is selected individually for each of the options of the controller. The use of the interrupt controller makes it possible in real-time controller operation to provide data exchange between computers, random access memory, receiver and transmitter, and arbitrate real-time processes. Using an interrupt controller in conjunction with a storage device, a register device, and a multiplexer allows real-time data exchange between a computer, receiver, transmitter, and controller. Using the multiplexer allows you to switch to the first group of address inputs of the memory device address signals from the address bus of the controller or data signals from the data bus of the controller, which is necessary for processing control words and status words by the storage device. The use of a register device allows for temporary storage of data during the exchange of data between RAM, storage device, computer, receiver and transmitter.

 In FIG. 1 shows a block diagram of a controller; in FIG. 2 is a structural diagram of connecting a computer through a controller to a communication channel; in FIG. 3 is a structural diagram of a storage device; in FIG. 4 is a block diagram of an interface; in FIG. 5 is a block diagram of a bus controller; in FIG. 6 is a block diagram of a register device; in FIG. 7 is a block diagram of an interrupt controller; in FIG. 8 is a structural diagram of a control encoder; in FIG. 9 is a structural diagram of a micro command address generator; in FIG. 10 is a block diagram of a receiver; in FIG. 11 is a structural diagram of a transmitter; in FIG. 12 shows an example implementation of an encoder circuit; in FIG. 13 is an example implementation of a decoder circuit; in FIG. 14 is a structural diagram of a cyclic control logic; in FIG. 15 is a structural diagram of a reverse store type memory (Fifo circuit); in FIG. 16 shows a format of data packets transmitted to a communication channel; in FIG. 17 is a format for transmit buffer descriptors and receive buffers. Descriptors describe computer memory zones (receive and transmit buffers) allocated for storage of received and transmitted data, as well as state words describing the process of data exchange.

 The controller contains (Fig. 1) an interface 1, a bus controller 2, an address counter 3, an address register 4, a comparison circuit 5, a random access memory 6, a memory device 7, a register device 8, an interrupt controller 9, an address selector 10, a control encoder 11, receiver 12, transmitter 13, multiplexer 14.

 Through the internal bus 15, the control bus 16, through the data bus 17, the address bus 18, the control system bus 19, the controller 20 (Fig. 2) is connected to the computer 21. The first group of inputs and outputs of the interface 1 is connected to the controller data bus 17, the second the input-output group of interface 1 is connected to the controller address bus 18. The data bus 17 is connected to the computer data bus, the address bus 18 to the computer address bus, the controller system bus 19 is connected to the computer system bus. The inputs and outputs of the bus controller 2 are connected to the control system bus 19. On line 22 through the controller data input and on line 23 through its output, the controller is connected to communication channel 24. The control input of the receiver 12 is connected to the controller data input, and the output of the transmitter 13 is connected to the controller output. Through the bus 25, the bit outputs of the counter 3 addresses are connected to the first group of inputs of the comparison circuit 5 and to the inputs of the address of the interface 1. The outputs of the register 4 addresses are connected to the second group of inputs of the comparison circuit 5. The inputs of the interface 1 through the bus 26 are connected to the outputs of the receiver 12, and its outputs via the bus 27 are connected to the inputs of the transmitter 13. On the bus 28, the data outputs of the interface 1 are connected by a second group of inputs of the multiplexer 14, the first group of inputs of which and the address inputs of the address selector 10 are connected by bus 29 with outputs of the address of interface 1. On bus 30, the first group of control inputs of the interface 1, the first group of control inputs of the receiver 12, the first group of control inputs of the transmitter 13, the control inputs of the address selector 10 are connected to the control outputs of the con roller 2 of the tire. On bus 31, the fourth group of inputs of the control encoder 11 and the third group of request inputs of the interrupt controller 9 are connected to the outputs of the bus controller 2, the output of which is connected via line 32 to the counting input of the address counter 3. The first group of control inputs of the bus controller 2 on the bus 33 is connected to the control outputs of the transmitter 13, and the second group of control inputs on the bus 34 is connected to the control outputs of the receiver 12. The status outputs of the receiver 12 are connected via bus 35 to the second group of inputs of the control encoder 11 and to the first the group of inputs of the request controller 9 interrupts. The status outputs of the transmitter 13 are connected via bus 36 to the third group of inputs of the control encoder 11 and to the second group of request inputs of the interrupt controller 9. The inputs of the address of the RAM 6 are connected via bus 37 to the first group of outputs of the register device 8. The outputs of the memory device 7 are connected via bus 38 to the third group of inputs of the register device 8. The second group of outputs of the control encoder 11 is connected via bus 39 to the first group of inputs of the register device 8 Line 40 connects the control input of the control encoder 11 to the transfer output of the storage device 7, to the transfer input of which via line 41 the first output of the control encoder 11 is connected. The fifth group of inputs of the control encoder 11 is connected via bus 42 to the outputs of the interrupt controller 9, the request input of which is connected via line 43 to the second output of the control encoder 11, the control output is connected via line 44 to the second input of the control encoder 11, and the synchronization input and register synchronization input devices 8 are connected via line 45 to the third output of the control encoder 11. The outputs of the address selector 10 are connected via bus 46 to the fourth group of input requests of the controller 9 interrupts. The output of "Equal" comparison circuit 5 is connected via line 47 to the control input of the receiver 12, to the control input of the transmitter 13, to the first input of the control encoder 11. The third group of outputs of the control encoder 11 is connected to the second group of inputs of the register device 8 via the bus 48. The third group of outputs of the register device 8 via the bus 49 is connected to the control inputs of the memory device 7, the second group of outputs of the register device 8 is connected via bus 50 to the second group of address inputs memory device 7. The status outputs of the memory device 7 via bus 51 are connected to the first group of inputs of the control encoder 11. To the internal bus 15 of the controller are connected the data inputs of the counter 3 addresses, the information inputs of the register 4 addresses, the outputs of the multiplexer 14, the data inputs of the interface 1, the inputs and outputs of the transmitter 13, the inputs and outputs of the receiver 12, the inputs and outputs of the RAM 6, the inputs and outputs of the register devices 8, the first group of address inputs of the storage device 7. To the control bus 16 of the controller are connected the first group of outputs of the control encoder 11, the input of the counter counter 3 addresses, the input of the register register 4 addresses, the second group of control inputs of the interface 1, control inputs of multiplexer 14, control inputs of RAM 6, control inputs of register device 8, third group of control inputs of controller 2 of the bus, second group of control inputs of receiver 12, second group of control inputs of transmitter 13, priority control inputs of controller 9 interrupts.

 The storage device 7 contains (Fig. 3) sections 52 and a storage device 53 accelerated transfers. The first and second groups of address inputs of the storage device 7, as well as its outputs contain groups of lines. The number of line groups in the first group of address inputs is equal to the number of line groups in the second group of address inputs, equal to the number of line groups of outputs of the memory device 7. For example, with the number of sections equal to four, the first, second groups of address inputs and outputs of the memory device 7 contain four groups of lines, each of the line groups of the first group of address inputs of the storage device 7 is connected to the first group of inputs of one of the sections 52 of the memory device, and each of the line groups of the second group of address inputs the storage device 7 is connected to the second group of inputs of one of the sections 52 of the storage device, the third group of inputs of the sections 52 of the storage device are connected to the input inputs of the storage device 7. The transfer inputs of each of the sections 52 of the storage device are connected to one of the output groups of the transfer outputs of the accelerated transfer storage device 53 , each of the groups of transfer inputs of which is connected to the transfer outputs of one of the sections 52 of the storage device. The transfer input of the storage device 7 is connected to the transfer input of the first section 52 of the storage device and to the transfer input of the fast transfer storage device 53, the transfer output of the storage device 7 is connected to the transfer output of the fast transfer storage device 53. Each of the groups of output lines of the storage device 7 is connected to the outputs of one of the sections 52 of the storage device and to the outputs of the states of the storage device 7. The control inputs of the storage device 53 of the accelerated transfers are connected to the control inputs of the storage device 7.

 To implement section 52 of the storage device, a permanent programmable storage device is used, the input address of which is connected to the transfer input of the section of the storage device. The first group of address inputs of the latter is connected to the first group of inputs of the storage section 52, the second group of address inputs is connected to the second group of inputs of the storage section, the third group of address inputs is connected to the third group of inputs of the storage section, the fourth group of address inputs is connected to section transfer inputs a storage device, and the first group of outputs is connected to the transfer outputs of the storage section of the device, the second group of outputs is connected to the outputs of the storage section of the storage device royals.

 The memory device 53 accelerated transfers is implemented on a permanent programmable memory device, and with each of the groups of inputs of the transfer of the memory device 53 accelerated transfers connected to one of the groups of inputs of the address of the permanent programmable memory device, the input address of which is connected to the transfer input of the memory device 53 accelerated transfers, and each of the groups of outputs connected to one of the groups of outputs of the transfer of the storage device 53 accelerated transfers, the output of which is connected n with the transfer output of the accelerated carry memory 53, and a separate group of address inputs is connected to the control inputs of the accelerated carry memory 53.

 Interface 1 contains (Fig. 4) address bus amplifiers 54 and data bus amplifiers 55, register 56, switch 57. Inputs and outputs address bus amplifiers 54 are connected to a second group of inputs and outputs of interface 1, the first group of inputs and outputs of which are connected to inputs - outputs of amplifiers 55 data bus. The inputs of the amplifiers 54 of the address bus are connected to the inputs of the address of the interface 1, to the outputs of the address of which the outputs of the amplifiers 54 of the address bus are connected. The outputs of the data bus amplifiers 55 are connected to the data outputs and to the outputs of the interface 1. The first group of inputs of the switch 57 is connected to the data inputs of the interface 1, the second group of inputs of the switch 57 is connected to the inputs of the interface 1. The outputs of the switch 57 are connected to the inputs of the register 56, the outputs of which are connected with inputs of amplifiers 55 data bus. The first group of control inputs of the amplifiers 54 of the address bus, the first group of control inputs of the amplifiers 55 of the data bus, the first control input of the register register 56, the first control input of the switch 57 are connected to the first group of control inputs of the interface 1, the second group of control inputs of which are connected to the second group of control inputs amplifiers 54 of the address bus, with a second group of control inputs for amplifiers 55 of the data bus, with a second input for register write control 56, with a second control input for switch 57.

 The bus controller 2 contains (Fig. 5) amplifiers 58, a decoder 59, a timer device 60. The inputs and outputs of the amplifiers 58 are connected to the inputs and outputs of the bus controller 2, the outputs of which are connected to the first group of outputs of the decoder 59. The inputs of the amplifiers 58 are connected to the second group the outputs of the decoder 59, the first group of inputs of which are connected to the outputs of the amplifiers 58. The third group of outputs of the decoder 59 is connected to the control outputs of the bus controller 2, the second group of inputs of the decoder 59 is connected to the third group of control inputs of the controller 2 w us. The fourth group of outputs of the decoder 59 is connected to the inputs of the timer device 60, the outputs of which are connected to the third group of inputs of the decoder 59. The fourth group of inputs of the decoder 59 is connected to the first group of control inputs of the bus controller 2, the second group of control inputs of which are connected to the fifth group of inputs of the decoder 59. The output of the decoder 59 is connected to the output of the bus controller 2, the control output of the decoder 59 is connected to the control input of the amplifiers 58.

 The register device 8 contains (Fig. 6) a multiplexer 61, a multiplexer 62, registers 63, amplifiers 64, a reversible counter 65. Control inputs of amplifiers 64, control inputs of a multiplexer 61, control inputs of a multiplexer 62, control inputs of registers 63, control inputs of a reversible counter 65 connected to the control inputs of the register device 8, the first group of inputs of which is connected to the first group of inputs of the multiplexer 62. The second group of inputs of the multiplexer 62 is connected to the second group of inputs of the register device 8. Third the inputs of the multiplexer 62 are connected to the outputs of the amplifiers 64. The third group of inputs of the register device 8 is connected to the fourth group of inputs of the multiplexer 62. The inputs and outputs of the register device 8 are connected to the inputs and outputs of amplifiers 64, to the inputs of which the first group of outputs of the multiplexer 61 is connected. The first group the outputs of the register device 8 is connected to the second group of outputs of the multiplexer 61, its second group of outputs is connected to the third group of outputs of the multiplexer 61, and its third group of outputs is connected to a gated group of outputs of the multiplexer 61. The synchronization inputs of the registers 63 and the synchronization input of the reverse counter 65 are connected to the synchronization input of the register device 8. The multiplexer 62 has several groups of outputs, and the inputs of each of the registers 63 are connected to one of the output groups of the multiplexer 62. The multiplexer 61 contains several groups of inputs, and the outputs of each of the registers 63 are connected to one of the groups of inputs of the multiplexer 61. The outputs of the reverse counter 65 are connected to the inputs of the addresses of the registers 63.

 The interrupt controller 9 contains (Fig. 7) a logic matrix 66, which can be used, for example, a programmable logic matrix, register 67. The outputs of the register 67 are connected to the outputs of the controller 9 interrupts and with the first group of inputs of the logic matrix 66, to the second group of inputs which connects the priority control inputs of the controller 9 interruptions, to the third group of inputs connected the first group of request inputs of the controller 9 interruptions, to the fourth group of inputs connected the second group of request inputs of the controller 9 interrupts, the third group of request inputs of the controller 9 interrupts is connected to the fifth group of inputs, the fourth group of inputs of the controller requests 9 interrupts is connected to the sixth group of inputs, the request input of the controller 9 interrupts is connected to the input, and the outputs are connected to the inputs of register 67, the output is connected to the control input register 67. The control output of the interrupt controller 9 is connected to the output of the register 67, the synchronization input of which is connected to the synchronization input of the bus controller 2.

 The control encoder 11 contains (Fig. 8) a microcommand register 68, a multiplexer 69, a microcommand memory 70, which is used, for example, read-only programmable memory, a multiplexer 71, a decoder 72 — a start address converter, a micro command address generator 73, a condition multiplexer 74 , generator 75, multiplexer 76, counter 77 — timer, decoder 78, RS flip-flop 79, control bus 80.

 The outputs of the micro-command address generator 73 are connected to the bus 81. Its output is connected to the line 82, its address inputs, instruction inputs, and the increment input are connected to the control bus 80. Its condition input is connected to line 83, the synchronization input to line 45. The second group of outputs of the control encoder 11 is connected to the outputs of the multiplexer 69, the first group of inputs of which is connected to the outputs of the counter-timer 77 and to the inputs of the decoder 78. The first group of outputs of the control encoder 11 connected to the first group of outputs of the register 68 microcommands, the inputs of which are connected to the first group of outputs of the memory 70 microcommands. The control inputs and the first input of the multiplexer 76, the control inputs of the multiplexer 71, the address inputs, instruction inputs, the increment input of the shaper 73 of the micro command address, the reset input of the counter-timer 77, the R-input of the RS flip-flop 79, the control inputs of the multiplexer 74 conditions, the second group of outputs register 68 are connected to the bus 80. The control input of the multiplexer 69 is connected to the output of the memory 70 microcommands. The second group of outputs of the micro-command memory 70 is connected to the second group of inputs of the multiplexer 69. The output of the generator 75 is connected to the counting input of the counter-timer 77, to the write input of the micro-command register 68, to the synchronization input of the micro-command address generator 73, with the third output of the control encoder 11. The inputs of the memory address of the microcircuit 70 are connected to the outputs of the multiplexer 71, the first group of inputs is connected to the outputs of the microcircuit address generator 73, the second group of inputs is connected to the outputs of the initial address decoder-transformer 72, the third group of inputs is connected to the fifth group of inputs of the control encoder 11, and the first the control input is connected to the second input of the control encoder. The inputs of the decoder-converter 72 of the starting address are connected to the first group of inputs of the control encoder 11. The output of the micro command address generator 73 is connected to the second control input of the multiplexer 71. The conditions input of the micro command address generator 73 is connected to the output of the condition multiplexer 74, the first group of inputs of which is connected to the third group of inputs of the control encoder 11, its second group of inputs is connected to the fourth group of inputs of the control encoder , the third group of inputs is connected to the second group of inputs of the control encoder, and its first input and second input of the multiplexer 76 are connected to the control input of the control encoder Niya. The second input of the condition multiplexer 74 is connected to the first input of the control encoder 11. The output of the decoder 78 is connected to the S-input of the RS-flip-flop 79, the output of which is connected to the second output of the control encoder 11. The output of the multiplexer 76 is connected to the second output of the control encoder. The third group of outputs of the micro-instruction memory 70 is connected to the third group of outputs of the control encoder 11.

 The micro-command address generator 73 (Fig. 9) contains a register 84, an adder 85, a stack 86, a reverse counter 87 — a stack pointer, a multiplexer 88, an instruction decoder 89. The outputs of the multiplexer 88 are connected to the outputs of the micro-command address generator 73 and to the inputs of the adder 85, the increment input of which is connected to the increment input of the micro-command address generator 73, and the outputs are connected to the inputs of the register 84. The addresses of the micro-command address generator 73 are connected to the first group of inputs of the multiplexer 88, the outputs of the stack 84 are connected to the second group of inputs of which the outputs of the stack 86 are connected, and the outputs of the register 84 are connected to the third group of inputs and to the inputs of the stack 86. by the instructions decoder 89, the condition input of which is connected to the conditions input of the micro command address generator 73, the control outputs are connected to the control inputs of the multiplexer 88, and the output is connected to the control input of the counter counter-pointer 87 of the stack and to the control input of the stack 86. The output of the decoder 89 is connected with the output of the shaper 73 addresses of the micro command. The synchronization input of the micro-instruction address generator 73 is connected to the counting input of the reverse counter-pointer 87 of the stack, with the synchronization input of the stack, with the synchronization input of the register 84. The outputs of the reverse counter-pointer 87 of the stack are connected to the inputs of the address of the stack 86.

 An example implementation of receiver 12 is shown in FIG. 10. The receiver contains Fifo 90 reception, a multiplexer 91, a shift register 92, a flag detector 93, an RS flip-flop 94, a loopback logic 95, a decoder 96, an input signal detector 97, a counter 98 bits, a counter 99 bytes, a control logic 100, a bus 101. The outputs of the FIFO reception 90 on the bus 26 are connected to the outputs of the receiver 12 and to the first group of inputs of the multiplexer 91. The outputs of the FIFO labels 90 of the reception on the bus 102 are connected to the first group of inputs of the control logic 100. The outputs of the shift register 92 are connected via the bus 103 to the inputs of the FIFO 90 receptions and with detector inputs 93 flags, exit which is connected to S-input of RS-flip-flop 94. The output of the decoder 96 is connected via line 104 to the input of shift register 92 and to the input of the control logic 95 cyclic. The synchronization output of the decoder 96 is connected via line 105 to the synchronization input of the shift register 92, with the synchronization input of the cyclic control logic 95 and with the counting input of the 98-bit counter. The input of the decoder 96 and the input of the detector 97 of the input signal are connected to the data input of the receiver 12. The output of the logic control 95 of the cyclic control via line 106 is connected to the first input of the multiplexer 91. The output of the RS-trigger 94 is connected to the reset input of the counter 98 bits, the outputs of which are connected to the second the group of inputs of the control logic 100 and with the second group of inputs of the multiplexer 91. The outputs of the multiplexer 91 are connected to the inputs-outputs of the receiver 12. The output of the detector 97 of the input signal is connected to the second input of the multiplexer 91 and to the second input of the control loop geeks 100. The outputs of the 99-byte counter are connected to the third group of inputs of the multiplexer 91 and to the third group of inputs of the control logic 100, with the fourth group of inputs of which the second group of inputs of the receiver control is connected. The status outputs and control outputs of the receiver 12, control inputs and inputs of the FIFO labels 90 of the reception, control inputs of the multiplexer 91, control inputs of the logic 95 of cyclic control, counting input and reset input of the counter 99 bytes, R-input of the RS flip-flop 94, outputs of the control logic 100 connected to the bus 101. The fifth group of inputs of the control logic 100 is connected to the first group of inputs of the control of the receiver 12, to the inputs and outputs of which a sixth group of inputs of the control logic 100 is connected. The control input of the receiver 12 is connected to the input of the control logic 100.

 An example of transmitter 13 is shown in FIG. 11. The transmitter contains FIFO 107 transmission, shift register 108, logic 109 cyclic control, switch 110, encoder 111, counter 112 bits, control logic 113, amplifiers 114, generator 115, bus 116. The outputs of FIFO 107 transmission are connected via bus 117 with inputs register 108 shift, the output of which is connected via line 118 to the first input of the switch 110 and to the input of the logic 109 of cyclic control. The output of the generator 115 via line 119 is connected to the synchronization input of the encoder 111, to the synchronization input of the control logic 113, to the synchronization input of the shift register 108, to the synchronization input of the cyclic control logic 109, to the counter input of the 112 bit counter. The data output of the logic 109 of cyclic control is connected via line 120 to the second input of the switch 110, the output of which is connected via line 121 to the input of encoder 111. The output of the encoder is connected to the output of transmitter 13. The inputs and outputs of the transmitter are connected to the fifth group of inputs of control logic 113 and to the outputs amplifiers 114. The control inputs and inputs of amplifiers 114, the status outputs and control outputs of the transmitter 13, the label inputs and the control inputs of the transmission FIFO 107, the input of the shift register 108, the control inputs of the logic 109 of the cyclic control, the control input the switch 110, the reset input of the counter 112 bits, the control input of the encoder 111, the outputs of the control logic 113 are connected to the bus 116. The outputs of the tags Fifo 107 transmission are connected via bus 122 to the first group of inputs of the control logic 113, with the second group of inputs of which the outputs of the counter 112 bits are connected , a second group of transmitter control inputs 13 is connected to a third group of inputs, and a first group of transmitter control inputs is connected to a fourth group of inputs. The inputs of the transmitter 13 are connected via bus 27 to the inputs of the fifo 107 transmission. The input of the transmitter 13 is connected to the input of the control logic 113.

 An exemplary embodiment of encoder 111 is shown in FIG. 12. The encoder contains a diode 123, a resistor 124, an inverter 125, coincidence circuits 126, 127, JK flip-flops 128, 129. The input of the inverter 125 and the first input of the coincidence circuit 126 are connected to the input of the encoder 111. The output of the inverter 125 is connected to the first input of the circuit 127 matches. The second input of the coincidence circuit 126 and the second input of the coincidence circuit 127 are connected to the inverse output of the JK flip-flop 129, the J- and K-inputs of which are connected through the resistor 124 to the power bus to set the level to "1". The output of the match circuit 126 is connected to the J-input of the JK flip-flop 128, to the K-input of which the output of the match circuit 127 is connected. The synchronization input of the JK trigger 128 and the synchronization input of the JK trigger 129 are connected to the synchronization input of the encoder 111. The output of the JK trigger 128 through the diode 123 is connected to the output of the encoder 111.

 An exemplary embodiment of decoder 96 is shown in FIG. 13. The decoder comprises a delay line 130, an EXCLUSIVE OR circuit 131, 132, an inverter 133, D-flip-flops 134, 135. An input of the delay line 130, a first input of an EXCLUSIVE OR 131 circuit, the D-input of the D-flip-flop 135 are connected to the input of the decoder 96. The second input of the EXCLUSIVE OR circuit 131 is connected to the first output of the delay line 130, the second output of which is connected to the first input of the EXCLUSIVE OR circuit 132, and the third output is connected to the second input of the circuit EXCLUSIVE OR 132. The output of the circuit EXCLUSIVE OR 131 is connected to the input of inverter 133, the output which is connected to the D-input of D-flip-flop 134. The circuit output is EXCLUSIVE LI 132 is connected to the input of sync D-flip-flop 134, whose output is connected to the output of sync decoder 96 and to the D-input of synchronization flip-flop 135. Inverted output of D-flip-flop 135 is connected to the output of the decoder 96.

 The controllers 20 are connected to the communication channel 24 through some distances. Such connections can be made, for example, by puncturing the coaxial cable used to implement the communication channel 24. In this case, matching loads 136 are installed at the ends of the coaxial cable (Fig. 2).

The logic 109 of the cyclic control of the transmitter 13 and the logic 95 of the cyclic control of the receiver 12 implement data verification using the polynomial x ¹⁵ + x ¹² + x ⁵ +1 and are constructed according to the same scheme (Fig. 14), which includes the circuit EXCLUSIVE OR 137, the scheme 138 matches, five-bit shift register 139, EX-OR circuit 140, seven-bit shift register 141, EX-OR circuit 142, five-digit shift register 143, multiplexer 144, decoder 145. The input of the cyclic control logic is connected to the first input of the circuit EXCLUSIVELY the multiplexer 144. The synchronization logic input is connected via line 119 for the transmitter 13 and via line 105 to the receiver 12 with the synchronization inputs of the registers 139, 141, 143. The control inputs of the cyclic control logic are connected to the first input of the match circuit 138 and the control inputs of the multiplexer 144 The data output of the cyclic control logic is connected to the output of the multiplexer 144, to the second input of which and the second input of the EXCLUSIVE OR 137 circuit, the output of the shift register 143 is connected. The output of the EXCLUSIVE OR 137 circuit is connected to w the next input of the coincidence circuit 138, the output of which is connected to the input of the shift register 139, with the first inputs of the EXCLUSIVE OR circuit 140, 142. The output of the register 139 is connected to the second input of the circuit EXCLUSIVE OR 140, the output of which is connected to the input of the shift register 141. The output of the shift register 141 connected to the second input of the EXCLUSIVE OR circuit 142, the output of which is connected to the input of the shift register 143. The outputs of the shift register 139 are connected to the first group of inputs of the decoder 145. The outputs of the shift register 141 are connected to the second group of inputs of the decoder and 145. The outputs of the shift register 143 are connected to the third group of inputs of the decoder 145, the output of which is connected to the control output of the cyclic control logic.

 Fifo 90 reception and Fifo 107 transmission are reverse store type memory, which includes (Fig. 15) RAM 146, RAM 147, multiplexer 148, counters 149, 150. The FIFO inputs are connected to the inputs of the RAM 146, to the outputs of which are connected Fifo exits. The FIFO inputs are connected to the inputs of the RAM 147, to the outputs of which the outputs of the FIFO labels are connected. Fifo control inputs are connected to the control inputs of RAM 146, RAM 147, multiplexer 148, counters 149, 150. The outputs of the counter 149 are connected to the first group of inputs of the multiplexer 148, the outputs of the counter 150 are connected to the second group of inputs. The outputs of the multiplexer 148 are connected to the inputs RAM addresses 146 and RAM 147.

 The storage device 7 is designed to store the results of arithmetic and logical operations on the data. The operands go to the first and second groups of address inputs of the memory device 7, if operations are performed on two operands, or go only to the first group of address inputs of the memory device 7, if operations are performed on one operand, while the second group of inputs is used to expand the bit depth of control signals memory device 7. In the latter case, the code of the operation to be performed is supplied to the second group of address inputs and to the control inputs of the memory device 7.

 The storage device 7 may be implemented, for example, on the basis of read-only programmable storage devices or programmable logic arrays. Programming persistent programmable storage devices or programmable logic arrays is done before the controller is assembled.

 The storage device 7 performs the functions of an arithmetic-logical device with a non-standard set of arithmetic and logical commands, which is selected individually for each specific controller execution. A set of arithmetic and logical commands is implemented by programming permanent programmable storage devices or programmable logic matrices that are part of the storage device 7. A non-standard set of arithmetic and logical commands when programming the storage device 7 is selected so as to increase the speed of the controller and, in particular, due to this to achieve a reduction in hardware costs and the expansion of its functions.

 When using permanent programmable storage devices to build a storage device 7 in their memory cells should be recorded the results of logical and arithmetic operations on operands that are fed to their address inputs.

 An example of a non-standard arithmetic operation programmed in the storage device 7 can be a subtraction operation performed on the storage device. The execution time of such an operation is shorter than the execution time of a similar operation on standard arithmetic-logic devices, since this operation does not require the translation of one of the operands into additional code. Programming should be performed in such a way that the result of the operation is read to the outputs of the storage device 7 when the operands are supplied to the first and second groups of its inputs, when the operation code is supplied to the control inputs and when the input transfer signal is applied to the transfer input of the storage device 7.

 Another example of an operation is the operation of multiplication by a constant. In this case, the storage device 7 should be programmed in such a way that when the multiplier is supplied to the first group of address inputs and when the operation code is supplied to the control inputs, the result of the operation is read at the outputs of the memory cells of the storage device 7, and the transfer output of the storage device 7 could indicate that the result of the operation does not fit in one word. In this case, the storage device 7 is programmed so that when the operation code is retrieved from the storage device 7 for the next word of the result of the multiplication operation, the next word of the result of the operation is read at the outputs of the storage device 7.

 If the storage device 7 is made single-section based on programmable read-only memory, then the first group of address inputs of the storage device 7 is connected to the first group of address inputs of the programmable read-only memory, the second group of address inputs of which are connected to the second group of address inputs of the storage device 7, the third group of inputs the address is connected to the control inputs of the storage device 7, the outputs are connected to the outputs of the storage device 7, the address sa connected to the input transfer memory 7 and output - with output transfer storage devices 7.

 To perform the subtraction operation, the programmable read-only memory devices are pre-programmed before the controller is assembled in such a way that when the subtraction operation code is supplied to the control inputs of the memory device 7, it is reduced to the first group of its address inputs, the code is deducted to the outputs of the programmable constant memory device, which are the outputs of the memory device 7, from its memory cells are read codes of numbers, which are the difference of the mind shaemogo and subtract. If the reducible is less than the subtracted, then the output transfer signal is read out from the memory cell, the address of which is determined by the codes to be reduced, subtracted and the operation code, at the transfer output of the storage device 7, which is the output of the programmable read-only memory device. The input transfer signal connected to one of the address inputs of the programmable read-only memory also affects the result of the operation, since the corresponding memory cell is selected.

 If the address inputs of the programmable read-only memory are not enough to perform operations on multi-digit numbers, then the storage device 7 is partitioned. Each of the storage section 52 may be performed based on programmable read-only memory. In this case, the first group of inputs of section 52 of the storage device is intended to supply several bits of the reducible, the second group of inputs is several bits of the subtracted, the third group of inputs is the operation code, the transfer inputs of section 52 of the storage device are the output signals from the outputs of the transfer of the memory device 53 of accelerated transfers, inputs the transfer of which is intended to supply propagation signals and transfer generation from the transfer outputs of section 52 of the storage device. The transfer input of the storage device 53 accelerated transfers and the transfer input section 52 of the storage device are designed to supply them with an input transfer signal. The control inputs of the storage device 53 serves to supply them with operation code signals.

 The memory device 53 accelerated transfers can be performed, for example, on the basis of a programmable logic matrix or programmable read-only memory, which are programmed in advance before the controller is assembled so that when the transfer propagation signals and transfer generation are transferred to the transfer inputs from the transfer outputs of the storage section 52 of the storage device at the outputs of the transfers of the memory device 53 accelerated transfers generated signals of input transfers for each of the sections 52 inayuschego devices based on those signals which outputs operation result is generated.

 Similarly, by programming in the memory cells of the storage device 7 of the results of operations, operations of addition, shift, logical addition and multiplication are realized. In addition, the logical operations of code conversion are implemented, for example, the conversion of address codes from the bus 18 of the controller address to the address codes of RAM cells 6. The logical operations of converting state and control words to control codes are implemented, which are supplied from the outputs of the states of the memory device 7 to the first group of inputs encoder 11 control. According to these control codes, the controller switches to a particular operating mode.

 Each of the operations performed on the storage device 7 is programmed in such a way as to minimize the response time of the controller to process external influences and achieve real-time processes, for example, to ensure the exchange of data (control and state words) between the controller data bus 17 and RAM 6 in the mode of program exchange from the side of the computer 21 during the time allotted for the read and write modes on the data bus 17. The operations performed on the storage device 7, for example, allow filtering received packets from the communication channel 24 by the destination addresses of these packets for periods of time not exceeding the packet receiving time of the minimum length.

 To expand the ability of the memory device 7 to store in its memory cells the results of arithmetic and logical operations on operands supplied to its inputs when performing single-operand commands, the second group of address inputs of the memory device 7 is used as a group of control inputs, the control signals are supplied from the second and the third group of memory outputs 70 microcommands through a register device 8.

 The interrupt controller 9 provides arbitration of internal interrupt requests and generates an internal interrupt vector at its outputs to transfer the controller to a new operating mode.

 As the logic matrix 66, a programmable logic matrix programmable prior to installation in the controller may be used. Programming is performed in such a way that the programmable logic matrix generates vector signals at its outputs, the value of which is determined by the state of the priority control inputs, the state of the current priority inputs and request inputs. Programming is performed in such a way that if the state of the priority control inputs determines a priority higher than the requested priority at the request inputs of the logic matrix 66, then a request signal is not generated at its control output. If the requested priority at the inputs of the request is equal to or higher than the priority at the inputs of the priority control and at the first group of inputs of the logic matrix 66 (higher than the current priority), then the outputs of the logic matrix 66 should generate signals of the internal interrupt vector corresponding to the highest of the requested priorities at the request inputs, and at the control output of the logic matrix 66, a request signal should be generated.

 Register 67 is used to store the request signal, which, together with the signals of the internal interrupt vector by the clock pulse at the synchronization input of the register 67 of the interrupt vector, is written to its outputs and to the control output.

 Priorities can be distributed as follows. The controller’s initialization mode has the highest priority, then its read and write modes when working in software exchange with the computer 21, then the modes of transition to direct access to the computer's memory 21 - these modes are switched after internal interruptions are performed according to the request signals from the controller outputs of the 2 bus . The next priority is the filtering program for received packets by destination addresses. Interrupt requests for this mode come from the second group of outputs of the states of the receiver 12. The next priority request from the outputs of the statuses of the transmitter 13 is to interrupt at the end of the packet transmission. The lowest priority goes to the input of the controller request 9 interrupts when switching to the subroutine of the master timer.

 The control encoder 11 is designed to generate control signals to the controller nodes. Control signals, in particular, can be formed as a sequence of microcommands. Rgeistr 68 microcommands is intended for temporary storage of microcommands and for issuing microcommands from the first group of outputs of the register 68 microcommands to the controller control bus 16 and from its second group of outputs to the control bus 80. The memory of 70 microcommands is intended for storing microcommands and constants. A programmable read-only memory can be used as the memory 70 of the microcommands. The constants are read from the second group of memory outputs of 70 microcommands. The sequence of sampling microcommands from the memory 70 microcommands is provided by supplying to its inputs addresses of the address signals generated by the driver 73 of the address of the microcommand, the decoder-transformer 72 of the starting address, and the controller 9 interrupts. The multiplexer 71 is intended for switching address signals from the outputs of the micro-command address generator 73, the initial address decoder-transformer 72, and the interrupt controller 9 to the memory address inputs of 70 micro-commands. The decoder-converter 72 of the initial address converts the control signals from the outputs of the storage device 7 into the memory addresses 70 of the microcommands. The generator 75 synchronizes the operation of the control encoder 11. According to his pulses, the microcommands are changed in the register of 68 microcommands, the driver of the microcommand address 73, the counter-timer 77, the interrupt controller 9 and the register device 8 are synchronized. The multiplexer 69 allows you to switch constant signals from the second group of memory outputs 70 microcommands and signals of the time intervals from the outputs counter-timer 77 to the first group of inputs of the register device 8. The multiplexer 76 provides the signals at its control inputs for switching the input transfer signal or output ode transfer of the storage device 7, or from the control bus 80 to the transfer input of the storage device 7. The conditions multiplexer 74 switches from its inputs to the conditions input of the micro-command address generator 73 condition signals. Counter-timer 77 is designed to synchronize the operation of software timers of the controller according to the signals from its outputs. The decoder 78 upon reaching the outputs of the counter-timer 77 a certain value of the signals at its output generates a signal, overturning the RS-trigger 79. The RS-trigger 79 generates an interrupt request signal from the controller 9 interrupts when switching to the subroutine timer.

 The microcommand address generator 73 generates the microcommand addresses that are received at its outputs either from the outputs of the register 84, or from the outputs of the stack 86, or from the control bus 80 through its address inputs. The adder 85 in the presence of a unit signal increment input increases the address of the microcommand by one, which makes it possible to form a sequence of addresses. Stack 86 upon transition to the subroutine provides loading the address of the microcommand from register 84 into stack 86 with its subsequent unloading to the outputs of stack 86 when exiting the subroutine. The decoder 89 is designed to set the operating modes of the shaper 73 of the micro command address according to the signals at the inputs of the instructions of the decoder 89. In accordance with the signal at the input of conditions at its outputs, control signals of the nodes of the shaper 73 of the micro command instruction are generated. The nodes of the shaper 73 of the micro command are synchronized by the pulses received through its synchronization input from the generator 75. These pulses are used to increase or subtract the contents of the reverse counter-pointer 87 of the stack, write to stack 86, write to register 84. Register 84 is used for temporary storage addresses of microcommands, which are written to the register 84 from the outputs of the adder 85 according to the clock pulses supplied to the synchronization input of the register 84. The reversible counter-pointer 87 of the stack generates address signals in odes address stack 86, necessary to select memory cells in the stack 86. A multiplexer 88 is used for switching signal outputs from the stack 86, outputs from the register 84 to the address generator 73 inputs the address of the microinstruction on the output of the microinstruction address.

 The bus controller 2 provides control of the data exchange process between the computer 21 and the controller. In the modes of program exchange, direct access to memory and in the interrupt mode, the signals at the control inputs of the controller 2 of the bus specify the modes of its operation. The bus controller 2 provides control of the interface 1, receiver 12, transmitter 13, address selector 10 by signals supplied from the control outputs of the bus controller 2. The controller 2 of the bus when exchanging data with the computer 21 exchanges control signals with the computer 21 via the system bus 19 control.

 The decoder 59 is designed to generate signals that control the process of data exchange between the computer 21 and the controller. The timer device 60 generates signals that allow the decoder 59 to withstand the time relationships required on the computer system bus 21 when generating the signals controlling the data exchange process. Amplifiers 58 are designed to coordinate the circuit of the controller control bus 19 with the controller circuit of the bus 2.

 Interface 1 is designed to interface the data bus 17 and the controller address bus 18 with its internal circuits. The interface 1 under the control of signals from the control outputs of the bus controller 2 performs data exchange between the data bus 17 and the controller nodes. Interface 1 sends the address signals in the program exchange mode from the address bus 18 to the address inputs of the address selector 10 and to the first group of inputs of the multiplexer 14 or sends address signals from the bit outputs of the address counter 3 to the controller address bus 18 in the direct memory access mode.

 Amplifiers 54 and 55 are bidirectional and are designed to coordinate the internal circuits of the controller with its data bus 17 and address bus 18. Amplifiers 54 switch the address signals from the bit outputs of the address counter 3 to the address bus 18 or address bus 18 to the first group of inputs of the multiplexer 14. The amplifiers 55 switch the data signals between the controller data bus 17 and the outputs of the register 56, as well as the second group of inputs of the multiplexer 14 and the inputs transmitter 13. Register 56 is intended for temporary storage of data sent from the controller to the data bus 17. The switch 57 is intended for switching data to the inputs of the register 56 from the internal bus 15 of the controller or from the outputs of the receiver 12.

 The register device 8 is designed to store data loaded into its registers 63 from the outputs of the memory device 7 from the internal bus 15, as well as to store the constants loaded from the second group of memory 70 microcommands through the multiplexer 69, and to store control signals downloaded from the third group of outputs memory microcommands. The register device 8 generates signals from the registers 63 to the inputs of the address of the RAM 6, to the internal bus 15 of the controller, to the second group of address inputs and to the control input of the memory device 7. Registers 63 are memory with a stack organization and are used to store data written to the registers 63 under the control of signals from the control inputs of the register device 8 by sync pulses from the synchronization input of the register device 8. The stacked organization of memory allows to reduce the transition time to subprograms. The reversible counter 65 serves as a pointer to the stack, and its output signals supplied to the inputs of the addresses of the registers 63 allow the selection of the memory cells of the registers 63. The reversible counter 65 under the control of the signals from the inputs of the control of the register device 8 allows you to increase or decrease the addresses of the memory cells of the registers 63 when applying to the synchronization input of the reverse counter 65 clock pulses from the output of the generator 75. The multiplexer 62 is used to switch input, and the multiplexer 61 is used to switch the output signals of the register 63 by signals from the register device control inputs 8. The bidirectional amplifiers 64 are used to switch signals between input-output register unit 8, the output of register 63 switched through multiplexer 61, register 63 or input, switched through a multiplexer 62.

 Random access memory 6 is used to store state and control words in its cells, which the computer 21 and the controller exchange in program exchange mode and direct memory access mode. The interrupt vector is also stored there. In addition, RAM is used to store data necessary for the operation of the controller.

 The multiplexer 14 is used for switching data to the internal bus 15 of the controller coming from the data bus 17 through the interface 1 to the second group of inputs of the multiplexer 14, or switching the address signals coming from the address bus 18 through the interface 1 to the first group of inputs of the multiplexer 14.

 The address counter 3 is used to generate address signals that, in direct access mode, are sent via the interface 1 to the address bus 18 for addressing to the computer memory 21. The address counter 3 provides parallel loading of the initial address from the controller internal bus 15 and further counting of the pulse addresses from the controller outputs 2 tires.

 Register 4 addresses serves to store the final address of the memory zone of the computer 21, loaded into it from the internal bus 15.

 The comparison circuit 5 is designed to generate a comparison signal at its output when the contents of the address counter 3 and the address register 4 are equal, which allows you to determine the moment when, when reading or writing in direct access to memory, access is made to all memory cells of the computer 21, starting from the initial the address loaded by the data inputs into the counter 3 addresses, and ending with the final address loaded into the register 4 addresses.

 The address selector 10 is designed to select the addresses of the bus 18 of the controller address, with which the computer 21 accesses the controller in program exchange mode. At the same time, from the control outputs of the bus controller 2 in the program exchange mode, if there are address signals on the address bus 18, control signals of the address selector 10 receive selection enable signals. When recognizing the address of the address selector 10, at its outputs it generates internal interrupt request signals arriving at the fourth group of request inputs of the interrupt controller 9. The address selector 10 is designed to generate interrupt request signals for reading or writing data in a program exchange mode, depending on whether the computer 21 writes to the controller or reading data.

 The receiver 12 is intended for receiving from the controller input a serial data stream represented by the Manchester-11 code, decoding the received data into a code without returning to zero, converting the received data into a parallel sixteen-bit code of data words. The receiver 12 buffers the received data in fifo 90 reception and through its outputs in direct access mode transmits data words via interface 1 to the controller data bus 17. It supports the direct memory access mode, generating control signals of the bus controller 2 in the direct access mode at its control outputs, and controls the control errors in the received signal and the presence of transmissions in the communication cable (carrier control). The receiver 21 distinguishes the preamble delimiter in the received code, followed by the packet data, and generates an internal interrupt request signal for filtering the destination addresses of the received packets by the number of received data at its state outputs, and also generates status bits that determine the quality of the received packet and its correct length in bits and words.

 Decoder 96 is designed to convert the Manchester-11 code into a data code without returning to zero at the output of decoder 96, followed by clock pulses at its synchronization output. Shift register 92 is used to convert a serial data code without returning to zero into a parallel code of sixteen-bit data words. Fifo 90 reception is intended for temporary buffering of received data, which allows matching the data exchange rates on the communication channel 24 and on the controller data bus 17. It is designed to store end-of-frame labels that mark the last word of a received packet. The flag detector 93 determines the moment of reception of the preamble limiter in the received packet and generates a signal that overturns the RS flip-flop 94 at the S-input, and from that moment, data reception from the communication channel 24 begins. The RS flip-flop 94 generates a reset signal of a counter of 98 bits at its output. The input signal detector 97 is intended for generating a carrier signal at its output in the presence of transmissions in the communication channel 24. Loopback logic 95 is designed to detect errors in received packets. Error control is performed based on a polynomial of degree 16. If there are errors in the packet, an error signal is generated at the control output of the cyclic control logic. The counter 98 bits allows you to count the received bits of data by the clock on its input counter and, thus, determine the multiplicity of the received data by eight to identify the byte boundaries of the received packets. The irreversibility of the number eight determines the reception error. According to the counter 98 bits, the control logic 100 generates clock pulses for supplying them to the counting input of the counter 99 to count the number of received bytes in the packet. A 99 byte counter is used to count the number of bytes received in a packet. The control logic 100 is designed to control the operation of the nodes of the receiver 12 and generates at its outputs signals of interrupt requests for filtering packets at destination addresses that are issued to the outputs of the receiver states. The control logic 100 generates at the outputs of the receiver 12 signals of the reception states, which are fed to the third group of inputs of the condition multiplexer 74, and generates at its outputs connected to the control outputs of the receiver 12 signals that control the operation of the bus controller 2 in the direct memory access mode. The multiplexer 91 is designed for switching to the internal bus 15 of the data controller from the outputs of the FIFO 90 reception or status bits from the bus 106, from the outputs of the counter 98 bits, from the output of the detector 97 of the input signal and from the output of the logic 95 of cyclic control.

 The transmitter 13 is designed to exchange the transmitted data with the computer 21 and the internal bus 15 of the controller, as well as for pre-buffering the transmitted data in FIFO 107 transmission and for subsequent conversion of data into Manchester-11 code and transmitting it to the communication channel 24. The transmitter 13 before transmitting the data packet transmits the preamble to the communication channel 24, ending it with a preamble limiter, and ends the transmission of the packet with the checksum generated by the cyclic control logic 109. Fifo 107 transmission is intended for temporary storage of transmitted data packets. The shift register 108 is designed to convert the transmitted data into a serial code without returning to zero. Logic 109 logic control is designed to generate a checksum when dividing the transmitted data by a polynomial of degree 16. The logic of cyclic control is similar to that available in the prototype. The switch 110 is designed for switching to the input of the encoder 111 data from the output of the shift register 108 or the checksum from the output of the logic 109 cyclic control transmitted after the transmission of the last bit of data. Amplifiers 114 are designed to match the bus 116 and the internal bus 15 of the controller when transmitting status bits from the outputs of the control logic 113 to the internal bus 15. The control logic 113 is used to control the operation of the nodes of the transmitter 13. It generates and sends tag signals to the input of the tag Fifo 107, which marks the last word of the transmitted packet when recording it in fifo 107 transmission. The control logic 113 generates control signals at the control inputs of the transmission FIFO 107, by which the data words are written from the inputs of the transmitter 13 to the transmission FIFO 107 or the read data words are transmitted to the outputs of the transmission FIFO 107.

 When the packet is transmitted, the control logic 113 generates a word recording signal at the write input of the shift register 108 according to the outputs of the counter 112 bits, when all the bits of the previous word are shifted by the register 108, and generates control signals at the control inputs of the loop control logic 109, according to which the loop control logic generates checksum for the transmitted packet or provides a checksum to its output bit by bit, synchronizing the presence of each of the bits of the checksum at the output with clock pulses from the outputs of the generator 115. The control logic 113 generates control signals at the control input of the switch 110, through which the signals are switched either from the output of the shift register 108, or from the output of the logic 109 of the cyclic control to the input of the encoder 111. It generates a reset signal of the counter 112 bits, which allows the latter to the absence of a reset signal to count the clock pulses from the output of the generator 115. This is necessary for generating control logic 113 from the outputs of the counter 112 bits of control signals for sequential reading of the layer in from FIFO 107 and transfer them to the shift register 108. The control logic 113 generates an internal interrupt vector at the state outputs at the end of the packet transfer to request internal interrupts for the second group of interrupt request inputs of the interrupt controller 9. It generates a control signal at the control inputs of amplifiers 114, through which the words of transmission states are sent through amplifiers 114 from the outputs of transmission states to the internal bus 15 of the controller. The control signal at the control inputs of the amplifiers 114 is formed upon request of the status word of the transmitter 13 by its second group of control inputs from the control encoder 11. The control logic 113 generates at the control inputs FIFO 107 the transmission of the control signal for writing data words in the presence of the control outputs of the controller 2 bus control signals write to the first group of control inputs of the transmitter 13. In this case, the data words from the inputs of the transmitter 13 are recorded in fifo 107 transmission. The control logic 113 in synchronous mode according to the control signals from the control outputs of the bus controller 2 generated in the recording mode of direct access to the memory of the computer 21 generates synchronization signals at the control outputs of the transmitter 13 that support the exchange between the computer 21 and the transmitter 13. The control logic 113 stops the exchange data from the computer 21, removing the busy signal from the control outputs of the transmitter 13 in the presence of a comparison signal at the transmitter input from the output of "Equal to" comparison circuit 5. It communicates with the internal bus 15 of the controller through the fifth group of its inputs. This allows you to reduce the number of control inputs on the second group of control inputs of the transmitter 13 due to the fact that the control signals of the transmitter are supplied simultaneously on the internal bus 15 of the controller and on the second group of control inputs of the transmitter 13. The counter 112 bits serves to count the number of bits of received data. Encoder 111 is designed to convert a serial data code and a checksum code into a Manchester-11 code.

 The coincidence circuit 126 generates an inverse code at its output with returning the transmitted data to zero. The inverter 125 and the coincidence circuit 127 generate an inverse code at their output with the inverted transmitted data returning to zero. JK trigger 128 generates a Manchester-11 code on its output. JK-trigger 129 is a frequency divider and generates pulses at its output that are supplied to the second inputs 126 and 127 matches.

The delay line 130 of the decoder 96 serves to phase delay the received Manchester-11 code. EXCLUSIVE OR 131, 132, inverter 133, and D-flip-flop 134 circuits are used to isolate the clock frequency from the received Manchester-11 code. D-flip-flop 135 is used to generate a data code from the received signal without returning to zero. The EXCLUSIVE OR circuit 137, the coincidence circuit 138, the shift register 139, the EXCLUSIVE OR circuit 140, the shift register 141, the EXCLUSIVE OR circuit 142, the shift register 143 are used to calculate the checksum when dividing the input data code by the generatrix polynomial x ¹⁵ + x ¹² + x ⁵ +1.

 A multiplexer 144 is used for switching output data of input data supplied to its first input, or a checksum code supplied to its second input. This allows the transmission of the checksum code after the transmission of the data packet. The decoder 145 on the signals at its inputs generates at its output the control signal of the error of the checksum in the presence of errors in the input logic of the cyclic data control.

 Random access memory 146 serves for temporary storage of received or transmitted data, which allows you to coordinate the exchange rate in the communication channel 24 and on the controller data bus 17. Random access memory 147 serves to store mark signals that mark the words of received or transmitted data. The multiplexer 148 switches the address signals from the outputs of the counters 149 and 150 to the inputs of the address of the RAM 146 and RAM 147. The counter 149 is used to generate the address when writing data words to the RAM 146. The counter 150 is used to generate the address when reading the data words from the RAM 147.

 The controller works as follows.

 Before you start the computer 21 initializes the controller. Its initialization is carried out either when the initialization signal is supplied via the control system bus 19 from the side of the computer 21, or by software initialization. In initialization mode, the controller writes into the RAM 6 words of the initial states of the state and control words. The transition to the initialization subroutine is carried out when requesting interruptions on the third group of inputs of interrupt requests of the controller 9 interrupts. These requests come from the outputs of the bus controller 2 if there is an initialization signal from the computer 21 at its inputs and outputs.

 The transition to the initialization subroutine can be made by writing the first state word from the computer 21 to the controller in program exchange mode. In the process, the controller communicates with the computer 21 in the program exchange mode and in the direct access mode to the memory of the computer 21. In the program exchange mode, the controller and the computer 21 exchange state words and control words. In the direct access to the memory of the computer 21, the controller exchanges with the computer 21 received from the communication channel 24 or transmitted to the communication channel 24 packets, as well as control data. State and control words are stored in random access memory 7. Data exchange in the direct access mode to the computer 21 memory can be carried out in groups of words without returning the system bus to the computer 21.

 Data exchange in the modes of program exchange and direct access to memory is carried out by controlling the nodes of the controller microcommands, which are selected from the memory of 70 microcommands during the execution of the corresponding routines described below. The transition to any control subroutine is possible when generating the vector of internal interrupts at the outputs of the controller 9 interrupts, as well as when generating the code of the starting address of the control subroutine at the outputs of the storage device 7, as well as the branch addresses supplied from the second group of outputs of the register 68 microinstructions to the inputs addresses of the driver 73 addresses of the micro-command. According to the internal interrupt vectors, transitions are made to the control subroutines for servicing internal interrupts, which include subprograms listed below in descending order of priority: controller initialization subroutine, read and write subroutines during program data exchange between computer 21 and the controller, direct memory access subroutine , a routine for filtering received packets by destination addresses, a timer routine.

 The initial address code of the control routines is generated at the outputs of the storage device 7 as a result of non-standard logical operations on the control words and states. The code of the starting address of the control routines is converted at the outputs of the decoder-converter 72 of the starting address to a memory address of 70 microcommands.

 The exchange of data, which is information packets, control words and status words, is performed between the controller, the computer 21, the receiver 12 and the transmitter 13. The receiver 12 receives data packets from the communication channel 24. The transmitter 13 transmits data packets to the communication channel 24. In the program exchange mode, the computer 21 accesses the controller at several addresses of the address bus 18 to perform read or write cycles.

 The transmission of packets (Fig. 16) begins with the transmission of the preamble - an alternating sequence of ones and zeros, ending with two units - the preamble limiter. The preamble is necessary to synchronize the receivers 12 of all devices connected to the communication channel 24. The preamble limiter separates the preamble from the number field of the device transmitting the transmission (LLP field), in which a unique device number is transmitted in the local area network. This number determines the order in which packets are transmitted by devices. The control field indicates the type of packet being transmitted. A set bit 15 or bit 14 indicates that a monitor device packet is being transmitted. The set bit 13 indicates that a token packet is being transmitted.

 The monitor device provides the right to transmit packets to the communication channel 24 devices. A monitor package may contain arbitrary data. The packet of the upper levels of the local area network has zero bits 15, 14, and 13 set to zero in the control field.

 The destination address field indicates the 48-bit destination address of the packet. The destination address can be individual (the first bit of the address is set to zero), multicast (the first bit of the address is set to one) or broadcast (all bits of the address are set to one). The source address field indicates the address of the device - the sender of the packet. The data field contains the packet data. The checksum for the data contained in the fields transmitted after the preamble limiter is transferred to the amount control field.

 The set bit 15 in the control field means that the transmitted packet is a marker packet. The set bit 14 in the control field means that the station transmitting the packet is preparing to become a monitor station. The set bit 13 in the control field means that the packet of the monitor station is being transmitted.

 In computer memory 21, for communication with the controller in direct access mode, zones are allocated for storing data to be transmitted to communication channel 24 — transmission buffers and memory zones where received information should be recorded, reception buffers, and also memory zones allocated under descriptors of receive buffers and descriptors of transmit buffers. Each of the descriptors represents a memory zone of the computer 21 from several cells (Fig. 17). Descriptors in computer memory 21 are located in adjacent memory zones, that is, they follow one after another, forming groups of descriptors of eight descriptors in a group (chain of descriptors). For each of the receive buffers, a receive buffer descriptor is intended. For each of the transfer buffers, a descriptor for the transfer buffer is provided. The descriptor flag is stored in the first descriptor cell. Significant bits of the flag are bits 15 and 14. They are designed to acknowledge the established connections between the computer 21 and the controller. The bits are initialized by the computer software 21 and upgraded by the controller. If bits 15 and 14 are set to zero (00), then the buffer is used by the software. If bit 15 and bit 14 are set to "1" and "0", then the controller has not yet used the buffer described by the descriptor. If the value of bit 15 and bit 14 is "1" and "1", then the controller uses a buffer.

 In the second cell of the buffer descriptor, the high bits of the start address of the buffer described by the descriptor (bits 00-05), and status bytes (bits 08-15) are stored. The third word of the descriptor contains the least significant bits of the buffer start address (bits 00-15). The total length of the start address of the buffer is twenty-two bits.

 The status of bits 15 and 14 of the status byte “0” and “0” indicates that the bits of the buffer start address are not significant. The status of bits 15 and 14 "1" and "0" indicates that the bits of the buffer start address are significant. The state of bits 15 and 14 "1" and "1" indicates that the start address bits are the start address of the buffer descriptor, which is necessary for switching from one group of descriptors to another. The set bit 13 of the status byte indicates that the buffer described by the descriptor contains the last packet segment. The set bit 12 of the status byte indicates that the buffer described by the descriptor contains control data or, in other words, is an installation package. The remaining bits of the third cell are reserved.

 The fourth cell of the descriptor stores the word of the length of the buffer described by the descriptor. Using the word buffer length and the start address of the buffer, you can calculate the address of the last buffer cell. The fifth descriptor cell contains the first word of the buffer states. The sixth descriptor cell contains the second buffer state word. The sixth cell of the buffer descriptor, if it is not the last in the descriptor group, is followed by the flag of the next descriptor.

 The meaning of the bits of the first word of the state of the buffer descriptor is as follows: bits 15 and 14, set to state "1" and "0", inform that this buffer was not used by the controller. The status of these bits "1" and "1" means that the buffer was used by the controller, but is not the last segment of the packet. The status of these bits "0" and "0" means that the buffer contains the last segment of the packet, received or transmitted with errors.

 For the descriptor of the transmission buffer, the status of bits 15 and 14 “0” and “0” in the first word of the transmission status means a transmission error due to the absence of a signal detected by the input signal detector 97 in the communication channel 24 when the packet was transmitted by the transmitter 13, or because there is no confirmation of the received packet from the network device to which the packet was intended. At the same time, with bits 15 and 14 equal to "0" and "0", bits 12, 09, 03 can be set. The set bit 12 determines the absence of a signal in the communication channel 24 during transmission. The set bit 09 indicates that the received packet did not receive an acknowledgment. Bits 08, 07, 06, 05 contain a counter of the number of attempts to transmit a packet to which there was no acknowledgment of receipt. The set bit 03 indicates that the largest number of transmissions of the same packet has been made without acknowledgment of the receipt of this packet. The bits in the second word of the states of the descriptor of the transmission buffer carry information about the time interval between the start of transmission of the packet and the receipt of confirmation of its receipt.

 For the receive buffer descriptor in the first word of the status, the value of bits 15 and 14 “0” and “0” means a reception error due to the receipt of an invalid packet length (for example, the length is more than 1500 bytes) or due to the reception of a packet with a cyclic control error, or because receive a very short packet (for example, less than 64 bytes), or because of a packet reception, the number of bits in which is not a multiple of eight. When bits 15 and 14 are reset to “0” and “0”, bits 11, 02, 01, 00 are set. The set bit 11 means that a short packet of less than 64 bytes in length has been received. The set bit 02 indicates that the length of the received packet has a number of bits not a multiple of eight. A set bit 01 indicates a cyclic check error. The set bit 00 indicates that the packet is unacceptably long. Bits 10, 09, 08, 07, 06 indicate the packet number in the message.

The second state word of the receive buffer descriptor contains information about the number of bytes in the received packet. The installation package is described by the descriptor of the transmission buffer, in which bit 12 is set to state "1". The installation package contains a table of destination addresses of packets that the controller must receive from the communication channel 24 to its receive buffer and transport it to the computer memory 21 in direct access mode
An installation package can contain up to fourteen six-byte destination addresses for packages, one of which is a broadcast address, the other is an individual address, and the remaining twelve addresses can be group or individual. The broadcast address is intended for all network stations connected to the communication channel 24, and contains units in all its forty-eight bits. An individual address starts with a bit set to zero - only one controller accepts a packet with an individual address. The multicast address has the first bit set to one and serves to address a group of controllers. Group and individual addresses can be programmatically changed by the computer 21. The location of the destination addresses in the buffer of the installation package in the memory of the computer 21 can be, for example, the following: in the buffer, all fourteen destination addresses occupy three words (six bytes) and form a continuous zone of 42 the words.

 The installation package may contain not twelve, but a smaller number of group destination addresses of the packages. The installation package contains in the last two words (in the word number and in the word number of the controller) information about the number (NG) of controllers connected to the communication channel 24, and about the number (NU) of the controller in the communication channel 24. The length of the installation package is described by the fourth word of the installation package descriptor, which indicates the length of the buffer.

 The controller communicates with the computer 21 descriptor buffers, installation packages in direct access to memory mode. To store descriptors and installation packages in RAM 6 memory cells are allocated.

 In RAM 6, the words of states and control are stored, which the computer 21 and the controller exchange in program exchange mode at fourteen addresses of the address bus 18. To these addresses (port register addresses) of bus 18, addresses must be mapped to fourteen addresses of RAM 6 through which the program exchange is performed and which contain the following words: only readable six words of the physical destination address, the lower bytes of which contain six bytes of the physical destination address , and the two high bytes of the last two words contain the control code of the physical destination address; only four words that can be written are the start addresses of the receive buffer descriptors (two words) and the transmit buffer descriptors (two words); interrupt vector word; first word of state and control.

 The physical destination address is an individual destination address stored in the memory of 70 microcommands, from where it is read when the controller is initialized through the second group of outputs of the control encoder 11, through the register device 8 into the main memory 6. Similarly, the physical control code 6 is written into the main memory 6 the destination address, which was calculated and stored in the memory of 70 microcommands during its initial programming.

 The computer 21 in program exchange mode reads the words of the physical destination address and the control code of the physical destination address from the controller and can reassign or record the physical destination address in the installation package as an individual destination address.

 In the program exchange mode, the computer 21 writes into RAM 6 the word of the least significant bits and the word of the most significant bits of the start address of the transmit buffer descriptor, the word of the least significant bits and the word of the highest bits of the start address of the receive buffer descriptor, as well as the external interrupt vector and the first state and control word. The interrupt vector recorded from the computer 21 to the controller is necessary to perform external interrupt mode.

 The bits of the first word of state and control have the following meaning. Bit 15 - the interrupt request bit of the computer 21 is set by the controller after receiving the packet from the communication channel 24 to receive and transport it to computer 21 and upgrading bits 15 and 14 in the first word of the states of the last buffer descriptor, which contains the last message segment. The interrupt service program executed by the computer 21 should clear this bit. Bit 15 is cleared when the controller initializes.

 Bit 14 — The interrupt request bit is set by the controller if the list of receive descriptors has been exhausted. The interrupt service program and the controller initialization signal reset this bit.

 Bit 13 is set by the controller when reading from the side of the computer 21 the state and control word if the communication channel 24 contains a signal of transmitted packets (carrier signal) detected by the input signal detector 97.

 Bit 12 is reserve, bit 11 is reserve, bit 10 is reserve.

 Bit 09 is set from the side of the computer 21, if the controller is put into loopback mode. In this case, the controller transports from computer 21 to FIFO 107 transmissions, transmits to communication channel 24, receives from communication channel 24 to FIFO 90 reception, transports packets transmitted by it to computer 21.

 Bit 07 is set by the controller when requesting interruptions to the program executed by the computer 21, when the transmitter 13 transmitted the message to the communication channel 24 and upgraded bits 15 and 14 in the first word of the status of the transmission buffer descriptor. The software and initialization signal resets this bit.

 Bit 06 is set by software when the controller is allowed to generate a computer interrupt signal 21. This bit is cleared by a reset signal and software.

 Bit 05 is set by the controller when requesting interruptions to the computer software 21 if the list of receive buffer descriptors is exhausted.

 Bit 05 is set in the initialization mode and when bit 02 is set. Bit 05 is reset by the controller after loading the least significant words and the most significant bits of the receive buffer descriptor into it.

 Bit 04 - reserve, bit 03 - reserve.

 Bit 02 is set by the controller when generating a request signal to interrupt the computer 21, if the computer 21 in the direct memory access mode during the timeout of the timer device 60 did not respond with a ready signal confirming the reading or writing of the word.

 Bit 01 is set by the computer 21 if the software initializes the controller.

 Bit 00 is set by the computer and allows the reception of packets from the communication channel 24.

 In RAM 6, the second state and control word is stored, which is not available for computer 21. The set bit 00 of this word means that the start address of the transfer buffer descriptor has been loaded into the controller. The set bit 01 means that the start address of the receive buffer descriptor has been loaded into the controller. Setting bit 02 means that the transfer is made in the mode of direct access to memory from the computer 21 to the controller of the words of the descriptor of the transmission buffer. Setting 04 means that the transfer is made from the computer 21 to the controller of the words of the descriptor of the receive buffer. Setting bit 05 means that the transfer buffer descriptor is being transferred from the controller to the computer 21. Setting bit 06 means that the receiving buffer descriptor is being transferred from the controller to the computer 21. Setting bit 08 means that the contents of the transmission buffer are being transferred from the computer 21 to the controller . Setting bit 09 means that the contents of the receive buffer are transferred from the control to the computer 21. Setting bit 10 means that it is waiting for direct access to the memory of computer 21. Setting bit 12 indicates that the installation packet is being sent from computer 21.

 The modes of operation of the controller 2 of the bus are set by the signals at its control inputs. If a program exchange mode signal is supplied to the third group of its control inputs, then it gives control signals to the control outputs, through which address signals from address bus 18 are transmitted via interface 1 to the address inputs of address selector 10. Upon receipt of read or write signals accompanying the address signals on the address bus 18 to the control system bus 19, a signal is generated at the control outputs of the decoder 59, which allows the address selector 10 of the decoder to address if the addressing in the program exchange mode is made to the controller, the outputs of the address selector 10 generate interrupt request signals for reading in read mode or for writing in write mode.

 When the controller completes the read or write mode, a ready signal is supplied to the third group of control inputs of the bus controller 2, by which the decoder 59 generates a "Ready" signal, and this signal is fed to the system control bus 19, which completes the read and write cycles. If the third group of control inputs of the bus controller 2 or the first group of its control inputs, or the second group of its control inputs are read or write in direct access to the computer memory, then the decoder 59 generates a direct access request signal on the second group of outputs , which is fed through amplifiers 58 to the system bus 19 controls.

 When a direct access confirmation signal appears on the system bus 19 from the computer 21, the decoder 59 generates busy signals on the second group of outputs. These signals are issued to the control system bus 19 as confirmation signals of the capture of the computer system bus by the controller 21. On the third group of outputs of the decoder 59, request signals of internal interrupts for confirming the direct access mode are generated. On the second group of outputs of the decoder 59, control signals are generated, according to which address signals from the bit outputs of the address counter 3 are issued via interface 1 to the controller address bus 18. If the recording mode is set for this with direct access to the memory, then according to the control signals from the second group of control outputs of the decoder 59, the data signals from the outputs of the register 56 through the amplifiers 55 of the data bus are read onto the controller data bus 17. On the fourth group of outputs of the decoder 59, the trigger signals of the timer device 60 are generated, according to which the timer device starts counting the time interval, after which signals from the outputs of the third group of inputs of the decoder 59 are received. According to them, on the first group of outputs of the decoder 59, a “Read” signal or a “Write” signal is formed depending on the selected direct access mode.

 When the external interrupt mode is set on the second group of inputs of the decoder 59, the decoder 59 generates an interrupt request signal on the second group of its outputs. When an interrupt confirmation signal appears on the system bus 19 from the computer 21 side, the decoder 59 generates a Capture signal on the second group of its outputs, and generates control signals on the third group of its outputs, according to which the interrupt vector is read from the register 56 to the controller data bus 17. A signal is generated on the fourth group of outputs of the decoder 59, by which the timer device 60 is started. After a period of time sufficient to set the signals of the interrupt vector on the data bus 17, a signal “Record” is generated from the outputs from the timer device on the second group of outputs of the decoder 59 supplied to the control system bus 19. When received from the control bus 19 to the first group of inputs of the decoder 59 from the computer 21, the signal "Ready" stops the output of the vector on the data bus 17 and ends the external interrupt mode by removing the signal from the system bus 19 control signal "Capture".

 The transmitter 13 buffers the transmitted packet in fifo 107 transmission. Data in FIFO 107 transfer is recorded from the internal bus 15 of the controller via interface 1 under the control of signals on its second group of control inputs. Thus, for example, a preamble of a packet may be recorded. Data in fifo 107 transmission can be recorded from the controller data bus 17 through the interface 1 under the control of signals on the first group of its control inputs. Data in FIFO 107 is accompanied by labels at its label inputs.

 When recording in Fifo 107 data transfer or preamble words from the internal bus 15, each data word is accompanied by a second group of transmitter control inputs 13 by data recording control signals and mark signals. Labels make it possible to mark the words of the preamble, which are not subject to division into a generator polynomial on the logic 109 of cyclic control, in contrast to data words.

 After loading in FIFO 107 the transmission of the last data word to the third group of inputs of the control logic 113, a signal is written to mark the end of the packet. In this case, the label of the end of the packet is supplied to the inputs of the labels of the FIFO 107 from the outputs of the control logic 113, and the write signal is transmitted to the inputs of the control of the FIFO 107, according to which the label of the end of the packet is transferred to the FIFO 107 of the transfer.

 According to the signals of the start of transmission on the third group of inputs of the control logic 113, the transmitter 13 starts transmitting the packet. In this case, the synchronizing pulses from the generator 115 are supplied to the control logic 113, to the counting input of the counter 112 bits, according to the output signals of which and by the signals of the tags from the outputs of the tags FIFO 107 transfer control logic 113 controls the data transfer process. In this case, read signals are transmitted to the control inputs of the FIFO 107 transmission, through which the words of the preamble and data words are read from the memory cells to the outputs of the FIFO 107 and transferred to the shift register 108 and through the switch 110, through the encoder 111 they are transmitted in a serial bit stream through the output of the transmitter 13 to the communication channel 24. According to the labels of the data words read from the outputs of the labels of the transfer fifo 107, the control logic 113 generates enable signals for calculating the checksum, which are fed to the control inputs of the cyclic control logic, on which the checksum is calculated for the data received at the input of the cyclic control logic.

 The signals of the packet end mark and the signals from the outputs of the counter 112 bits stop the data transfer and through the switch 110, the checksum is transmitted from the output of the cyclic control logic. At the end of the transmission of the packet from the outputs of the status of the transmitter 13, a signal of internal interruptions of the end of the transmission of the packet to the communication channel 24 is issued.

 The receiver 12 buffers the data received from the communication channel 24 in fifo 90 reception. From Fifo reception data words are read either on the internal bus 15 of the controller, or on its data bus 17.

 The receiver 12 starts receiving after receipt of a reception permission signal from the outputs of the control encoder 11 upon the second group of its control inputs. From the outputs of the control logic 100 in this case, a reset signal of the RS flip-flop 94 is supplied to its R-input. The received data signal is decoded by decoder 96, at the output of which a code is generated without returning to zero, followed by clock pulses from the synchronization output of decoder 96.

 The data is shifted by the shift register 92, and if the outputs of the register 92 of the parallel code of the preamble limiter, the flag detector 93 generates a signal at its output that sets the RS-flip-flop 94 at the S-input, thereby removing the reset signal from the reset input of the 98-bit counter. The counter 98 bits starts counting clock pulses from the synchronization output of the decoder 96. Based on the value of the output signals of the counter 98 bits, the words of the data from the outputs of the shift register 92 are rewritten to receive FIFO 90 by the recording signals supplied to its control inputs. At the inputs of the labels Fifo 90 receive tags of data words that are recorded in Fifo reception by recording signals.

 According to the signals supplied to the control inputs, the logic 95 of the cyclic control calculates the checksum. Upon completion of receiving the packet by the signal from the output of the detector 97 of the input signal, the control logic 100 generates control signals by which the signals from the output of the control logic 95 of the cyclic control from the outputs of the counter 98 bits are fed to the inputs of the multiplexer 91.

 During the reception of packets, words of data are counted according to the signals at the counter input of the 99 bytes counter. When all words of the destination address of the packet are recorded in FIFO 90, the signal from the outputs of the counter 99 bytes at the outputs of the status of the receiver 12 generates an internal interrupt signal to filter the destination address. According to the read signal of the data supplied to the second group of control inputs of the receiver 12, the control logic 100 provides read signals to the control inputs of the FIFO 90, and the words of the destination address of the packet from the outputs of the FIFO 90 of the receive through the multiplexer 91 are read to the internal bus 15 of the controller.

 If the destination address of the packet does not differ by the controller as intended for it, then a packet reset signal is sent to the second group of control inputs of the receiver 12, through which a reset signal is also sent to the control inputs of the FIFO 90, the counters 149 and 150 are reset, and the FIFO 90 is set to the original state. The words of the packet with the destination address, recognized by the controller as its own, are sent in the direct access mode to the computer memory from the fifo 90 reception to the controller data bus 17.

 The receiver 12 enters the direct memory access support mode when a direct access mode initialization signal is supplied to its second group of control inputs. At the same time, from the outputs of the control logic 100, the control outputs of the direct memory access requirement are supplied to the control outputs of the receiver 12. When the direct signal access mode confirmation signal is received at the first group of control inputs of the receiver 12, the control logic 100 outputs the system bus busy signal and the word write signal to the control outputs of the receiver 12. When a ready signal arrives at the first group of control inputs of the receiver 12, if there is no signal on the end of the second group of control inputs of the receiver 12 requiring direct access to the memory generated in the firmware by the timeout of the counter-timer 77, if there is no demand signal at the control input of the receiver 12 the end of direct access to the memory generated by the signal from the output of the comparison circuit 5, and if there are no FIFO marks 90 at the outputs of the reception of the end of packet label signal, the control logic 100 provides the control outputs to nick 12 recording signal word. Otherwise, the control logic 100 removes the bus busy signal from the control outputs of the receiver 12 and this stops the direct access to the computer memory.

 Together with the issuance of the write signal to the control outputs of the receiver 12, a read signal is received to the control inputs of the FIFO 90, and data words are read from the outputs of the FIFO 90 reception, and the words are read from the outputs of the labels. If the label of the end of the packet is read from the outputs of the Fifo 90 reception labels, then, along with the termination of direct memory access to the second group of status outputs of the receiver 12, the control logic 100 generates an internal interrupt signal at the end of the packet transfer. If the second group of control inputs of the receiver 12 have an interrupt reset signal, the internal interrupt request signals are removed from the status outputs of the receiver 12.

 The receiver 12, according to the request signals at the second group of control inputs, through the multiplexer 91 gives state signals from the outputs of the counter 98 bits to the internal bus 15 of the controller, which determines the multiplicity of the received bits by the number eight, gives a signal from the control output of the logic 95 of the cyclic control and from the output of the detector 97 input signal.

 Software exchange of control words and state words through the RAM 6 is as follows. The computer 21 accesses the controller with read or write cycles. At the same time, it sets one of the addresses allocated for addressing port registers on the bus 18 of the controller address. Each of the twelve read or written in the program exchange mode words of states and control words stored in RAM 6 corresponds to a single address (port register address) on the address bus 18.

 On the system bus 19 of the control of the controller, the computer 21 sets the control signals for reading or writing. The bus controller 2, receiving these signals through the inputs / outputs, generates read or write signals at the outputs, and at the control outputs it generates operation enable signals for the address selector 10, and control signals through which signals from the address bus 18 pass through the outputs of the interface 1 address to address inputs of address selector 10. When address recognition, the address selector generates an internal interrupt request signal, which, as well as read and write internal interrupt request signals from the bus controller 2 outputs, interrupt controller 9 generates an internal interrupt vector at its outputs that goes to the third group of multiplexer inputs 71, and the control signal received on line 44 to the first control input of multiplexer 71. According to the control signal at its first control input, multiplexer 71 passes signals from the third ppy its inputs to the inputs 70 microinstruction memory addresses. From the memory of the micro-commands, the first micro-command of the control reading subroutine or recording subroutine is selected in the subroutine exchange mode. According to the synchronizing pulses from the output of the generator 75, the microcommands are copied with the first group of outputs of the memory 70 microcommands to the register 68 of microcommands, and from the second group of outputs of the memory 70 microcommands, the constant signals sent through the multiplexer 69 are transferred to the registers 63 under the control of the signal from the output of the memory 70 of the microcommands.

 Microcommands from the outputs of the register 68 microcommands are received on the control bus 16 of the controller, forcing its nodes connected by the control inputs to the control bus 16 to perform operations prescribed by the microcommands. The sequence of executing control microcommands in a program exchange is as follows.

 According to the first micro-command, the micro-command address of the previous control subroutine is backed up by rewriting it from register 84 to stack 86 and the interrupted subprogram data is backed up in registers 63 by increasing the value of the reverse counter 65 by one. These operations make it possible to return to the interrupted routine at the end of the current routine. According to the same micro-command, on the controller control bus 16, the third group of control inputs of the controller 2 of the bus receives a signal for resetting internal interrupt requests, which removes internal interrupt requests for reading or writing from the third group of inputs of the controller 9 interrupts, and is also installed on the priority control inputs controller 9 interrupt code of current priority, prohibiting the interruption of the current routine. Reservation of program interruptions is possible without using the stacked organization of registers 63. However, in this case, the transition time to the subroutine is increased, since the data from the register device 8 must be backed up in RAM 6.

 According to the second micro-command, according to the signals from the control bus 16, the bus controller 2 generates signals at its control outputs, according to which, as well as signals from the second group of control inputs of the interface 1, signals from the address bus 18 are sent through the outputs of the interface 1 address, through the multiplexer 14 through the internal bus 15 to the first group of address inputs of the storage device 7. To its second group of address inputs and to control inputs through the register device 8 from the second and third groups of outputs of the memory 70 microcommands receives the operation code, according to which The signal is converted from the first group of address inputs of the memory device 7 to the memory address signals 6 generated at the outputs of the memory device 7 and transferred to the first register of the register device 8 according to the third micro-command. The signals from the first register of the register device 8 are fed to the address inputs RAM 6, and the cell is sampled RAM 6.

 Thus, for each of the bus addresses 18, the addresses at which the computer 21 accesses the controller in program exchange mode, the outputs of the memory device 7 are formed by the address of the memory cell 6, in which the corresponding control word or status word is stored. By the same micro-command, an operation code is supplied to the second group of address inputs and control inputs of the memory device 7, according to which the signals from the address bus 18 to the first group of address inputs of the memory device 7 are converted at its state outputs into a code that defines an unconditional transition to one from the branches of a subroutine. This code is supplied to the first group of inputs of the control encoder 11. The decoder-converter 72 of the starting address according to the code from the outputs of the states of the storage device 7 generates the starting address of a new branch of the control subroutine, which, under the control of the signals at the control inputs of the multiplexer 71, enters through the third group of its inputs to the inputs of the memory address 70 of the microcommands to generate the fourth microcommand. According to the fourth micro-command, a subroutine is executed in which a specific word of states and control is processed, which was addressed by the computer 21.

 In the given controller example, the following routines are possible: reading from the controller in the computer 21 one of the words of the physical destination address or reading the word of the interrupt vector. These processes are performed the same way, and therefore form a single reading routine without modifications.

 Reading the status and control word, writing the high-order bits of the start address of the receive buffer descriptor, writing the high-order words of the start bit of the start buffer of the transmit buffer — they all perform differently.

 Writing the word of the least significant bits of the start address of the transmit buffer descriptor, writing the least significant bit of the start address of the start buffer of the receive buffer, writing the word of the interrupt vector form a single control recording routine without modifications.

 When the reading subroutine is executed without modification according to the fourth micro-command, the corresponding memory cell is read from the RAM 6 and its contents are transmitted to the data bus 17 through the interface 1, for which the corresponding control signals are sent to the controller nodes, in particular to the bus controller 2, via the control bus 16, which generates control signals for the outputs 1 for the interface 1 for reading signals from the interface to the data bus 17.

 When recording without modification according to the fourth micro-command, the signals from the data bus 17 go to the inputs of the RAM 6 and are recorded in the corresponding memory cell, the address of which is read from the register device 8.

 When recording words of the most significant bits of the address of the descriptor of the transmission buffer by the fourth micro-command, this word is recorded in RAM 6.

 According to the fifth micro-command, in the first of the registers 63 of the register device 8 from the memory 70 of the micro-commands, a constant is written through the multiplexer 69, which determines the address of the memory cell 6, which stores the second state and control word, not available for computer 21. The second state and control word is read on the first group of address inputs of the storage device 7, the outputs of which form the second word of states and control with the zero bit set, which corresponds to the loading of the high bits of the start address of the desktop RAM transfer buffer ripper 6.

 According to the sixth micro-command, the upgraded second state and control word is recorded in the second of the registers 63 of the register device 8 in order to be rewritten back to the RAM 6 using the same micro-command.

 According to the seventh micro-command from the second group of memory outputs 70 micro-commands, the addresses of the first state and control word are supplied to the inputs of the address of the RAM 6, by which bit 04 is reset on the memory device 7.

 According to the eighth micro-command, the first word of states and control with the bit 04 off from the outputs of the storage device 7 is written back to the RAM 6 at the same address. The reset bit 04 means that the computer 21 has prepared the data for transmission, that it is stored in the transmission buffer, the start address of the descriptor of which is loaded into the controller. In this case, the word of the least significant bits of the start address of the transmit buffer descriptor is loaded first, followed by the word of the highest bits of the transmit buffer descriptor. For the descriptor of the receive buffer, the first low-order word is also loaded into the controller, and then the high-order bit of the start address of the descriptor is then loaded.

 Similarly, the word of the high bits of the start address of the descriptor of the receive buffer is written, with the only difference being that the second bit is set not to zero but the first bit, and bit 05 is reset in the first word of states and control. This means that the computer is prepared buffer for receiving data from the controller.

 When reading the first word of states and control in software exchange via the fifth micro-command, the signals from the inputs of the multiplexer 91 are sent through the inputs and outputs of the receiver 12, through the first group of inputs of the register device 8 to its second of the registers 63. Switching signals with the input of the multiplexer 91 should be such that the carrier signal in the communication channel 24, taken from the output of the input signal detector 97, passes to one of the outputs of the multiplexer 91. In this case, one of the bits (carrier bit) in the second of the registers 63 register device 8 after execution of the fourth microcommand is installed if in the communication channel 24 there is at this time a packet transmission signal. For example, it may be the second bit. The remaining bits may be in an arbitrary state.

 According to the fifth micro-command, the first state and control word is read from the RAM 6 to the first group of address inputs of the memory device 7, and the word of the second of the registers 63 with or without the bit set is read from its second group of address inputs from the second group of I / O of the register device 8 carrier depending on the output states of the input signal detector 97. At the outputs of the storage device 7, a state and control word is generated with a modified bit 13. In this case, bit 13 is set to "1" or "0" depending on the state of the carrier bit.

 To modify bit 13, the control inputs of the memory device 7 receive a command to modify the bit 13 of the first state word depending on the status of the carrier bit on the second group of address inputs of the memory device 7. From the memory cell of the memory device 7, the address of which is contained in the first and second groups of address inputs and control inputs of the storage device 7, the outputs of the operation entered in the cell during the manufacture of the controller are read at its outputs.

 The implementation of special operations on operands supplied to the first and second groups of address inputs of the memory device 7, such as the operations of addition, subtraction, multiplication by a constant, converting the addresses of the control system bus 19 to the addresses of the RAM 6, converting control words to codes, and others special operations, allows to ensure the execution of routines in the required limited time intervals, which is necessary to ensure real-time processes. At the same time, the task of reducing hardware costs is solved, since there is no need to use registers in the controller to store state and control words, and state and control words are stored in RAM 6, and there is no need to connect additional logic to the register outputs, since the analysis of register states is performed on the storage device 7 with the subsequent transition to the control routines of the control encoder 11.

 According to the sixth micro-command, the output signals from the inputs / outputs of the storage device 7 are sent through the second of the registers 63 of the register device 8, through the data inputs of the interface 1 to the controller data bus 17.

 According to the fourth micro-command of the subroutine for recording the first state word and control, the signals of this word from the data bus 17 are fed to the first group of address inputs of the memory device 7. The operation code for analyzing the states of the bits of the first state word and control is supplied to the control inputs and the second group of address inputs of the memory device 7. When this operation is performed, the control program codes are generated at the status outputs of the storage device 7, which are decoded by the decoder-converter 72 of the initial address and converted to the address of the fifth micro-command.

 The following subprograms are possible, which the control program switches to based on the results of the fourth micro-command execution: Enabling software survivability timer, setting or disabling the loopback mode, program initialization, prohibition or permission to receive.

 According to the fifth micro-command to enable operation of the software survivability timer and to set the loopback mode on or off, the first state and control word is written from the first group of address inputs of the memory device 7 through its inputs and outputs into the main memory 6. According to the fifth micro-command to ban or allow reception to the second group of inputs control receiver 12 is fed a reception prohibition signal when bit 00 of the first word of states and control is reset, or a reception permission signal when bit 00 of this is set fishing. In this case, the control logic 100 generates a reset signal, supplies it to the R-input of the RS-flip-flop 94 and holds the reset signal from the moment of generation of the reception prohibition signal until the formation of the reception permission signal. In this case, the level "0" at the output of the RS-flip-flop resets the counter 98 bits, which makes it impossible to record the received data in FIFO 90 reception.

 According to the sixth micro-command, the first word of states and control through the storage device 7 is recorded in RAM 6.

 According to the fifth micro-command of the software initialization, a constant zero is generated at the inputs / outputs of the memory device 7, which is recorded in the second register of the register device 8. Based on the same micro-command, the bus controller 2 generates a ready signal confirming the end of the write cycle on the signals of the third group of its inputs, and on the outputs of the bus issues it to the system bus 19 control. With this, the controller ends its participation in the program recording mode from the computer 21 of the first word of the state and control. Computer 21 should not contact the controller until the end of software initialization. Next, the controller modifies the bits of the memory cells (set or reset) required from the conditions of its operation, in particular, writes the constant zero to the cell of the first word of state and control and to the cell of the second word of state and control, writes 6 words from the memory of 70 microcommands to RAM destination physical address, word number and word number. The addresses of the cells in which these words are stored in the RAM 6 are read from the memory 70 of the microcommands via the multiplexer 69, through the first of the registers 63 to the inputs of the address of the RAM.

 During controller initialization, the priority priority code is set on the priority control inputs of the 9 interrupt controller, which does not allow the interruption of the initialization subroutine during its execution. At the end of the initialization subroutine, the control bus 16 receives a zero level signal to the input of the adder increment 85, the instructions for reading the address of the microcommand are sent to the inputs of the instructions of the decoder 89, and the outputs of the shaper 73 are micro addresses, after which the subprogram loops over the micro command because its address does not increase in the adder 85, according to the pulses from the synchronization input of the driver 73 of the micro command address is copied from the outputs of the driver 73 of the address of the micro command in register 84. Current prior code itet at the inputs of the priority control of the controller 9 interrupt is set so as to allow interruption of the control program for the input signals of the request controller interrupt.

 All control subroutines of the program exchange mode, except for the initialization subroutine, are completed by returning to the subroutines interrupted by them, for which, according to the last microcommand of the subroutines from registers 63 having a stack organization, their contents are pushed out, the upstream counter 65 returns data from the interrupted subroutine to the top of the stack registers 63. The same microcommand is ejected from the glass 86 through the second group of inputs of the multiplexer 88 to its outputs the addresses of the microcommand of the interrupted subprogram. According to the last micro-command, a confirmation signal for the end of the write or read cycle is issued to the control system bus 19.

 The maximum number of microcommands in the control subroutines of the controller program exchange mode, excluding the initialization subroutine, is eleven. At a runtime of one microcommand of 200 ns, the maximum runtime of the controller for reading and writing subroutines in program exchange mode is 2.2 μs. The current priorities of the control exchange routines of the program exchange do not allow their interruption by other routines.

 The subroutine of the master timer is necessary for solving problems, firstly, the distribution of access time to the system bus between the computer 21 and the controller, and secondly, for calculating the software timer of the controller. The subroutine of the master timer is implemented as follows.

 The counter-timer 77 counts the pulse generator 75. The decoder 78 detects the status of the outputs of the counter-timer 77, corresponding to the lapse of a certain time interval after resetting the latter, for example, 51.2 μs, after which from the output of the decoder 78 to the S-input of the RS-flip-flop 79, a signal is supplied that sets the internal interrupt request signal at the second output of the control encoder 11, which is input to the request of the interrupt controller 9. If there are permissive priority levels at its priority control inputs, the interrupt controller 9 at its outputs generates an internal interrupt vector of the master timer subroutine, which, under the control of the control output from the interrupt controller 9, passes to the outputs of the multiplexer 71, after which the first micro command of the timer subroutine setter. At the beginning of the execution of the subroutine, the second group of control inputs of the transmitter 13 and the second group of control inputs of the receiver 12 receive signals to stop direct memory access, by which the receiver 12 and transmitter 13 stop supporting the direct memory access mode, if it is already running.

 The subroutine of the master timer calculates the values of the packet timer, marker timer, monitor timer, software survivability timer. According to the results of the analysis of the second word of states and control performed on the storage device 7, the subroutine can be completed by switching to the data exchange subroutines in direct access mode.

 When the subroutine of the master timer is executed, the signals from the outputs of the counter-timer 77 are overwritten through the multiplexer 69 to the register device 8, and then they arrive at the second group of address inputs of the memory device 7, the first group of address inputs of which are read out from the memory cells 6 words of the survivability timer software, transmission timer, marker timer, monitor timer, from which the numbers from the outputs of the counter-timer 77 are subtracted, and the difference signals are generated at the outputs of the storage device 7. If the difference is greater than the number zero, then it is recorded in the memory cell 6, in which the subtracted was stored. If the difference signals determine a number less than the number zero, then this implies the presence of a timeout of the corresponding timer, and an output transfer signal is generated at the transfer output of the storage device 7 and supplied through the conditions multiplexer 74 to the input of the conditions of the driver of the micro-command address 73. At the input transfer signal, subroutines for transmitting the monitor package, marker transfer, and computer initialization are performed.

 According to the input transfer signal at the input of conditions and if there is a conditional transition instruction at the inputs of the instructions of the micro-command address 73, the address signals of the timer-setter program are received from the controller control bus 21 through the address inputs of the micro-command address generator 73 to its outputs. In the absence of an output transfer signal, by incrementing on the adder 85 by the address unit of the previous micro-command, the transition to the next micro-command is performed, by which the bits of the second state and control word are analyzed. It is read from random access memory 6 to the first group of address inputs of memory device 7, the outputs of which, depending on the state of the bits of the second state and control word, generate codes for the direct access mode preparation routine for reading the receive buffer descriptor if bit 01 of the second state and control word is set and the remaining bits are cleared, or the routines for reading the flag word of the receive buffer descriptor if bit 01 and bit 04 are set, or the routines for reading the other words in the receive buffer descriptor if the bit 04 is set, and the remaining bits are reset.

 If bit 00 is set, a transition is made to the direct access mode preparation routine for reading the transmit buffer descriptor. If bit 00 and bit 02 are set, a transition is made to the flag word read routine. If bit 02 is set, and the remaining bits are cleared, a subroutine is sent from the computer 21 to the controller for the remaining words of the descriptor for the transmission buffer.

 The transition to the direct access preparation routine for sending the receive buffer is made if bit 04 and bit 09 are set. If bit 09 is set, and the remaining bits are cleared, a transition is made to the data transfer routine from FIFO reception 90 to the computer receive buffer 21. If bits 09 and 05 are set, a transition is made to the preparation routine for sending the transfer buffer descriptor from the controller to the computer 21. This subroutine is performed after the transfer of data from the computer 21 transfer buffer to the controller is completed, the descriptor words are modified and the descriptor with modified bits must be returned to the computer 21.

 The transition to the direct access training routine for transferring the transmission buffer is performed if bit 02 and bit 08 are set. If bit 08 is set, and the remaining bits are cleared, a transition is made to the data transfer routine from the transmission buffer of the computer 21 to the transmission FIFO 107.

 If bits 08 and 06 are set, this means that the transfer of packet data from FIFO reception 90 to the receive buffer of the computer 21 is completed, and now the controller must send the modified words to the receive buffer descriptor to the computer 21. By analyzing the second word of states and control, when bits 08 and 06 are set, the controller switches to the direct access mode preparation routine by sending the receive buffer descriptor to the computer 21.

 If bit 06 is set and the remaining bits are cleared, the controller proceeds to execute the subroutine for sending the receive buffer descriptor to the computer 21. If bit 12 is set and the remaining bits are cleared, the program is processed to the installation package.

 If all the bits of the second word of state and control are cleared, then a transition and looping is performed on a micro command, at the execution of which the value of the current priority signals with the lowest priority is set on the priority control inputs of the 9 interrupt controller, which allows internal interrupts to be performed upon requests at the interrupt controller 9 inputs.

 If, during the analysis of the second word of states and control, the transition to the subroutine is made using the set bit 00, then in this case the start address of the descriptor of the transfer buffer is reloaded from the RAM 6 into the address counter 3. If the transition is made according to the set bit 00, then the start address of the receive buffer descriptor is reloaded from RAM 6 to address counter 3. In both cases, signals of the sum of start addresses and the number five are loaded into the address register 4, which determines the address of the last word of the buffer descriptor. The addition operation is performed by the storage device 7. Then, in case of transfer of the transmission buffer, bit 02 in the second state and control word is set, bit 04 in the first state and control word is reset, or bit 04 is set in the case of sending the receive buffer descriptor in the second state and control word and is reset bit 05 in the first word of states and control, after which the bus controller 2 on the control system bus 19 sets a signal for direct access to the computer memory 21, the subprogram goes into cycling, and on the priority inputs of the controller 9 interruptions, the current priority is set, allowing you to interrupt the program.

 If the interruption occurs according to the outputs of the counter-timer 77 and the transition to the subroutine of the master timer is performed again, then the second word of states and control is analyzed again and when bit 00 and bit 02 are set or bit 01 and bit 04 are set, indicating that a direct memory access request signal is set, the transition to the looping subroutine is carried out again with a low current priority, which allows the execution of internal interrupts.

 The presence of a direct access confirmation signal on the system bus 19 of the controller, issued by the computer 21, leads to the installation on the system bus 19 of the control from the inputs / outputs of the controller 2 of the bus 2 bus busy signals and signals that establish the mode of "read - modify - write", and leads to the generation of interrupt request signals at the outputs of the controller 2 of the bus, causing the formation of 9 interrupts of the subroutine code on the outputs of the controller; read - modify - write in direct memory access, during which ik- 00 bits of the second word states and the control descriptor when sending or receiving buffer 01 is reset bit when sending descriptor transmission buffer is performed cycle "reading - modification - writing" Descriptor word flag. In this cycle, the descriptor flag word is read and, if the value of bits 15 and 14 is “1” and “0”, bit 14 is set and the flag word with the upgraded bit 14 is overwritten in the computer memory 21 at the same address. Counter 3 addresses is incremented by two units. After that, the current priority is set on the priority control inputs of the controller 9 interrupts, which allows interrupting subroutines such as initializing the controller, filtering packets by destination addresses, subroutine timer. Setting the low current priority is performed in the controller in all routines that implement direct memory access after the completion of each of the word exchange cycles.

 If the subroutine is not interrupted, the Read signal is set on the control system bus 19 from the side of the bus controller 2. On the address bus 18 from the bit outputs of the address counter 3, the address of the next descriptor word is set. The computer 21 puts the data on the data bus 17 and generates a signal "Ready". The addresses of the RAM 6 through the first of the registers 63 from the memory 70 of the microcommands are the address of the cell memory 6, in which the word is written from the data bus 17, after which the controller similarly reads the remaining words of the descriptor. Before the next cycle of reading the word is set, at the input of the conditions of the shaper 73 of the micro-command address, the signal from the output of "Equal" of the comparison circuit 5 is checked, which is set to unity when the codes on the bit outputs of the counter 3 of the address and the outputs of register 4 of the address match.

 If the interruption of the subroutine occurs between word exchange cycles, then in the next cycle of the subroutine of the timer-setter for analysis of the second word of state and control, when bit 04 is set, a direct access to the word exchange subroutine is returned. In this case, the controller sets bit 10 in the second state and control word and sets the direct access demand signal, and then proceeds to loop on the micro command with a low current priority. With the provision of direct access to the memory, the controller analyzes the second word of states and control, and according to the set bits 04 and 10, a transition is made to the subroutine for exchanging the remaining words of the descriptor, where bit 10 is reset.

 Similarly, interruption and return to the interrupted subroutine are performed in the remaining exchange modes in direct access to memory, return to the set bits 05 and 10, bits 08 and 10, 09 and 10. The set bit 10 means that there is a wait for direct access to memory from Computer 21.

 If there is a unit at the output of "Equal to" the comparison circuit 5, the Read signal is not generated, since all words of the address descriptor are overwritten into RAM 6. In the second state and control word, bit 08 is set if the transmit buffer descriptor, or bit 09, if the descriptor of the receive buffer was sent, after which the bus controller 2 removes the busy signal from the control system bus 19. This completes the mode of direct access to the computer memory 21 by sending buffer descriptors to the controller and the program enters the looping mode with a low current priority. The descriptor of the receive buffer and the descriptor of the transmit buffer are stored in different areas of the RAM 6.

 When reading the second descriptor word from the computer 21 during the execution of the transfer buffer descriptor transfer routine, the controller analyzes the 12 bit of the status byte. If this bit is set, then bit 12 is set in the second state and control word, which indicates the presence of the installation package in the transmission buffer. If in the subroutine of the master timer, when analyzing the second word of states and control, it is found that bits 02 and 08 are set, then a transition is made to the subroutine for preparing the transfer of the contents of the transmission buffer to transmitter 13. When this subroutine is executed, the lower addresses are written from RAM 6 to counter 3 and the high bits of the start address of the transmission buffer, which are contained in the second and third words of the descriptor of the transmission buffer. Then, the value of the start address of the transmission buffer is summed with the word value of the buffer length stored in the fourth word of the buffer descriptor. Thus, the final address of the transmission buffer is calculated and its value is sent to the address register 4. Bit 02 is reset and bit 10 is set in the second state and control word.

 The third group of control inputs of the controller 2 of the bus signals the initialization of the direct access to memory mode. In this case, the bus controller 2 issues a direct access demand signal to the control system bus 19 and the program is put into a looping mode with a low current priority.

 If in the subroutine of the master timer, when analyzing the second state and control word, it is detected that bit 08 and bit 10 are set, then the subroutine is put into a looping mode with a low current priority.

 If there is a direct access confirmation signal on the control bus 19, the bus controller 2 issues a read or write interrupt request signal to the third group of controller interrupt requests 9 for direct access and switches to a subroutine, during which bit 10 of the second state word is reset and management. The third group of inputs of the control logic 113 is used to transfer the transmitter 13 to the support mode of direct access to memory. The bus controller 2 on the control system bus 19 sets the bus busy signal and the Read signal. The address bus 18 is supplied with address signals from the bit outputs of the address counter 3.

 If there is a signal "Ready" on the control system bus 19, which the computer 21 accompanies the installation of data on the data bus 17, signals are generated at the control outputs of the bus controller 2, by which the data word is sent from the data bus 17 through the outputs of the interface 1 to the inputs of the transmitter 13.

 The controller serves several real-time processes. These include, for example, the mode of program exchange between the computer 21 and the RAM 6. During the exchange, the computer 21 writes to or reads data from the controller, accessing it at several addresses set on the address bus 18. The controller at the same time sends the data from the data bus 17 to the RAM 6 in the write mode or from the RAM 6 to the data bus 17 in the read mode.

 The real-time process is the exchange in direct access to the memory of the computer 21, when the controller, becoming active, on the system bus of the computer 21 in the read and write modes performs data exchange between the computer 21 and it.

 The real-time process is the process of recognizing destination addresses of packets received by the receiver 12, which should be completed taking into account other real-time processes before receiving the shortest packet. In particular, when implementing the IEEE802.3 standard, the transmission time of the shortest packet is 51.2 μs.

 Real-time processes are software timer calculation processes, which distribute the time for capturing the system bus between the computer 21 and the controller (timer-setter) or determine the time when the controller can start transmitting packets to the communication channel 24 (packet timer, timer of the manipulator, timer tokens - timers determining multiple access to the communication channel 24). The listed processes are performed with time sharing and taking into account their priority. The separation of the execution time of processes, taking into account their priority, is controlled by the controller 9 interrupts.

 As an example, the controller implements the interval-marker method of multiple access to the communication channel 24. The communication channel 24 can be performed using a radio frequency cable, into which, at some intervals of its length, data inputs and controller outputs are connected to lines 23. Data exchange on the communication channel 24 is carried out in packets.

 The interval-marker access method is a deterministic, that is, an access method that guarantees delivery of packets at finite time intervals. The transmission of packets to the communication channel 24 by the controllers 20 is carried out in order of priority. The sequence of packet transfers is determined by the controller number 20 (NU) specified by the computer 21. To implement the method, the controller programmatically calculates three timers: a marker timer, a monitor timer, and a transmission timer. To find its turn to transmit a packet, the controller maintains a software transmission timer, upon reaching the timeout (TAP) time of which the controller has the right to start transmitting the packet to the communication channel 24 in the time interval T. In general, the transmission time of the packet may exceed the time interval T, reserved for the beginning of the transmission of the packet. At the end of the interval T, the controller does not have the right to start transmitting the packet, since the next time interval T is reserved for the start of the transmission of the packet of another controller 20. When connecting the number of NG controllers 20 to the communication channel 24, NG time intervals are necessary for queuing for packet transmission from all network devices T.

When a packet is transmitted by any of the controllers 20, the others, upon detecting the transmission signals in the communication channel 24, must receive from the transmitted packet the word of the controller number (NUP) that is transmitting, and set their packet transmission timers to
TP = T (NUP + 1).

 At the end of the packet transmission signal in the communication channel 24, the controllers must continue the countdown of their transmission timers, starting from the value of T (NUP + 1).

 Transmission timers timeouts are determined by the expression TAP = TNU, where NU is the number of the controller that calculates the transmission timer timeout.

When setting gear timers to
TP = T (NUP + 1), controllers whose numbers are less than NUP + 1 cannot start the transmission of packets, because the timeouts of their transmission timers have already expired. Only controllers with NU numbers located on a segment can start transfers
[NUP + 1, NG], where NG is the boundary time for the transmission timers of all devices.

In the time span
[(NG + 1) T, (NG + 2) T] the packet of the monitor station should be transmitted. The monitor station package contains the number zero in the controller number field. This makes it possible for the packet to be transmitted to the monitor station to begin transmitting the packet to the controller with the first number, since the transmission timers of all the controllers are set to TP = T. Thus, all the controllers in turn have access to the communication channel 24. The guaranteed access time to the communication channel 24 for a particular controller is determined by the sum of the product T (NG + 2) and the product of the maximum packet transmission time by the number of controllers connected to the communication channel 24.

To protect the communication channel 24 from conflict situations, packet transfers can only be started when the controller is synchronized in the communication channel 24. The start of entering the synchronization mode is determined by the reception permission signal coming from the computer 21 (bit 00 of the status and control word is set). From this moment, the controller counts the time with the software timer of the marker, setting its timeout (TAM) to
TAM = (NГ + NУ + N) T, where N is a constant, an integer is greater than one.

Any transmission over communication channel 24 should reset the token timers of the controllers. If after the TAM time in the communication channel 24 there are no transmission signals of other controllers 20, then the controller in the time interval
[(NT + NU + N) T, (NG + NU + 1) T] should start the transfer of the token, after which it starts the countdown of the monitor timer, the timeout of which is set to
TAMON = NUT, where NУ is the number of this controller.

 If, before the monitor timer expires, the monitor packet is transmitted by the controller with the lower NU number, then the monitor packet is not transmitted. After the monitor timer timeout expires, the controller should begin transmitting the monitor packet with bit 14 set in the packet control field.

After transmitting the monitor package, the controller starts counting down again with the monitor timer, setting its timeout to
TAMON = (NG + 1) T.

 After the monitor timeout expires with the value TAMON = (NG + 1) T, the controller must transfer the monitor packet with bit 13 set to the packet control field, after which it becomes a monitor on the local area network and constantly transmits monitor packets after the monitor timeout equal to (NG + 1) T.

If the controller could not transmit the marker due to the fact that the marker timer was reset by another controller, then at the end of the transmission signal in the communication channel 24, the controller should begin the countdown with the marker timer set to timeout:
TAM = (NG + NU + N) T.

If the controller detects the transmission of the monitor packet with the bit set during the TAP time, then the transmission of packets to the communication channel 24 after the transmission timer has timed out, the value of which must be set to
TAP = NUT.

 The monitor device has the right to transmit data packets and must set the timeout of its transmission timer to the value TAP = NUT.

 To reduce the access time to the communication channel 24, the time interval T should be minimal, but it cannot be less than the sum of the doubled signal propagation time on the cable of the communication channel 24 and the controller reaction time necessary for organizing the transmission of the “own” packet at the end of the transmission of the previous “alien” "packet, plus frame interval - the time during which transmissions are prohibited to ensure attenuation of the signal in the cable after transmission. So, if the doubled signal propagation time through the cable is 51.2 μs, the inter-frame interval is 9.6 μs, and the controller reaction time does not exceed 53 μs, then the time interval T equal to 153 μs can satisfy the presented requirement.

 To set the monitor timer and the packet transmission timer, the controller, during cable transmission, performs the operation of multiplying NUP + 1 numbers by the time interval T = 153 μs. The product resulting from the operation is subtracted from the monitor timeout value, as well as from the transmission timeout value. The results of the subtraction operation are recorded in the timer cell of the monitor and the timer cell of the transmission memory device 7.

 To calculate timers, the numbers equal to consecutive segments of the current time are subtracted from the monitor timer cell and the transmission timer cell until a zero result is achieved in one of the timers.

 The reference point of the first time interval is made from the end of the transmission of the next packet in the cable. A zero or negative result means that the corresponding timer has timed out.

 To ensure the necessary reaction time of the controller, the multiplication operation should be performed as soon as possible, for which a non-standard method of performing the operation is implemented. To perform the multiplication operation, the multiplicand is transformed as described below, and in the form of binary signals are supplied to the first and second groups of address inputs of the storage device 7, to the control inputs of which an operation code is supplied. From the cells of the storage device 7, the result of the operation on the outputs of the storage device 7 is read. The multiplier (number T = 153) is implicitly present in the multiplication operation.

 The words of the calculated program timers and the words of the timeout values of the timers are stored in RAM 6. These words are read or written after installing 6 control signals for reading or writing at the inputs of the control memory and setting 6 signals of constants from the second group of memory outputs at the inputs of the RAM address 70 micro-commands through the first of the registers 63, through the first group of outputs of the register device 8.

 The calculation of the timers is performed in the subroutine, which is transferred by the interrupt request signal from the output of the RS-flip-flop 79. The interrupt request is generated when the counter-timer 77 reaches its timeout. The timeout is determined by the decoder 78, from the output of which a signal is supplied to the S-input of the RS-flip-flop 79, which sets an interrupt request signal at the output of the RS-flip-79.

 According to the interrupt request signal, the interrupt controller 9 generates an interrupt vector at its outputs, and a control signal at the control output, by which the multiplexer 71 passes the interrupt vector to the inputs of the memory address 70 of the microcommands. Then, operations are performed on microcommands from the memory 70 microcommands, during which the time value generated at the outputs of the counter-timer 77 is subtracted from the contents of the timers, for which the signals from the outputs of the counter-timer 77 are sent through the multiplexer 69 to the register device 8 and then to the second group address inputs of the storage device 7, the first group of address inputs of which the words of the timers are read from the RAM 6. The memory device 7 calculates the difference between the values of the signals on the first and second ppah its address inputs. Upon receipt of a negative difference, a transfer signal is generated at the transfer output of the storage device 7, which determines the achievement of the timeout timers. The transfer signal is supplied through the conditions multiplexer 74 to the input of the conditions of the micro-command address generator 73, which, taking into account the signal at the input of the conditions, generates the starting address of the program that controls the transfer of the marker, the transmission of the monitor packet, the transmission of the data packet or the reset of the timers.

 Counter-timer 77, after reading signals from its outputs, should be reset to zero at the reset input, after which it continues to count pulses from the output of the generator 75.

 The number of the controller that transmits the packet, which is necessary to set the value of the timer for transmissions, as well as the destination address of the packet, is read from the fifo 90 of the reception through the multiplexer 91, through the inputs / outputs of the receiver 12 to the internal bus 15. This occurs while receiving the packet from the channel 24 communication through the data input of the receiver 12.

 During packet reception, a serial stream of data encoded in Manchester code is input to decoder 96. At the output of decoder 96, a serial data code is generated without returning to zero, followed by clock pulses at the synchronization output of decoder 96. Received data is converted to the outputs of the shift register 92 into parallel code. The flag detector 93, having deferred the preamble flag, generates a signal at its output, which sets the output of the RS flip-flop 94 to unity, and the reset signal is removed from the reset input of the 98-bit counter. The counter 98 bits starts counting the received data bits by counting the number of clock pulses from the synchronization output of the decoder 96. According to the signals from the outputs of the counter 98 bits, the control logic 100 supplies pulses to the counting input of the counter 99 to count the number of received words, to the control inputs 90 receiving signals recording words , and on the inputs of labels Fifo 90 prima signals labels received words. In this case, the received data words are recorded in Fifo 90 reception and labeled with word labels. When receiving a data signal from the input of the receiver 12 at the output of the input signal detector 97, a carrier signal is generated in the communication channel 24, at the end of which the control logic 100 generates a packet end mark signal supplied to the input fifo 90 of the reception, and a recording signal for recording the end mark of the received package in Fifo 90 admission. At the end of packet reception, a 99 byte counter is reset at its reset input by a signal from control logic 100.

 Timers are set when a packet is received. After receiving the destination address and the controller number word, the control logic 100 generates interrupt request signals for filtering the destination address of the packet by the output signals of the counter 99 bytes at the status outputs of the receiver 12. Based on these signals, the interrupt controller 9 generates an interrupt vector at its outputs, according to which the control encoder 11 switches to a packet filtering routine at their destination addresses and to a marker, monitor, and transmission timer setup routine.

 The subroutine for setting the timers starts after the subroutine for filtering destination addresses is executed, when three words of the destination address are read from Fifo 90 for reception to compare them with the table of destination addresses, which is set for the computer controller 21.

 For the destination addresses from FIFO 90, the word of the controller number is read, for which purpose the instruction to read the word from Fifo 90 receives through the multiplexer 91 to the internal bus 15 through which the control encoder 11 generates control signals to the second group of control inputs of the receiver 12 from the control encoder 11 FIFO control inputs 90 of the reception and control inputs of the multiplexer 91. The controller number word is fed to the first group of address inputs of the storage device 7. This completes the execution of the first micro command subprogram Amma set the timers.

 Suppose that the largest number of controllers connected to the communication channel 24 is 79 (NG = 79). Thus, the controller number (NUP) can be placed in the first six bits of the word controller number (bits 0-5). Suppose that the storage device 7 is partitioned and contains four sections 52 of the storage device, the first and second groups of address inputs of which contain four bits.

 When the second microcommand is executed, the word from the internal bus 15 is recorded in the second of the registers of the register device 8. The operation code is supplied to the control inputs of the memory device 7, during which the word is generated at the outputs of the memory device 7, bits 00 and 01, 04 and 05, 08 and 09, 14 and 15 of which are set in pairs equal to the value of the pair of bits 04 and 05 on the first group of address inputs of the storage device 7, i.e., bits of the transmitted packet controller (NUP) become equal bits 04 and 05. This is possible if the second section 52 of the storage device sends to its transfer outputs the two least significant bits supplied to the first group of its inputs unchanged, and the accelerated transfer circuit outputs these bits to the transfer inputs of section 52 of the storage device 7 as well, and then to the outputs of the lower bits sections 52 of the storage device are formed in pairs low-order bits equal to bits 05 and 04 words on the first group of address inputs of the storage device 7. The result of the operation is recorded in the third of the registers 63 of the register oystva 8. This completes the execution of the second microinstruction. Further, similarly, at the outputs of the storage device 7, as a result of another operation, a word is formed in which the bits are in groups of four 00, 01, 02, 03 and 04, 05, 06, 07, and 08, 09, 10, 11, and 12, 13, 14, 15 are equal to the bits 00, 01, 02, 03 of the word (NUP) of the transmitting device number, respectively. The signals from the outputs of the storage device 7 are recorded in the second of the registers 63, which completes the execution of the third microcommand.

According to the fourth micro-command, the signals of the second of the registers 63 are fed to the first group of address inputs of the memory device 7, the signals of the third of the registers 63 are fed to the second group of address inputs of the memory device 7, the control inputs of which are supplied with the operation code of the multiplication by the constant T of the number NUP + 1. The low-order bits of the NUP member are supplied to the second group of inputs, and the high-order bits are sent to the first group of inputs of each section 52. The unit level is transferred to the transfer input of the storage device 7, which is summed with the number of NUP during the operation. This level through the memory device 53 accelerated transfers extends to the input inputs of section 52. As a result of the operation on the outputs of section 52 are formed bits of the result of the operation
TP = T (NUP + 1), where T = 153 is set implicitly by the operation code.

 On the first and second groups of inputs of each of the sections 52 there are all six bits of the number of the transmitting device (NUP). Each section is individually programmed in such a way that at its outputs a group of four bits of the result word is formed. In four sections 52, all sixteen bits of the result word are generated, which is recorded in the second of the registers 63. The address constant of the cell of the memory device 7, in which the transmission timer timeout word is stored, is recorded in the first of the registers 63. This completes the fourth microcommand. If the execution time of one microcommand is 200 ns, then the TP value is calculated for four microcommands or 800 ns.

 According to the fifth micro-command, the value of the timeout of the transmission timer for the first group of address inputs of the storage device 7 is read from the RAM 6, the number of TSs that are subtracted from the timeout value is read from the register device 8.

 According to the sixth micro-command, the result is written into RAM 6 in the temporary storage cell of the transmission timer word.

 According to the seventh micro-command, from the RAM 6 the timeout value of the monitor timer is read, the value of the TP is subtracted from it. The result of the eighth microcommand is copied to the temporary storage cell of the timer monitor RAM 6.

 According to the ninth and tenth microcommands from the RAM 6, the marker timeout value is read from the marker timer timeout cell, the value of the marker timeout is subtracted from it, and the result is overwritten into the temporary storage cell, which completes the timer setup routine based on the results of receiving the packet from channel 24 of the communication .

 At the time of receiving the packet, the cyclic control logic 95 calculates a checksum to check the received data for errors. At the end of packet reception, in the absence of a carrier signal in the communication channel 24, determined by detector 97, and by signals from the outputs of the counter 99 bytes, when they are not equal to zero, interrupt request signals are generated at the outputs of the control logic 100 at the end of packet reception, which are fed to the outputs status of the receiver 12. Based on these signals, the interrupt controller 9 generates a vector and the transition to the timer start routine is performed. To this end, the signals from the second group of control inputs of the receiver 12 through the multiplexer 91 to the internal bus 15 read the signal from the control output of the logic 95 cyclic control, which determines the absence or presence of errors in the received packet. Signals from the outputs of the counter of 98 bits are read, determining the multiplicity of the received bits to the number eight, i.e., the multiplicity of the integer number of bytes, the signals from the outputs of the counter are 99 bytes, which determine the length of the received packet, if the received packet has a length within the acceptable range, if it ends on the byte boundary and has no errors, the words of the timer of the monitor, packet and marker are sent from the temporary storage cells to the corresponding timer cells of the marker, monitor and transmission in RAM 6.

If the packet was received with errors, then the marker timer is set to
TAM = (NG + NU + N) T, and the monitor and packet timers are greater than TAM, which allows you to not transmit packets to the cable until the controller is re-synchronized in the communication channel 24.

 The computer 21 generates a table of destination addresses, which the controller distinguishes as "their own", and receives packets with destination addresses specified in the table of destination addresses. The controller reads them in the direct memory access mode from the main memory of the computer 21. The controller does this before the computer 21 is allowed to receive and transmit packets to the communication channel 24. For example, a destination address table may contain fourteen 48-bit packet destination addresses. Of these, one address is broadcast, that is, intended for all devices on the network, the other is individual, that is, intended only for this controller. Such an address starts with a bit set to zero. The remaining addresses are group addresses, that is, they are intended for groups of devices that include this particular controller. A multicast address starts with a bit set to one.

 To ensure accelerated filtering, the destination address of the received packet is divided into twelve groups of bits, four bits in each group (twelve nibbles). Each of the nibbles is addressed to one of the groups of memory cells 6. In each group there are sixteen memory cells. From memory cells to which nibbles are addressed, data (matching words) is read, which makes it possible to determine whether a given nibble is part of one of the destination addresses specified in the destination address table. If all nibbles of the received destination address are defined as nibbles of the same destination address specified in the destination address table, the packet is received by the controller in Fifo 90 reception.

 The controller generates a table of matching words. Correspondence words form 6 twelve groups of sixteen words in RAM. For these groups, a page of the area of RAM 6 with a size of 21 words is assigned. To address words of correspondence within a page, it is enough to have eight bits of inputs of the address of RAM 6. From the fourth to seventh bits, the addresses indicate the group number, from zero to third bits - to one of the words of correspondence in the group. Before compiling a table of words of correspondence, all memory cells located on the page must be zeroed.

 The group number is set in accordance with the nibble number in the destination address of the filtered packet. The nibble count is maintained from the number 0 to the number 13. From zero to third digits are mapped to zero to third digits of the nibbles of the destination addresses.

 Bits 0-13 of each of the matching words are opposed to one of the fourteen addresses specified in the destination address table. If, for example, bit 5 of the word located on the match words page is set, and from zero to seventh digits the addresses of the RAM cell containing this match word have the value 00110110, then set bit 5 means that the third nibble (third, from the fourth to the seventh because the bits of the RAM address have the value 0011) of the fifth (since bit 5 of the correspondence word is one) from the addresses specified in the destination address table, it has the value 0110 (from zero to the third bits of the RAM address dissolved value 0110).

 When forming the words of correspondence, the controller reads directly the words of the destination addresses through the data bus 17, through the interface 1 and the multiplexer 14 from the table of destination addresses located in the main memory of the computer 21, to the internal bus 15. The read word of the destination address is written in the second of the registers 63 and converted to the outputs of the storage device 7 so that bits 0-3 remain equal to bits 0-3 of the word on the internal bus 15, bits 4-7 are reset, and bits 8-16 are set to the value necessary for addressing to the opera page RAM 6, on which a word table of words is stored. The word from the outputs of the storage device 7 is sent through the first of the registers 63 to the inputs of the address of the RAM 6, from which the selected matching word is read to the internal bus and converted to the storage device 7 by setting the unit to zero. The result is entered into RAM 6 at the old address. The presence of a unit in the zero bit of the correspondence word, which was addressed with four bits of the first nibble of the first word of the destination address, indicates that it is such a first nibble in the first word of one of the destination addresses. Next, the contents of the second of the registers 63 are read onto the internal bus 15 and the second nibble of the first word of the destination address is sent to the outputs of the storage device 7. In this case, bits 0-3 at the outputs of the storage device 7 become equal to bits 4-7 on its first group of address inputs, bits 4-7 at its outputs acquire the values 0001, the remaining bits are set, as before, to address the corresponding page. RAM 6 is addressed through the first of the registers 63 to the new address. Another word is read to the outputs of RAM 6. The zero bit of this word is set to unity and the converted word is written to the old address.

 In the same way, the conversion is made with two other nibbles of the first word of the destination address stored in the first of the registers 63. As a result, four matching words are generated in the RAM 6, one of which is set to zero. Next, from the computer 21, the second and then the third words of the first destination address are read. With these words, the same conversions are performed as with the first word of the destination address. After that, twelve matching words are formed in RAM 6, which is equal to the number of nibbles in the destination address. In all matching words, the zero bits are set to units. These matching words are located one in each of the groups of matching words on the page of matching words of RAM 6.

 Similarly, correspondence words are generated for the remaining destination addresses called from the computer 21, only with the difference that for the second destination address in the matching words located in RAM 6, the first bits are set to unity, and for the third destination address, the third bits and etc. for all twelve destination addresses.

 Such a correspondence table in RAM 6 allows you to quickly filter received packets by destination addresses in order to simultaneously perform several real-time processes.

 Packet filtering is performed as follows. When switching to the packet filtering subroutine, the control encoder 11 transfers to the second group of control inputs of the receiver 12 the signals by which, under the control of the control logic 100, the destination address word is read from the receiving FIFO 90 through the multiplexer 91 to the internal bus 15 and written to the second of the registers 63. On This completes the first micro command of the subroutine.

 Then, bits 0-3 are sent to bits 0-3 of the outputs of the storage device 7, bits 4-7 of which are set to zero, this corresponds to the first nibble of the received destination address, bits 8-15 are set to the page of matching words (second microcommand). The generated word is used for addressing the RAM 6, from which the correspondence word is read on the internal bus 15 and entered in the third of the registers 63. This correspondence word is also tested by the memory device 7 to detect bits set to one in it (third microcommand).

 If at least one bit of the match word is set to one, then this means that the received nibble of the destination address is in the destination addresses allowed for the table to receive the destination addresses. If, for example, the unit is set in the sixth bit of the match word, then this means that the first nibble of the received destination address and the first nibble of the seventh destination address from the destination address table are the same. In this case, the subroutine continues, and otherwise stops, the package is recognized as a “foreign”, not intended for this controller, and the execution of the subroutine ends.

 When the subroutine is continued, the words of the address of RAM 6 are formed, in bits 0-3 the bits of the remaining nibbles of the destination address are set one by one, in bits 4-7 the nibble number is set, and in bits 8-15 the address of the page of matching words is set. Correspondence words are read from RAM 6, each time the logical multiplication operation is performed on a word read from RAM 6 and a word stored in the third of registers 63. The result is entered back into the third of registers 63 and tested for the result in the word at least one bit set to one.

 Let the sixth bit is set to one in the correspondence word of the second nibble of the received destination address. This means that the second nibble of the received destination address and the second nibble of the seventh destination address from the destination address table are the same. When performing a logical multiplication operation on a word stored in the second of the registers 63 and read from the RAM 6, the result of the operation contains the sixth bit set to one. This means that the seventh destination address from the destination address table and the received destination address have the same first bytes. Thus, the belonging of the received address to the destination address table is established.

 The total number of microcommands executed in the subprogram taking into account the logical multiplication operation is 48 microcommands, or 9.6 μs will be required to execute it.

 Since the filtering subroutine is quite long, and the total operating time of the controller is divided between several real-time processes, for this reason the packet filtering subroutine by destination address may be interrupted by a subroutine in which program exchange between the computer 21 and the controller is performed.

 If a program exchange between them can be completed in a time not exceeding 2.6 μs, and the Ready signal, by which the program exchange ends and which the controller issues, should be issued no later than 7.2 μs after the receipt of the Read signal "or" Record "with the computer 21, it is advisable when filtering the destination addresses to the priority control inputs of the controller 9 interrupts from the control encoder 11 to issue signals of the current priority every 3 μs (15 microcommands), allowing higher-priority subprograms You can interrupt the execution of the destination address filtering routine.

 The proposed controller compares favorably with the prototype, as it has a wider field of application while reducing hardware costs for its implementation. The extension of the scope is expressed in the fact that the controller can be used in systems that perform real-time data exchange, when computers work together with a limited address space allocated for addressing to registers of external devices. An example of such computers is computers built on the basis of microprocessors of the 580 series, where 256 addresses are allocated for addressing the registers of external devices.

 In the prototype, control data (state and control words) is written to the controller registers in program exchange mode. The number of registers is determined by the number of words of control data that the controller must simultaneously store. To ensure the operation of the latter in real-time modes, each of the bits of the registers is connected to the control encoder. At the same time, hardware registers are required for the registers and the control encoder, depending on the number of registers in which the control data is stored.

 In the proposed controller, the exchange of control data is performed both in program exchange mode and in direct memory access mode. The exchange of control data performed by the proposed controller in the direct memory access mode allows to reduce to the required minimum the address space reserved for addressing the registers of external devices. Processing of control data on the storage device with subsequent generation of codes on its outputs that are transformed by the decoder-converter of the initial address into a control action (into the address of the corresponding subprogram) is performed for a cycle of reading or writing direct access mode or program exchange mode, i.e., in the process real-time data exchange management.

 Reducing the address space reserved for addressing the registers of external devices, and the exchange of control data in direct access to the computer memory while maintaining the requirements for the controller when working in real time, can expand the scope of the controller. At the same time, it can work together with computers that have a limited address space reserved for addressing the registers of external devices, and perform data exchange in real time.

 The use of random access memory for storing control data exchanged both in direct access mode and in software exchange allows reducing hardware costs due to the absence of external device registers, as well as due to the absence of control logic associated with each of the categories of external registers devices. Such control logic is replaced in the proposed controller memory device and interrupt controller. The generation of control signal codes at the outputs of the storage device during the real exchange of control data and the real-time arbitration of processes performed by the interrupt controller make it possible not to use the control logic associated with each of the bits of the external device registers and to exclude these registers from the controller.

 To implement the proposed option requires memory cells in RAM for storing control data. When exchanging these cells programmatically, ten are required. When exchanging buffer descriptors (with seven transmit buffer descriptors and seven receive buffer descriptors), 42 memory cells are required. When exchanging the installation package, 256 memory cells are required. The use of RAM when using, for example, 541RU2 series microcircuits for a sixteen-bit internal bus 15 allows you to have only four cases of such microcircuits instead of more registers.

Claims (1)

 A CONTROLLER comprising a bus controller, an interface, an address selector, an address counter, an address register, a comparison circuit, a receiver, a transmitter, a control encoder, wherein the inputs / outputs of the bus controller are connected to the system control bus, the first group of interface inputs and outputs is connected to the data bus, the second group of its inputs and outputs is connected to the address bus, its data inputs are connected to the internal bus, its address outputs are connected to the address inputs of the address selector, the bit outputs of the address counter are connected to the inputs of the interface address CA and to the first group of inputs of the comparison circuit, the second group of inputs of which the outputs of the address register are connected, the inputs of the address counter data and the information inputs of the address register are connected to the internal bus, the input of the address counter record, the input of the address register record, the second group of interface control inputs, the third the group of control inputs for the bus controller, the second group of control inputs for the transmitter, the second group of control inputs for the receiver, the first group of control encoder outputs connected to the control bus, control output The bus bus is connected to the counting input of the address counter, the output is “Equal to” the comparison circuit is connected to the first input of the control encoder, the data input of the receiver is connected to the device input of the same name, the output of the transmitter is connected to the output of the device, characterized in that RAM, a memory device are inserted into it , register device, interrupt controller, multiplexer, and the bus controller control outputs are connected to the address selector control inputs, to the first group of interface control inputs, to the first group receiver control inputs and to the first group of transmitter control inputs, the first group of bus controller control inputs is connected to the transmitter control outputs, the second group of bus controller control inputs is connected to the receiver control outputs, receiver inputs and outputs, transmitter inputs and outputs, RAM memory inputs and outputs , inputs and outputs of the register device, the first group of address inputs of the storage device are connected to the outputs of the multiplexer and to the internal bus of the device, the outputs of the receiver are connected to the inputs of the interface, the inputs of the transmitter are connected to the outputs of the interface, the inputs of the address of the RAM are connected to the first group of outputs of the register device, the outputs of the memory device are connected to the third group of inputs of the register device, the outputs of the states of the memory device are connected to the first group of inputs of the control encoder, the second group of address inputs the storage device is connected to the second group of outputs of the register device, the first group of inputs of the register device is connected to the second the control encoder outputs group, the second group of inputs of the register device is connected to the third group of outputs of the control encoder, the third group of outputs of the register device is connected to the control inputs of the storage device, the control input of the control encoder is connected to the transfer output of the storage device, the transfer input of which is connected to the first output of the control encoder , the second group of inputs of the control encoder and the first group of inputs of the interrupt controller request are connected to the status outputs the receiver, the transmitter status outputs are connected to the third group of control encoder inputs and the second group of interrupt controller request inputs, the third group of request inputs of which and the fourth group of control encoder inputs are connected to the bus controller outputs, the address selector outputs are connected to the fourth group of interrupt controller request inputs, the second the control encoder output is connected to the interrupt controller request input, the control output of which is connected to the second control encoder input, the input is the clock of the interrupt controller and the synchronization input of the register device are connected to the third output of the control encoder, the outputs of the interrupt controller are connected to the fifth group of inputs, the outputs of the interface address are connected to the first group of information inputs of the multiplexer, the output of the interface is connected to the second group of information inputs "comparison circuit connected to the control input of the receiver and the input of the transmitter, the inputs of the priority control of the interrupt controller, the control inputs RAM memory, control inputs of the multiplexer, control inputs of the register device are connected to the control bus of the device.

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