KR0150754B1 - Bus control circuit using clock phase difference - Google Patents

Abstract

The present invention relates to a bus adjustment circuit using a phase difference of a clock. The present invention relates to arbitrary N logic means 101 for receiving a reset signal, any N bus allowable signals, and its own bus request signal and outputting a reset signal for control. ); And an arbitrary N clocks are input to each clock terminal CLK to receive a bus request signal from any N processors, and to allow a bus according to its timing. Any N flip-flop means 102 for outputting a signal includes one information source, that is, a memory, an input / output device, or a data channel, by which any number of processors divide it in time and effectively share two or more Any number of processors can share a single source of information, the circuit configuration can be made irrespective of the type of processor, and the integrated circuit (ASIC) for application purposes of the circuit can be achieved.

Description

Bus adjustment circuit using phase difference of clock

1 is a system configuration to which the present invention is applied.

2 is an overall configuration diagram according to an embodiment of the present invention.

3 is an operation timing diagram according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

101: logic section 102: flip-flop

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus adjustment circuit using a phase difference of a clock. In particular, in a high reliability system in which a plurality of processors are to be duplicated or tripled, a common memory is shared, and one processor through a system bus is connected to a plurality of processors through a common memory. The present invention relates to a bus adjustment circuit that communicates with a processor and uses a phase difference of a clock that allows a plurality of processors to transmit and receive information through a single data bus.

Conventionally, the bus request signal of a plurality of processors and the bus permission signal are used by using a simple AND gate or a negative AND gate. In this case, either the output method is used or the designer arbitrarily configures the delay flip-flop (D flip-flop) and the processor state information according to the application purpose. However, in the former case, it is difficult to set the priority because the bus request signal occurs at the same physical point of time or the initial state at power-on, and in the latter case, the circuit configuration varies according to the application purpose and the type of processor. .

Accordingly, the present invention devised to solve the above-described problems of the prior art is that any number of processors share one information source, that is, a memory, an input / output device, or a data channel, in a timely manner, and effectively share it. Two or more processors can share a single source of information, can be configured regardless of the type of processor, and provides a bus adjustment circuit using a clock phase difference capable of forming an integrated circuit (ASIC) for circuit application purposes Its purpose is to.

The present invention for achieving the above object is any N logic means for receiving a reset signal, any N bus permit signal, its own bus request signal and outputting a reset signal for control; And an arbitrary N clocks are input to each clock terminal CLK, and a bus request signal is input from any N processors to output a bus permission signal according to its timing. And any N flip-flop means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a configuration diagram of a system to which the present invention is applied, in which reference numeral 10 denotes a bus adjustment circuit of the present invention, 20 a clock supply means, 30 a processor, 40 a buffer means, and 50 a memory or an input / output device, respectively.

The clock supply means 20 generates clock signals that are out of phase with each other and supplies them to the bus adjustment circuit 10. The bus adjustment circuit 10 receives a reset signal from the outside, receives a bus request signal from any of the N processors 30, and outputs a bus allowance signal to any N buffer means 40 and the processor at its timing. Output to The bus enable signal input to the buffer means 40 is used as an enable signal of the buffer. When the bus permission signal is input, the processor 30 receives or outputs data of each of a plurality of addresses or data signals through the plurality of buffer means 40.

By operating as described above, any one of a plurality of processors divides one information source, that is, a memory, an input / output device, or a data channel, and effectively shares it in time, and two or more arbitrary numbers of processors share one information source. can do.

2 is a schematic configuration diagram of a bus adjustment circuit using a phase difference of a clock according to an embodiment of the present invention, where 101 is a logic unit and 102 is a flip-flop.

The operation of the present invention will be described with reference to FIG. 3, wherein a clock signal is inputted with any number of N clocks corresponding to the number of processors, and the clock signal has N N phases different from each other as shown in FIG. The clock is input. In addition, the reset signal is activated for a certain time when the power is turned on and is input from the outside. In the present invention, the reset signal is operated to 'high'. According to the present invention, the N logic unit 101 and the flip-flop 102 are configured. The flip-flop 102 is composed of delay elements, and the logic unit 101 is configured to reset signals and N bus allowable signals from the outside. A logic gate gate for receiving the bus request signal of the processor 30 by AND and multiplying the fed-back bus permission signal and the bus request signal, and a reset signal and its bus permission signal which are different from the output of the AND gate. It is composed of a logic sum gate for outputting the logical sum of the bus allowable signal except for and outputting the control signal for controlling the flip-flop 102. The flip-flop 102 receives a bus request signal to the data terminal D and outputs a bus permission signal at its timing under the control of the logic unit 101.

The above process will be described in more detail with reference to FIG. 3. For convenience of description, the case where the number of processors is three will be described as an example. The bus request signal, the bus enable signal, and the reset signal are assumed to be an active low signal, marked with a * at the end of the signal, and the flip-flop 102 is assumed to operate at the rising edge of the clock signal.

The reset signal is applied for a predetermined time when the system is powered on, and the output Q of all the flip-flops is in a high voltage state, and bus permission is prohibited. Only a specifically allowable processor can enable bus requests and permits by not applying the reset signal to a preset input. When the reset signal is terminated, the bus adjustment operation starts under the concept of pre-request and pre-approval for all processors.

The clock signal is supplied by the number of processors of clocks 1, 2, and 3 that are out of phase with each other, and as shown in FIG. 3, the bus request signals 1 *, 2 *, and 3 are physically identical at the same time. Even if *) is output, each clock has a different phase difference with respect to rising edge when free-running, so that the processor using the clock with the rising edge first from the bus request point is the bus that is allowed to the bus first. If Permit 1 * is received, the other processor will remain at high voltage and wait.

The bus enable 1 * signal for the bus request 1 * signal is provided from the rising edge of the clock signal clock 1 to the next rising edge after the termination, so that the bus switching time is automatically guaranteed by the phase difference between different clocks.

The processor that generates the bus request 2 * signal receives the bus enable 2 * signal by its own clock 2 and uses the bus after the bus switching time between the two clock rising edges after the bus occupancy of the first processor.

The bus request and occupancy method of the third or other processor is such that the bus can be shared using the same method as described above.

Therefore, in the present invention operating as described above, two or more arbitrary multiple processors use a common memory or input / output device, a data channel independently of each processor, and use only a clock source having a different phase difference between clocks. It can be shared with the advantage of guaranteeing the bus transition time as much as the phase difference, so that the bus transition time is as much as the data retention time of the buffer, and this arbitration can be arbitrarily adjusted. Second, two or more arbitrary multiple processors Share common memory or common I / O devices and data channels, and the bus request and enable signals for each processor are determined by clocks that are out of phase with each other, so that the clock speeds are adjusted according to the importance of the application being executed. Ranks can be arbitrarily adjusted. Third, any number of processors A bus permit conditions has the advantage that you can give the same. On the contrary, in the case where the same clock source and constant delay element are used after temporarily prohibiting the bus allowance in order to implement different bus permits, the free-running method is required by the pre-required and pre-allowed method. By using a constant clock speed with a constant phase difference, the same bus tolerance can be implemented.

Claims (4)

Any N logic means 101 for receiving a reset signal, any N bus enable signals, its bus request signal, and outputting a reset signal for control; And an arbitrary N clocks input to each clock terminal CLK, and receive a bus request signal from an arbitrary N processors, according to its timing. And an arbitrary N flip-flop means (102) for outputting an allowable signal. 2. The logic unit of claim 1, wherein the logic unit (101) comprises: a logical AND gate for performing an AND operation on the feedback of its own bus allowance signal and the bus request signal input from the processor; And a logic sum gate for receiving the output of the AND gate and the reset signal and the bus permission signal of other flip-flop means except for the bus permission signal thereof. Adjustment circuit. The bus adjustment circuit according to claim 1, wherein the arbitrary N clocks receive clocks having different phases. 2. The bus adjustment circuit according to claim 1, wherein the flip-flop means (102) consists of delay elements.