KR970027494A - Bus adjustment circuit using phase difference of clock - Google Patents

Bus adjustment circuit using phase difference of clock Download PDF

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Publication number
KR970027494A
KR970027494A KR1019950040278A KR19950040278A KR970027494A KR 970027494 A KR970027494 A KR 970027494A KR 1019950040278 A KR1019950040278 A KR 1019950040278A KR 19950040278 A KR19950040278 A KR 19950040278A KR 970027494 A KR970027494 A KR 970027494A
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KR
South Korea
Prior art keywords
bus
signal
arbitrary
adjustment circuit
outputting
Prior art date
Application number
KR1019950040278A
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Korean (ko)
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KR0150754B1 (en
Inventor
김도영
김상중
전경표
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양승택
한국전자통신연구원
이준
한국전기통신공사
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Application filed by 양승택, 한국전자통신연구원, 이준, 한국전기통신공사 filed Critical 양승택
Priority to KR1019950040278A priority Critical patent/KR0150754B1/en
Publication of KR970027494A publication Critical patent/KR970027494A/en
Application granted granted Critical
Publication of KR0150754B1 publication Critical patent/KR0150754B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Information Transfer Systems (AREA)

Abstract

본 발명은 클럭의 위상차를 이용한 버스 조정 회로에 관한 것으로, 리셋신호, 임의의 N개의 버스허용신호, 자신의 버스요구 신호를 입력받아 제어를 위한 리셋 신호를 출력하는 임의의 N개의 로직수단(101); 및 상기 로직 수단(101)의 리셋 신호에 의해 제어되고, 임의의 N개의 클럭을 각각의 클럭단자(CLK)에 입력받아 임의의 N개의 프로세서로부터 버스요구신호를 입력받아 자신의 타이밍에 맞춰 버스허용 신호를 출력하는 임의의 N개의 플립플롭 수단(102)을 구비하여 하나의 정보원, 즉 메모리, 입출력 장치, 또는 하나의 데이타 채널을 임의의 다수의 프로세서가 이를 시간적으로 분할하여 효과적으로 공유하여 2개 이상 임의 갯수의 프로세서가 하나의 정보원을 공유할 수 있으며, 프로세서의 종류와 무관하게 회로 구성이 가능하며, 회로의 응용 목적용 집적회로(ASIC)화가 가능한 효과가 있다.The present invention relates to a bus adjustment circuit using a phase difference of a clock. The present invention relates to arbitrary N logic means (101) for receiving a reset signal, arbitrary N bus allowable signals, and its own bus request signal and outputting a reset signal for control. ); And an arbitrary N clocks are input to each clock terminal CLK to receive a bus request signal from any N processors, and to allow a bus according to its timing. Any N flip-flop means 102 for outputting a signal includes one information source, that is, a memory, an input / output device, or a data channel, by which any number of processors divide it in time and effectively share two or more Any number of processors can share a single source of information, the circuit configuration can be made irrespective of the type of processor, and the integrated circuit (ASIC) for application purposes of the circuit can be achieved.

Description

클럭의 위상차를 이용한 버스 조정 회로Bus adjustment circuit using phase difference of clock

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명이 적용되는 시스템 구성도.1 is a system configuration to which the present invention is applied.

제2도는 본 발명의 일실시예에 따른 전체 구성도.2 is an overall configuration diagram according to an embodiment of the present invention.

제3도는 본 발명의 일실시예에 따른 동작 타이밍도.3 is an operation timing diagram according to an embodiment of the present invention.

Claims (4)

리셋신호, 임의의 N개의 버스허용신호, 자신의 버스요구 신호를 입력받아 제어를 위한 리셋 신호를 출력하는 임의의 N개의 로직 수단(101); 및 상기 로직 수단(101)의 리셋 신호에 의해 제어되고, 임의의 N개의 클럭을 각각의 클럭단자(CLK)에 입력받아 임의의 N개의 프로세서로부터 버스요구신호를 입력받아 자신의 타이밍에 맞춰 버스허용 신호를 출력하는 임의의 N개의 플립플롭 수단(102)을 구비한 것을 특징으로 하는 클럭의 위상차를 이용한 버스 조정 회로.An arbitrary N logic means (101) for receiving a reset signal, any N bus enable signals and its own bus request signal and outputting a reset signal for control; And an arbitrary N clocks are input to each clock terminal CLK to receive a bus request signal from any N processors, and to allow a bus according to its timing. And an arbitrary N flip-flop means (102) for outputting a signal. 제1항에 있어서, 상기 로직 수단(101)은, 피드백된 자신의 버스허용 신호와 프로세서로부터 입력된 버스 요구신호를 논리곱하여 출력하는 논리곱 게이트; 및 상기 논리곱 게이트의 출력과 리셋 신호, 그리고 자신의 버스허용 신호를 제외한 다른 플립플롭 수단의 버스허용 신호를 입력받아 이를 논리합하여 출력하는 논리합 게이트를 구비한 것을 특징으로 하는 클럭의 위상차를 이용한 버스 조정 회로.2. The logic unit of claim 1, wherein the logic unit (101) comprises: a logical AND gate for logically multiplying the own bus allowed signal fed back and the bus request signal input from the processor; And a logic sum gate for receiving the output of the AND gate and the reset signal and the bus permission signal of other flip-flop means except for the bus permission signal thereof. Adjustment circuit. 제1항에 있어서, 상기 임의의 N개를 클럭은 위상이 서로 다른 클럭을 입력받는 것을 특징으로 하는 클럭의 위상차를 이용한 버스 조정 회로.2. The bus adjustment circuit according to claim 1, wherein the arbitrary N clocks receive clocks having different phases. 제1항에 있어서, 상기 플립플롭 수단(102)은 지연 소자로 구성된 것을 특징으로 하는 클럭의 위상차를 이용한 버스 조정 회로.2. The bus adjustment circuit according to claim 1, wherein the flip-flop means (102) consists of delay elements. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950040278A 1995-11-08 1995-11-08 Bus control circuit using clock phase difference KR0150754B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950040278A KR0150754B1 (en) 1995-11-08 1995-11-08 Bus control circuit using clock phase difference

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950040278A KR0150754B1 (en) 1995-11-08 1995-11-08 Bus control circuit using clock phase difference

Publications (2)

Publication Number Publication Date
KR970027494A true KR970027494A (en) 1997-06-24
KR0150754B1 KR0150754B1 (en) 1998-10-15

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