JPH07200420A - Resetting controller - Google Patents

Abstract

PURPOSE:To perform resetting control over >=2 different functions through simple constitution. CONSTITUTION:When a process module A performs a resetting control over process modules B and C, the process module A sends out a resetting sent signal 2A whose pulse width is a 16-clock period to a resetting control line RCL. Thereby, a resetting request signal 3A for this resetting sent signal 2A is masked by a system bus interface part A2 and a reset request signal 3B is fetched by a system bus interface part B2 effectively to perform a resetting process. Further a resetting request signal 3C is also fetched effectively by a system bus interface part C2 to perform a resetting process. Further, a resetting request signal 3D is supplied to a system bus interface part D2, but a resetting signal 4D is not supplied to a main module part D1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset control device, and more particularly to a device in which a plurality of processing modules, processing devices, etc. are connected to a reset control line and various reset controls can be performed.

[0002]

2. Description of the Related Art In recent years, electronic devices that perform digital processing are often provided with a plurality of processing modules inside, and these processing modules are connected to a system bus. In many cases, the processing module that performs these digital processes controls the use of the system bus by a system control module or the like. In an electronic device having a plurality of processing modules that perform digital processing with such a configuration, in operation, a power-on reset at power-on, a program logical abnormality in program processing, a data abnormality, etc. Depending on the case, the process may be reset in the middle.

Therefore, here, the mechanism of the reset control of the electronic device that performs the digital processing described above will be specifically described with reference to the drawings.

FIG. 2 is a functional block diagram of a conventional processing device. In FIG. 2, the processing device mainly includes a system control module D0 and a 1-system processor module A0.
And a 0 system processor module B0 and a 0 system memory module C0. These modules are connected to the system bus SB.

The system bus SB of FIG. 2 is composed of a reset control line RCL, a data bus line and the like.
The reset control line RCL is, for example, from the 1-system processor module to the 0-system processor module B.
It is used to reset the processing for 0 and the 0-system memory module C0 when the processing is abnormal. Therefore, the reset request signals 2a, 2b, 2c from the modules A0, B0, C0 are sent to the reset control line RCL which is OR-connected. In addition, the reset control line RC
The reset request signal sent to L is for each module A0,
The received signals 3a, 3b and 3c are given to B0 and C0.

Further, the system control module D0 shown in FIG.
Generates the signals d1 to d3 for performing the power-on reset POR and initializing all the internal states of the processing apparatus when power is applied to the processing apparatus, and the processing modules A0, B0,
Give to C0. By this operation, the state inside the processing apparatus can be returned to the initial state.

Further, in FIG. 2, for example, when the 1-system processor module A0 detects a processing abnormality during the processing operation, a reset request signal 2a is sent to the reset control line RCL to reset the 0-system module (this). , For example, Other Reset: OtherRese
t, or ORS for short. ). Then, the 0-series processor module B0 and the 0-series memory module C0 are given the reset request signals as the reception signals 3b and 3c to bring them to the initial state.

[0008]

However, as described above, the processing apparatus shown in FIG. 2 has the power-on reset POR function and the other reset ORS function as the reset operation in terms of the operation of the apparatus. In one case
System module to 0 module, other reset OR
Reset control line RCL for S and power-on reset PO performed by system control module D0
Since the signals d1 to d3 for performing R are provided with separate control lines, the number of wirings (reset control lines RCL) increases and the power-on reset POR signal is transmitted when the number of processing modules in the apparatus increases. There is a problem that the circuit and the configuration of the circuit for sending the other reset ORS signal are complicated.

Further, as the number of wires increases as described above, the number of connecting pins of the bus connector must be increased, and the size of the connector must be increased.

For example, in the case of a communication control device installed in a bank for financial processing business of a bank connected to a public line (ISDN), there are actually 10 or more processing modules in the system. Since it is connected to the bus SB, a mechanism capable of performing different types of reset control (power-on reset POR and other reset ORS) with a simpler mechanism has been desired.

Further, as another conventional technique, for example, in the technique of "Reset circuit of common bus connection module" of the invention of Japanese Utility Model Laid-Open No. 61-189326, different types of reset are performed by the above reset control lines. No configuration is suggested that could provide control. In addition, for example, the technique of the invention "reset control system of multiprocessor" disclosed in Japanese Patent Laid-Open No. 3-132860 is to issue a reset signal in a pulse shape for a time necessary for resetting the multiprocessor. As described above, no technique has been suggested that can perform reset control such as a power-on reset POR and another reset ORS of different types on the reset control line.

Further, as another conventional technique, Japanese Patent Laid-Open No.
The technique of the failure recovery method in the multi-host system disclosed in Japanese Patent No. 180948 does not suggest a technique for performing functionally different types of reset control in the system. In addition, JP-A-4-155542
The technology of the invention "restarting method at the time of bus lock" of the publication is
A technique for turning on the reset line to restart the processor when the bus is locked, and a technique for performing the above-described functionally different types of reset control has not been suggested.

From the above, a plurality of processing modules or processing devices are connected to the reset control line in the device or the system, and at least two or more different functions are provided in such a device configuration or system configuration. When reset control can occur, it has been desired to realize a reset control mechanism that can be realized with a simple configuration by reducing the number of reset control lines.

[0014]

SUMMARY OF THE INVENTION Therefore, the present invention has a sending circuit for sending a reset control command signal to a reset control line, a receiving circuit for receiving a reset control command signal from the reset control line from the reset control line, and a receiving circuit. In a reset control device, a processing module having a reset processing circuit that performs reset processing based on a reset control command signal is connected to at least two or more reset control lines,
It is realized by the following characteristic means.

The reset control command signal is, for example,
A signal for resetting the entire device, a signal for resetting a part of the device, and the like.

Here, the processing module has a function of sending and receiving the reset control command signal, and may be a processing device or a communication device.

That is, the sending circuit of each processing module is provided with a circuit for sending a reset control command signal having a different signal form corresponding to the processing module to be reset, in order to indicate which processing module is to be reset. I shall. The signal form here may be, for example, a pulse-like signal form or an analog signal form. More specifically, they may have different pulse widths or different analog signal modulation characteristics.

Further, in the receiving circuit of each processing module,
It is provided with a reset judgment circuit that judges from the signal form of the reset control command signal given from the reset control line whether it is for the self-processing module, and operates the reset processing circuit if it is for the self-processing module. .

[0019]

According to the reset control device having such means,
When multiple processing modules are connected to the reset control line and you want to reset the entire processing module from a certain processing module, reset the reset control command signal in the signal form (for example, pulse width) for resetting the entire processing module. It is given to the whole processing module through the control line. When any signal forms the reset determination circuit for receiving circuit in advance by setting the whether is for self, is given a reset control command signal for resetting the entire device, the receive circuit Perform a reset.

Further, when a certain transmission circuit wants to reset the target processing module, the reset control command signal which this processing module can recognize is given to the processing module through the reset control line, so that the target processing module is reset. Can only be reset.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described with reference to the drawings. Further, in this embodiment, the reset type (power-on reset PO
R, other reset ORS, system reset SRS, etc.) to change the time for which the reset signal is valid, and the receiving side of the reset signal to determine the reset type by the valid time of the reset signal The number of control lines can be minimized. The system reset SRS
Is a module that controls the system in a certain device,
The following description will be given as a reset operation for initializing all the processing modules in the apparatus.

Therefore, in the first embodiment, the system reset SRS when the invention is applied to a certain basic processing apparatus.
The reset operation for the other reset ORS will be described. It is assumed that the power-on reset POR is performed by powering on the device, and the system control module inside the device performs the system reset SRS. Further, in the other reset ORS, it is assumed that a specific module other than the module that issued the other reset ORS is reset.

"First embodiment": FIG. 1 is a block diagram of a processing apparatus. In FIG. 1, the processing apparatus is composed of processing modules A, B and C and a system control module D. And these modules A to D
Are connected to the system bus SB. The system bus SB is composed of a data bus line, a reset control line RCL, and the like. In FIG. 1, focusing on reset control, each module is connected to the reset control line RCL. There is.

(Structure of Processing Module A): In FIG. 1, the processing module A is composed of a main module unit A1 and a system bus interface unit A2. The main module unit A1 is for performing a certain process. Then, the main module part A1 gives an other reset (ORS) request signal 5A to the system bus interface part A2. When the main module unit A1 receives the reset signal 4A from the system bus interface unit A2, it resets the process to the initial state. By this reset, for example, the program processing operation, the logic circuit operation, and the like are initialized.

When the system bus interface section A2 of the processing module A of FIG. 1 receives the other reset (ORS) request signal 5A from the main module section A1, it sends the other reset sending signal 2A to the reset control line RCL. When the system bus interface unit A2 receives the reset request signal 3A from the reset control line RCL, the system bus interface unit A2 generates a reset signal 4A and supplies it to the main module unit A1.

In the system bus interface section A2 of the main module section A of FIG. 1, the input 6A is an input for controlling the system reset SRS, but this processing module A is a module that performs the system reset SRS. Is not used in processing module A (input 6A is open). Since the system reset SRS is performed by the system control module D, it will be described there.

The system bus interface section A2 of the processing module A shown in FIG. 1 is specifically shown in FIGS. Then, the system bus interface unit A2
Is composed of a transmission circuit IT (FIG. 3) and a reception circuit IR (FIG. 4).

(Structure of Processing Module B): The processing module B of FIG. 1 is also connected to the reset control line RCL of the system bus SB and is composed of a main module B1 and a system bus interface section B2.
The system bus interface unit B2 is specifically composed of a transmission circuit IT (FIG. 3) and a reception circuit IR (FIG. 4).

The main module B1 shown in FIG. 1 receives the reset signal 4B from the system bus interface B2.
Is given, the process is initialized.
Further, the system bus interface unit B2 is connected so as to be able to send the other reset ORS sending signal to the reset control line RCL. Further, the system bus interface unit B2 is connected to receive the reset request signal 3B from the reset control line RCL.

The system bus interface unit B2
In this example, from the processing module A to the other reset O
Since an example of receiving RS or receiving system reset SRS from the system control module D is going to be shown, input 5B (other reset request signal input) and input 6B (system reset request signal input) are not used,
It is open (not connected).

(Structure of Processing Module C): The processing module C of FIG. 1 is also connected to the reset control line RCL of the system bus SB and is composed of a main module section C1 and a system bus interface section C2. . The system bus interface section C2 is specifically composed of a transmission circuit IT (FIG. 3) and a reception circuit IR (FIG. 4).

The main module section C1 of FIG. 1 receives the reset signal 4C from the system bus interface section C2.
Is given, the process is initialized.
Further, the system bus interface unit C2 is connected so as to be able to send the other reset ORS sending signal to the reset control line RCL. Further, the system bus interface unit C2 is connected so as to receive the reset request signal 3C from the reset control line RCL.

The system bus interface unit C2
In this example, from the processing module A to the other reset O
Since the example of receiving RS or receiving system reset SRS from the system control module D is shown, input 5C (other reset request signal input) and input 6C (system reset request signal input) are not used,
It is open (not connected).

(System Control Module D): FIG.
The system control module D connected to the reset control line RCL is composed of a main module section D1 and a system bus interface section D2. The main module D1 supplies the system reset SRS request signal 6D to the system bus interface unit D2. Then, the system bus interface unit D2 gives the system reset transmission signal 2D to the reset control line RCL. Further, the system bus interface section D2 is connected so as to be supplied with the reset request signal 3D from the reset control line RCL.

The system bus interface section D2
Specifically, the transmitting circuit IT (FIG. 3) and the receiving circuit IR
(FIG. 4) and.

(Structure of System Bus Interface Unit): System bus interface unit A2 in FIG.
B2, C2, and D2 can all be realized with the same circuit configuration. Then, as described above, the system bus interface unit includes a transmitter circuit (FIG. 3) and a receiver circuit IR.
(FIG. 4) and. Therefore, the operation of these transmission / reception circuits is performed next.

((Configuration of Transmission Circuit IT)): FIG. 3 is a circuit configuration diagram of the transmission circuit IT. In FIG. 3, the transmission circuit IT is mainly a transmission circuit ITa for other reset.
And a system reset transmission circuit ITb. The other reset transmission circuit ITa is
It is composed of an OR circuit 30, a gate circuit 31, a flip-flop 32, and a 4-bit counter 33.

Further, the system reset transmission circuit ITb
Is composed of an OR circuit 34, a gate circuit 35, a flip-flop 36, and a 5-bit counter 37.

In FIG. 3, as a common circuit,
There is an OR circuit 38 on the output side, from which the reset sending signal 2A (2B, 2C) for other reset or the reset sending signal 2D for system reset is sent.

((Operation of Transmission Circuit IT)): In FIG. 3, for example, when the other reset transmission circuit ITa of the transmission circuit IT is given the other reset request signal 5A from the main module unit A1 and becomes valid for one clock or more, Four
Enable count enable CE bit counter ^{(2 quaternary} counter) 33 (logic 1, high) is a. Then, the OR circuit 38 sends a reset sending signal to the reset control line RCL. After that, the 4-bit counter 33 counts 16 clocks, and then the carry output C
When Y (high level pulse) is sent to the gate circuit 31, the sending of the other reset sending signal 2A is stopped (invalid). That is, the other reset transmission signal 2A is effectively transmitted while counting 16 clocks.

Further, in FIG. 3, for example, the transmitting circuit I
The system reset transmission circuit ITb of T is supplied with the other reset request signal 6D from the main module part D1.
When it becomes valid for more than one clock, the count enable CE of the 5-bit counter ( ²⁵ counter) 37 is made valid (logic 1, high level). Then, the OR circuit 38 sends a reset sending signal to the reset control line RCL. After that, the 5-bit counter 37 counts 32 clocks and then the carry output CY (high level pulse)
Is sent to the gate circuit 35, the sending of the system reset sending signal 2D is stopped (invalid). That is, the system reset transmission signal 2D is effectively transmitted while counting 32 clocks.

((Configuration of Receiver Circuit IR)): FIG. 4 is a circuit configuration diagram of the receiver circuit IR. In FIG. 4, the receiving circuit IR includes gate circuits 40 and 42 and an OR circuit 4
1, a flip-flop 43, and an 8-bit counter 44
It consists of and.

The reset request signal 3A is effectively taken in by the other reset OR from another processing module.
S, or a system reset SRS request from the system control module D. Then, the gate circuit 40
Takes in the reset request signal (high level pulse),
When valid for 1 clock or more, 8-bit counter (2 ⁸
The count enable CE of the counter 44 is made valid (logic 1, high level). Then, the flip-flop 43 starts outputting the reset signal 4A to the main module A1. Then, the 8-bit counter 44 has 256
(= 2 ⁸ ) Carry output CY after counting clocks
When (high level pulse) is sent to the gate circuit 42,
The output of the reset signal 4A is stopped.

That is, while counting 256 clocks, the other reset ORS or the system reset SRS
Is effectively done. Incidentally, a signal 32a from the flip-flop 32 of the transmitting circuit ITa for other reset of the transmitting circuit IT (FIG. 3) is given to the inverter input of the gate circuit 40 of the receiving circuit IR, whereby a certain processing module A generates the other reset ORS. In this case, the reset signal is not generated in the main module part A1 of the self-processing module A.

(Operation of system reset SRS):
Next, referring to FIG. 1, the system control module D sends a system reset S to the processing modules A, B and C.
The operation when performing RS will be described. First, the system control module D performs a power-on reset by turning on power to the processing apparatus, and performs a system reset for all processing modules A, B, and C inside the apparatus. Therefore, the main module section D1 supplies the system reset request signal 6D to the system bus interface section D2.

Then, the system bus interface section D
2 outputs the system reset SRS transmission signal 2D as a high level pulse for 32 clocks. The system reset SRS transmission signal 2D is transmitted to the reset control line RCL connected by the wired OR connection, and all the processing modules A, B, and
System reset request signal 3A, 3B, 3C to C
Given as.

The system bus interface unit A2 of the processing module A, to which the system reset request signal 3A is applied, applies the system reset signal 4A to the main module unit A1 for 256 clocks. As a result, the main module unit A1 can reset the processing operation.

Similarly, when the processing module B is given the system reset request signal 3B from the reset control line RCL, the system bus interface unit B2 of the processing module B sends the system reset signal 4B to the main module unit B1 for 256 clocks. Give to As a result, the main module unit B1 can reset the processing operation.

Similarly, when the processing module C is supplied with the system reset request signal 3C from the reset control line RCL, the system bus interface section C2 of the processing module C sends the system reset signal 4C to the main module section C1 for 256 clocks. Give to As a result, the main module unit C1 can reset the processing operation.

As described above, the system control module D can perform the reset control on all the processing modules A, B and C inside the apparatus by using the reset control line RCL.

(Operation of Other Reset ORS for Processing Modules A to B and C): FIG. 1 and FIG.
The operation of the other reset ORS from the processing module A to the processing modules B and C will be described with reference to the circuit diagram of FIG. 4 and the timing chart of FIG. First, the main module part A1 of the processing module A gives an other reset request signal 5A to the system bus interface part A2. Then, the system bus interface unit A2 causes the other reset transmission circuit ITa of the transmission circuit IT.
Is another reset transmission signal 2A for 16 clocks.
(FIG. 5A) is generated and sent to the reset control line RCL.

Then, the other reset transmission signal S1 (FIG. 5B) transmitted to the reset control line RCL is given to the processing modules A, B, C and the system control module D. Therefore, the other reset request signal 3B (FIG. 5 (e)) given to the processing module B is given to the system bus interface unit B2. Then, here, for 256 clocks, the reset signal 4B (see FIG.
(F)) is given to the main module part B1 to reset the process.

Further, the other reset request signal 3C (FIG. 5 (g)) given to the processing module C is given to the system bus interface section C2. Then, here, for 256 clocks, the reset signal 4C (FIG. 5 (h))
To the main module B1 to reset the process.

On the other hand, the processing module A is also supplied with the other reset request signal 3A (FIG. 5C) to the receiving circuit IR of the system bus interface section A2, but the flip-flop of the transmitting circuit ITa for the other reset of the transmitting circuit IT. The signal 32a from 32 is the gate circuit 4 of the receiving circuit IR.
Since it is given to the inverter input of 0, the other reset request signal 3A is masked (reception prohibited), and the reset signal 4A (FIG. 5 (d)) is not output to the main module part A1. As a result, the processing module unit A that has issued the other reset request is not reset.

Further, the system control module D is also provided with the other reset request signal 3D to the system bus interface section D2. The signal 4D (reset signal) of the receiving circuit IR output of this system bus interface section D2 is the main module section D1. It is not connected so that it is not given to, so it cannot be reset.

By the above operation, the other reset ORS can be performed from the processing module A to the processing modules B and C.

(Operation when System Reset and Other Reset Occur at Same Time): Next, referring to FIGS.
The operation when the other reset from the processing module to the processing modules B and C and the system reset from the system control module D occur at exactly the same time will be described with reference to FIGS. 4 and 6. Therefore, in such a case, the other reset transmission signal 2 from the processing module A is sent.
A (FIG. 5A) and the system reset transmission signal 2D (FIG. 5B) from the system control module D are transmitted to the reset control line RCL at exactly the same time.

Then, assuming that the pulse widths of the other reset transmission signal 2A and the system reset transmission signal 2D transmitted to the reset control line RCL are exactly the same width (time), these two reset signals S1 are the reset request signal 3A.
(FIG. 5 (d)), 3B (FIG. 5 (f)), 3C (FIG. 5)
(H)) 3D is simultaneously given to each processing module A-D. Then, the processing module 3B receives the reset request signal 3B (Fig. 6 (f)), and the system bus interface unit B2 outputs the reset signal 4B (Fig. 6 (g)) for 256 clocks to output the main module unit. Reset B1.

At the same time, when the processing module C also receives the reset request signal 3C (FIG. 6 (h)), the system bus interface section C2 outputs the reset signal 4C (FIG. 6 (i)) for 256 clocks. The module part C1 is reset.

On the other hand, in response to the reset request signal 3A (FIG. 6 (d)) given to the processing module A, the system bus interface section A1 itself sends out the other reset sending signal, so that the receiving circuit IR The reset request signal 3A is masked (prohibition of acceptance), and the reset signal 4A (FIG. 6 (e)) is not given to the main module part A1.

Although the reset request signal 3D is given to the system control module D, the reset signal 4D output from the system bus interface section D2 is not reset because it is not connected to the main module section D1.

As described above, when the other reset request (sending) signal from the processing module A and the system reset request (sending) signal from the system control module D occur at exactly the same time, the processing module B and C are reset, but the processing module A is not reset. Therefore, although the other reset operation can be realized, the system reset operation is not completely realized.

(Operation when System Reset and Other Reset Occur at Different Times): However, actually, in the case of system reset SRS, system reset sending signal 2D from system bus interface section D2.
(FIG. 7B) is transmitted for 32 clocks. on the other hand,
In the case of the other reset ORS, the other reset transmission signal 2A (FIG. 7A) is transmitted to the reset control line RCL for 16 clocks. Thus, in reality, even if the other reset ORS and the system reset SRS are started at the same time, the other reset transmission signal 2A
The sending period of FIG. 7 (a) is a period of 16 clocks, while the system reset sending signal 2D (FIG. 7 (b)).
The transmission period of the system reset transmission signal 2D (see FIG. 7) is 16 clock periods.
The sending period of (b)) is long.

Therefore, the reset control line RCL for the other reset transmission signal 2A and the system reset transmission signal 2D is used.
The reset signal S1 (FIG. 7 (c)) remains on the reset control line RCL for 32 clocks. When the reset signal S1 is started, the reset request signal 3B (see FIG. 7) is sent to the processing module B.
(F)) is given for 32 clocks. As a result, the system bus interface unit B2 applies the reset signal 4B (FIG. 7 (g)) to the main module unit B1 for 256 clocks to reset it.

At the same time, the reset request signal 3C (FIG. 7 (h)) is also applied to the processing module section C for 32 clocks. As a result, the system bus interface unit C
2 applies the reset signal 4C (FIG. 7 (i)) to the main module unit C1 for 256 clocks to reset it.

At the same time, the reset request signal 3A is given to the processing module A, but during the 16 clocks from the start of the reset signal S1, the other reset transmission signal 2A is sent.
Since it is during the period (FIG. 7A), the system bus interface unit A2 does not output the reset signal 4A during the 16 clocks (FIG. 7E1). However, when the sending period of the other reset sending signal 2A (FIG. 7A) ends, the system reset request signal 3A is not masked by the reset signal S1 by the system reset sending signal which continues at the same time, and the system bus interface unit is not masked. Between A2 and 256 clocks (Fig. 7
(E2)), the reset signal 4A is given to the main module part A1 and reset.

By the above operation, even if the other reset transmission and the system reset transmission are started at the same time, after the processing modules B and C are reset by the other reset transmission, the processing module A is also reset and the processing modules A to A system reset of C is also achieved.

[Effects of First Embodiment]: According to the reset control method of the processing apparatus of the first embodiment described above, the reset control line RCL of one line is provided between the processing modules A to C and the system control module D. Share and with other reset,
In order to achieve compatibility with system reset, the width of the reset transmission pulse (16 clock period for other reset, 32 clock period for system reset) is changed according to the type of reset. Each reset operation can be realized by the configuration.

Further, even if it is desired to increase the number of types of reset, the width of the reset transmission pulse is changed and set,
The type of reset can be increased only by providing a circuit for discriminating the reset pulse having this new pulse width.

[Second Embodiment]: The second embodiment is an embodiment in which the present invention is applied to the inside of a communication control device which can be connected to an ISDN line.

FIG. 8 is a block diagram of a communication control device capable of connecting the present invention to an ISDN line. In the communication control device shown in FIG. 8, a system control module 1, a 0-system processing module, a 1-system processing module, and a shared memory module 10 are connected to a system bus SB. The 0-system processing module and the 1-system processing module are used as an active system and a standby system.
Therefore, the 0-system processing module is the 0-system processor / memory module 2 and the 0-system ISDN control module 3
And a 0-system SCSI control module 6 and a 0-system LAN control module 7. Further, the 1-system processing module is the 1-system processor / memory module 4
It is composed of a 1-system ISDN control module 5, a 1-system SCSI control module 8 and a 1-system LAN control module 9.

The system bus SB is specifically composed of a 0-system reset control line RCL1, a 1-system reset control line RCL2, a data bus line, a control line and the like. Then, the 0-system reset control line R
CL1 includes a 1-system processor / memory module 4
The 0-system modules 2, 3, 6, and 7 are connected to the system control module 1. The 1-system reset control line RCL2 includes a 0-system processor / memory module 2 and 1-system modules 4, 5, 8, and 9,
The system control module 1 is connected.

Then, in the system control module 1,
The console 11 is connected. This console 11
Is for giving a system reset command to the system control module 1 and monitoring the state of the system control module 1.

The 0-system LAN control module 7 and 1
Each of the system LAN control modules 9 has an Ethernet
By et, it is connected to a personal computer or the like. Further, magnetic disk devices 6a to 6n are connected to the 0-system SCSI control module 6. Further, the 1-system SCSI control module 8 is also connected to the magnetic disk devices 8a to 8n.

Furthermore, the 0-system ISDN control module 3
Is configured so that it can be connected to an ISDN line.
It is for sending to the SDN host device or the like, and for taking in the data from the ISDN to this communication control device.
The 1-system ISDN control module 5 has the same function as the 0-system ISDN control module 3.

If an abnormality occurs in the 0-system, the 1-system processor / memory module 4 sends an other reset signal to the 0-system reset control line RCL1 to cause the 0-system modules 2 and 3 to operate. , 6, 7 are reset to another. The other reset signal at this time is to be transmitted with a pulse width of, for example, 16 clock periods as in the first embodiment.

When an abnormality occurs in the 1-system, the 0-system 0-system processor / memory module 2 becomes 1-system.
By sending an other reset signal to the system reset control line RCL2, each module 4, 5, 8, 9 of the first system is reset to another. The other reset transmission signal at this time is assumed to be transmitted with a pulse width of, for example, a period of 16 clocks as in the first embodiment.

Further, when the system control module 1 resets all the modules in the system, it sends a system reset sending signal to the 0-system reset control line RCL1 and the 1-system reset control line RCL2. Reset the system. The system reset transmission signal at this time is to be transmitted with a pulse width of, for example, a width of 16 clock periods as in the first embodiment described above.

Therefore, here, each of the modules 2, 3, 6, and 7 of the 1-system processor / memory module 4 to the 0-system.
Other reset operation to the system control module 1
The configuration and operation for performing the system reset from FIG.

Therefore, a partial view of FIG. 9 will be used as a partial view for explaining the other reset operation and the system reset operation from the above-described FIG. 8 (overall view of the apparatus). In FIG. 9, 1 is set to the 0-system reset control line RCL1.
It is shown that the system processor / memory module 4, the system 0 processor / memory module 2, the system 0 SCSI control module 6, and the system control module 1 are connected.

(Structure of 1-system processor / memory module 4): FIG. 10 is a block diagram showing an example of the 1-system processor / memory module 4. This FIG.
In the above, the 1-system processor / memory module 4 includes a main module section 4A1 and a system bus interface section 4A2. The main module unit 4A1 includes a CPU 4A1a, a ROM 4A1b, and a RAM 4
A1c and A1c are connected to the bus. And
The 1-system processor / memory module 4 is connected to the 0-system reset control line RCL1, and the other reset transmission signal 2
A is transmitted, and the reset request signal 3A can be received. The ROM 1D1b stores a program and is read out and processed based on an instruction from the CPU 1D1a. For example, the other reset request signal 5A is generated and given to the system bus interface unit 4A2. The RAM 1D1c temporarily stores working data being processed.

Then, the system bus interface unit 4
A2 is realized with the same circuit configuration (FIGS. 3 and 4) as that of the first embodiment described above.

(Structure of 0-system processor / memory module 2): FIG. 11 is a block diagram showing an example of the 0-system processor / memory module 2. In FIG. 11, the 0-system processor / memory module 2 includes a main module 2B1 and a system bus interface unit 2B.
2 and. And the main module section 2B
1 is CPU2B1a, ROM2B1b and RAM2B1
c and c are connected to the bus. The 0-system processor / memory module 2 is connected to the 0-system reset control line RCL1 so that it can receive the reset request signal 3B. And the ROM1B1b
Stores a program and is read and processed based on an instruction from the CPU 1B1a. RAM1B1c
Is for temporarily storing the working data being processed.

The system bus interface unit 2
B2 is realized by the same circuit configuration (FIGS. 3 and 4) as that of the first embodiment.

The processor / memory module 2
Uses the 0-system SCSI control module 6 to increase the speed of reading and writing the files stored in the magnetic disk devices 6a to 6n. In addition, this SCSI is Small Com
It is a putter system interface, and a dedicated LSI for this SCSI is already used in a personal computer or the like. The SCSI LSI is, for example, WD33C93
A (manufactured by Western Digital) and μPD72611
(Manufactured by NEC Corporation), HD6496IF (manufactured by Hitachi, Ltd.), MB87035 / MB87036 (manufactured by Fujitsu Limited), 53C700-66 (manufactured by NCR).
and so on.

(Structure of 0-system SCSI control module 6): Furthermore, FIG. 12 shows a structural diagram of the 0-system SCSI control module 6. In FIG. 12, 0
The system SCSI control module 6 includes a SCSI control main module unit 6C1 and a system bus interface unit 6C2.
It consists of and. The 0-system SCSI control module 6 is connected to the 0-system reset control line RCL1 so as to be able to receive the reset request signal 3C.

The system bus interface unit 6
C2 is realized with the same circuit configuration (FIGS. 3 and 4) as that of the first embodiment.

(Configuration of system control module 1):
Further, FIG. 13 shows a configuration diagram of an example of the system control module 1. In FIG. 13, the system control module 1 is composed of a main module unit 1D1 and a system bus interface unit 1D2. The main module unit 1D1 and the CPU 1D1a and the RO
M1D1b, RAM1D1c, and input / output unit 1D1d
Is connected to the bus and configured. Then, the system control module 1 uses the 0-system reset control line RCL1.
And is capable of delivering the system reset output signal 2D. And the ROM1D1b
Stores a program and is read and processed based on an instruction from the CPU 1D1a. For example, a system reset request signal 6D or the like is generated and given to the system bus interface unit 1D2. The RAM 1D1c temporarily stores working data being processed.
The input / output unit 1D1d also receives a system reset command from the console 11 and outputs processing status information to the console 11.

Then, the system bus interface unit 1
It is assumed that D2 is realized by the circuit configuration (FIGS. 3 and 4) similar to that of the first embodiment described above.

(Other Reset Operation from System 1 to System 0): Here, the operation for the processor / memory module 4 of system 1 to perform another reset on the module of system 0 will be described. Therefore, first, the CPU 4A1a of the 1-system processor / memory module 4 outputs the other reset request signal 5A to the system bus interface unit 4A2 through the bus. Then, the system bus interface unit 4A2 uses the circuit of FIG.
The other reset transmission signal 2A having a pulse width of 16 clocks is transmitted to the 0-system reset control line RCL1. Then, when this other reset transmission signal is given to the 0-system processor / memory module 2, the system bus interface unit 2B2 causes the reset request signal 3B.
Then, the reset signal 4B is output for a period of 256 clocks and is given to the main module unit 2B1 to generate CP.
U2B1a judges and resets.

Further, when the other reset transmission signal is given to the 0-system SCSI control module 6 as the reset request signal 3C, the system bus interface section 6C2 outputs the reset signal 4C for a period of 256 clocks and gives it to the main module section 6C1. Perform a reset.

The other reset transmission signal 2A is also given as a reset request signal 3A to the system bus interface section 4A2 of its own 1-system processor / memory module 4. However, since the transmitter circuit IT is configured as shown in FIG. 3, the reset request signal 3A is masked (rejection rejected or invalidated) by the gate circuit 40 in response to its own other reset transmission. The reset signal 4A is not output, and the 1-system processor / memory module 4 is not reset.

Furthermore, the reset request signal 3D is transmitted to the system control module 1 by the other reset transmission signal 2A.
However, the reset signal is not reset because it is configured not to output the reset signal to the main module unit 1D1.

As described above, in the 1-system processor / memory module 4, only the 0-system module can be reset.

(System Reset Operation) Next, the operation when the system control module 1 performs a system reset in the partial configuration of FIG. 9 will be described. Therefore, first, the system control module 1 is connected to the console 11
System reset command is given from CPU, CPU1D
1a generates a system reset request signal 6D and supplies it to the system bus interface unit 1D2. Then, the system bus interface unit 1D2 sends the system reset transmission signal 2 to the 0-system and 1-system reset control lines RCL1, 2
Send to. The system reset transmission signal 2D to be transmitted transmits a pulse having a pulse width corresponding to 32 clock periods by the circuit configuration of FIG. 3 described above.

Then, this system reset transmission signal is given to all the 0-system and 1-system modules. That is, in the case of the partial configuration diagram of FIG. 9, the reset request signal 3A is given to the 1-system processor / memory module 4. Then, the system bus interface unit 4A2 gives the reset signal 4A to the main module unit 4A1, and the CP signal
U4A1a judges and resets.

In the same manner as described above, the 0 system processor / memory module 2 and the 0 system SCSI in the partial configuration diagram of FIG.
The control module 6 is also reset. Further, the system reset transmission signal 2D is given to the system bus interface unit 1D2 of the own module 1 as the reset request signal 3D. However, since the system bus interface unit 1D2 itself issues the system reset transmission signal 2D, the gate circuit 4 of the receiving circuit IR is used.
At 0, the reset request signal 3D is masked (acceptance rejected or invalidated) and is not reset.

(Operation when the Other Reset from the 1st System to the 0st System and the System Reset Occur at the Same Time): Further, the processor / memory module 4 of the 1st system is set to 0
If the operation for applying the other reset to the system module and the operation for applying the system reset by the system control module 1 described above occur at the same time, 0
The system reset control line RCL1 includes a 1-system processor
Other reset transmission signal 2A from the memory module 4
And the system reset transmission signal 2D from the system control module 1 are transmitted at the same time. As a result, the above-mentioned operation is advanced and each module is reset.

The other reset transmission signal 2A has a transmission pulse width of 16 clocks, while the system reset transmission signal 2D has a transmission pulse width of 32 clocks. Therefore, in the processing module A of the first embodiment. Similarly to the operation, the 1-system processor / memory module 4 is also reset.

[Effects of Second Embodiment]: According to the reset control mechanism of the communication control device described above, the other system reset signal and the system reset signal having different functions are sent to the 0-system or 1-system reset control lines RCL1 and RCL2. Even if the sending signal is sent, the sending pulse width is different, so that the target module can be reset. Therefore, it can be realized with a reset control line having a simpler structure than the conventional one.

Further, even if it is desired to increase the number of types of reset, the width of the reset transmission pulse is changed and set,
The type of reset can be increased only by providing a circuit for discriminating the reset pulse having this new pulse width.

Other Embodiments: (1) The present invention can be realized in various modes other than the above embodiments. For example, a certain one line of the reset control line has a reset transmission circuit A and at least two or more reset reception circuits B,
C is connected, and the reset transmission circuit A can send reset request signals having different functions. The function of one reset request signal is to reset the receiving circuit B, and has a pulse width t1. The function of the other reset request signal is to reset the receiving circuit C, and has a pulse width t2. By doing so, the transmission circuit A can reset the reception circuit B by giving a reset signal of the pulse width t1 to the reception circuit B when resetting the reception circuit B, and the pulse width t2 when resetting the reception circuit C. The reset signal can be reset by applying the reset signal to the receiving circuit c.

(2) In addition, although the second embodiment has shown the example in which the invention is applied to the communication control apparatus, the invention is not limited to such an application. For example, it can be applied to a computer system in which a plurality of computers are connected to the reset control line.

(3) Further, in the above-described embodiment, the reset function can be identified by setting the pulse width of the reset signal to a different value depending on the function, but the present invention is not limited to this. For example, it may be set based on the pulse period, the number of pulses, or pulse information (combination of long and short pulses). Alternatively, the reset signal may be an analog signal and may be set by changing the modulation method of the analog signal (for example, FSK or PSK). In addition, FSK is Frequen
Abbreviation for cy Shift Keying, PSK
Is an abbreviation for Phase Shift Keying.

[0105]

As described above, in the reset control device of the present invention, when a plurality of processing modules capable of sending and receiving the reset control command signal are connected to the reset control line, each processing module is connected. In order to indicate which processing module the sending circuit of is to reset,
A circuit for transmitting a reset control command signal having a different signal form corresponding to the processing module to be reset is provided. Further, the receiving circuit of each processing module determines whether or not it is for its own processing module based on the signal form of the reset control command signal given from the reset control line. By including the reset determination circuit that operates the processing circuit, it is possible to perform a plurality of different reset controls in the device by using the reset control line with the minimum number of wirings.

[Brief description of drawings]

FIG. 1 is a device configuration diagram for explaining a reset control operation in a processing device according to a first embodiment of the present invention.

FIG. 2 is a device configuration diagram for explaining a reset control operation in a conventional processing device.

FIG. 3 is a circuit configuration diagram of a transmission circuit of a system bus interface unit of the first embodiment.

FIG. 4 is a circuit configuration diagram of a receiving circuit of a system bus interface unit of the first embodiment.

FIG. 5 is a timing chart (No. 1) of the first embodiment.

FIG. 6 is a timing chart (No. 2) of the first embodiment.

FIG. 7 is a timing chart (No. 3) of the first embodiment.

FIG. 8 is a configuration diagram of a communication control device according to a second embodiment of the present invention.

FIG. 9 is a partial configuration diagram of a communication control device of a second embodiment.

FIG. 10 is a configuration diagram of a 1-system processor / memory module of a second embodiment.

FIG. 11 is a configuration diagram of a 0-system processor / memory module of a second embodiment.

FIG. 12 is a configuration diagram of a 0-system SCSI control module of a second embodiment.

FIG. 13 is a configuration diagram of a system control module of a second embodiment.

[Explanation of symbols]

A to C ... Processing module, A1, B1, C1 ... Main module part, A2, B2, C2, D2 ... System bus interface part, D ... System control module, RCL ... Reset control line, 2A, 2B, 2C ... Other reset Sending signal, 2D ... System reset sending signal, 3A, 3B,
3C ... Reset request signal, 4A, 4B, 4C ... Reset signal.

Claims (3)

[Claims] 1. A sending circuit for sending a reset control command signal to a reset control line, and a receiving circuit for receiving a reset control command signal from the reset control line from the reset control line,
In a reset control device in which at least two or more processing modules each having a reset processing circuit that performs a reset processing based on the received reset control command signal are connected to a reset control line, the sending circuit of each processing module is In order to indicate whether to reset the module, a circuit for sending a reset control command signal having a different signal form corresponding to the processing module to be reset is provided, and the receiving circuit of each processing module has a reset control line. A reset control device comprising a reset determination circuit that determines whether or not it is for its own processing module based on the signal form of a control command signal and operates a reset processing circuit if it is for its own processing module. 2. The reset control device according to claim 1, wherein a signal form of the reset control command signal is a pulse signal, and a pulse characteristic or pulse information is changed according to a processing module to be reset. 3. The reset control device according to claim 1, wherein the reset control command signal has a signal form of an analog signal, and the characteristic of the analog signal is changed according to the processing module to be reset.