JP2866454B2 - Clock switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A clock switching circuit that dynamically switches between two clocks is provided, which is capable of effectively switching to a clock from the other clock source even when one clock source is not connected and the power is turned off. Generates a narrow chop pulse synchronized with the trailing edge of the clock pulse and synchronizes when switching clocks.Supplied as a clock to each stage except the last stage of the synchronization circuit consisting of multi-stage latches of master / slave FF. And the last stage master / slave
Monitors the mismatch between the input of the FF and the slave output, and when the mismatch is detected, supplies a chop pulse to the last master / slave FF and outputs the clock at the timing synchronized with the latch output of the master stage, that is, the trailing edge of the clock. It is configured to switch.

The present invention relates to a clock switching circuit that dynamically switches between two clocks and supplies the clock to an information processing circuit such as a CPU or a memory.

In a clock switching circuit that dynamically switches between two clocks, a synchronization circuit having a multi-stage latch configuration of a master / slave FF is provided for each clock, and at the time of switching, the synchronization circuit on the switching side sequentially latches a select valid signal. At the same time, the synchronization circuit on the disconnecting side is divided into two and the select invalidation signal is sequentially latched in parallel. For example, the selection invalidation signal is output from the last latch stage on the separation side by half the latch stage operation, and the output of the currently output clock is stopped. Subsequently, the clock switching output on the switching side is performed by the select valid signal obtained from the final latch stage by the operation of all the latch stages.

However, if one of the clock sources is not connected or the power is turned off, the clock input remains in the signal level and the clock switching operation to the clock source that is operating normally cannot be performed correctly. In addition, it is desired to enable clock switching in consideration of disconnection of a clock source and power supply stop.

[Prior Art] FIG. 7 shows a conventional clock switching circuit for dynamically switching between two clocks.

In FIG. 7, reference numerals 10-1 and 10-2 denote first and second latch parts corresponding to the first clock CLK1.
And a second synchronization circuit. The synchronization circuit 10-1 connects a master / slave FF24 composed of a master FF and a slave FF in five stages by means of a slave output.
Also connects the master / slave FF24 in three stages. The synchronization circuits 10-1 and 10-2 are connected via a NOR gate 26-1.

Reference numerals 10-3 and 10-4 denote third and fourth synchronization circuits provided corresponding to the second clock CLK2, which have the same circuit configuration as the clock CLK1 and are connected via the NAND gate 26-2. Have been.

A select signal for instructing the synchronization circuit 10-1 to switch to the clock CLK1 or CLK2 via the NOR gate 28-1
SEL is input. More specifically, the inversion of the select signal SEL from 1 to 0 instructs switching to the clock CLK1, and the inversion from 0 to 1 instructs switching to the clock CLK2.
The NOR gate 28- is connected to the synchronization circuit 10-3 on the clock CLK2 side.
1 is supplied through NOR gate 28-2.

Here, when the select signal SEL is 0, the NOR gates 28-1 and 28
The output of -2 (latch input) is defined as a select valid signal, and the output at 1 is defined as a select invalid signal.

The reset signal RES for the NOR gates 28-1 and 28-2
Is used to inhibit the operation of the synchronization circuit in the transient state at the time of power-on start of the device.

A total of eight stages of master / slave FF24 provided in the first and second synchronization circuits 10-1 and 10-2 are driven by clock inversion output from a skew driver 30-1 using an inverter. Similarly, the third and fourth synchronization circuits 10-3, 10-3
The master / slave FF24 having a total of eight stages provided in -4 is driven by a clock inversion output from a skew driver 30-2 using an inverter.

Following the synchronization circuits 10-2, 10-4, NOR gates 34-1, 3-4
A clock switching circuit composed of 4-2, 36 is provided, and the master / slave FF of the final group obtained by an eight-stage latch operation using a clock from the time of input (change) of the select signal SEL.
One of the NOR gates 34-1 and 34-2 is allowed and the other is disabled by the 24 slave inverted outputs, and the clock CLK1 or CLK2 is output from the NOR gate 36 to a circuit unit such as a CPU and a memory.

FIG. 8 shows an operation timing chart when switching from the clock CLK2 to CLK1 in FIG.

Now, at time t1, the select signal SEL changes from 1 to 0,
A select valid signal, which is output 1 from the NOR gate 28-1, is applied to the synchronization circuit 10-1.
A select invalidation signal which becomes the output 0 inverted by the R gate 28-2 is added at the same time. The synchronization circuits 10-1 and 10-
The NOR gate 26-1 connecting the two is enabled at the output 0 of the NOR gate 28-2, and thus operates as an eight-stage latch circuit. On the other hand, the NOR gate 26-2 is disabled by the output 1 of the NOR gate 28-1, and the output of the NOR gate 26-2 is at the 0 level indicating the select invalid signal. -4 are separated and the select invalid signal is latched in parallel.

The synchronization circuits 10-1 and 10-2 on the switching side sequentially latch the select valid signal obtained at time t1 and output the slave output of the master / slave FF24 as shown in the synchronization latch output of FIG. From 1 to 0. Master / slave of the last stage by 8 latch operations
Slave inverted output as latch output of FF24 is 1 to 0
, The NOR gate 34-1 enters the allowable state, and the clock CLK1 is output via the NOR gates 34-1 and 36.
That is, the switching to the clock CLK1 is performed in synchronization with the trailing edge (rising) of the clock CLK1, and the master input is guaranteed during the half cycle of the clock before the switching, so that no abnormality such as a hazard occurs.

On the other hand, the clock CLK2 side becomes the fourth
The slave inverted output of the master / slave FF24 at the final stage of the synchronization circuit 10-4 changes from 0 to 1 up to that time, and the NOR
The gate 34-2 is set in the prohibited state, and the output of the clock CLK2 is already prohibited. Therefore, it is possible to perform dynamic clock switching from the output state of the clock CLK2 to the output of the clock CLK1 through the stop state of both clocks.

[Problems to be Solved by the Invention] However, in such a conventional clock switching circuit, when two clock sources are normally connected and clock oscillation is performed by receiving power supply together, 2. It is possible to dynamically switch between two clocks, but if one of the clock sources is not connected, or if the power is not supplied normally even if the clock source is connected,
For example, even if an attempt is made to switch to a clock from a normal clock source at power-on start, there has been a problem that a correct clock switching operation cannot be performed.

That is, when the clock source is not connected or the power supply is cut off, the signal level of the clock input line to the clock switching circuit becomes level 0 because the clock polarity is negative and the terminating resistor is connected, and the clock is input. This causes a problem that the clock switching operation cannot be performed correctly.

For example, if the clock source of the clock CLK1 is not connected, the clock CL for the clock switching circuit of FIG.
All input lines of K1 are fixed at the signal level 0, the NOR gate 34-1 on the CLK1 side is placed in an allowable state, the slave inverted output 1 of the last stage is output as it is, and the switching operation to the CLK2 side is performed correctly. However, even if the output 1 on the CLK1 side is fixed and the CLK2 is masked, a correct switching state of the clock CLK2 cannot be obtained.

The present invention has been made in view of such a conventional problem, and it is possible to switch to a clock output from a normal clock source even if one of the clock sources is not connected or power is not supplied. It is an object of the present invention to provide a clock switching circuit capable of performing the following.

[Means for Solving the Problems] FIG. 1 is an explanatory view of the principle of the present invention.

First, the present invention is directed to a clock switching circuit that dynamically switches between two clocks CLK1 and CLK2.

Such a clock switching circuit comprises first and second multi-stage latches using a master / slave FF divided into a front stage and a rear stage for synchronizing two clocks when switching to the first clock CLK1. And a multi-stage latch using the same master / slave FF divided into a front stage and a rear stage for synchronizing the two clocks when switching to the second clock CLK2. And third and fourth synchronization means 10-3 and 10-4.

The latch structure of the first and second synchronization means 10-1 and 10-2 and the third and fourth synchronization means 10-3 and 10-4 is a selection means.
Determined by 12. That is, the selection means 12 is connected to the first synchronization means 10-1 and the second synchronization means 10 at the time of switching to the first clock CLK1.
A third synchronization means connected in series with the synchronization means 10-2;
10-3 and the fourth synchronizing means 10-4 are separated, a select valid signal is applied to the first synchronizing means 10-1, and the third and fourth synchronizing means 10-3 and 10-4 are applied. Input select invalid signal. On the other hand, at the time of switching to the second clock CLK2, the selecting means 12 comprises the third synchronizing means 10-3 and the fourth synchronizing means.
10-4 are connected in series, the first synchronization means 10-1 and the second synchronization means 10-2 are separated, and the third synchronization means 10-3 is connected.
And a select invalid signal is input to the first and second synchronization means 10-1 and 10-2.

The latch operation of the synchronization means 10-1 and 10-2 is the first clock
A narrow chop pulse synchronized with the trailing edge of CLK1 is generated and performed by the first chop means 14-1. The latch operation of the third and fourth synchronization means 10-3 and 10-4 is performed by generating a chop pulse having a narrow pulse width synchronized with the trailing edge of the second clock CLK2 by the second chop means 14-2. .

The chop pulse generated by the first chopping means 14-1 is applied to each of the latches except for the respective latch stages of the first synchronizing means 10-1 and the last latch stage of the second synchronizing means 10-2 by the first driver means 16-1. The selection is supplied to the stage, and the select valid signal or the select invalid signal is sequentially latched.

Similarly, the chop pulse generated by the second chopping means 14-2 is supplied to the third synchronizing circuit 10 by the second driver means 16-2.
-3 and the last latch stage of the fourth synchronizing means 10-4 are supplied to the respective latch stages to sequentially latch the select valid signal or the select invalid signal.

Further, the first mismatch detecting means 18- detects the mismatch between the input of the final latch stage of the second synchronizing means 10-2 and the slave output.
1 and the second mismatch detecting means 18- which detects a mismatch between the input of the last latch stage of the fourth synchronizing means 10-4 and the slave output.
2 are provided.

When a mismatch detection output is obtained from the first mismatch detecting means 18-1, the first gate means 20-1 operates, and the chop clock of the first chopping means 14-1 is synchronized with the second synchronizing means 10-2.
To the final latch stage. Second mismatch detecting means 18
-2, when a mismatch detection output is obtained from the second gate means,
18-2 operates to supply the chop clock of the second chopping means 14-2 to the final latch stage of the fourth synchronizing means 10-4.

The first gate switching means 22-2 is operated by the master latch output of the select valid signal synchronized with the trailing edge of the clock output from the last latch stage of the second synchronization means 10-2 by the latch operation by the chop clock by the first gate means 20-1. 1 allows the switching output of the first clock CLK1, and inhibits the switching output of the first clock CLK1 by the master latch output of the select invalid signal. In addition, the chopping clock supplied by the second gate means 20-2 supplies the master latch output of the select valid signal synchronized with the trailing edge of the clock output from the last latch stage of the fourth synchronizing means 10-4.
-2 permits the switching output of the second clock CLK2, and inhibits the switching output of the second clock CLK2 by the master latch output of the select invalidation signal.

Here, the first and second chopping means 14-1 and 14-2 include a clock inverting circuit, a delay circuit for delaying the output of the inverting circuit over a chop pulse width, the delay circuit and the clock inverting circuit. And an OR circuit for extracting the logical sum of

The first and second synchronization means 10-1, 10-2 and the third
The fourth synchronizing means 10-3 and 10-4 finally generate a latch output by the input of chop pulses for all the latch stages when the select valid signal is input, and are located at the subsequent stage when the select invalid signal is input. Second and fourth synchronization means 10-2,10
A latch output is generated by the input of chop pulses corresponding to the number of latch stages of -4, and clock switching is performed through a stop period of both clocks after application of the select signal.

Further, an exclusive OR circuit is used as the first and second mismatch detecting circuits 18-1 and 18-2.

[Operation] According to the clock switching circuit of the present invention having such a configuration, when the clock source is not connected, the chop pulse for latch driving generated from the clock is fixed to the stop state, thereby creating the same state as the clock stop. Clock switching from a normal clock source.

If power is not supplied to the clock source, the switching operation is fixed to the disabled state by the clock input to the circuit that switches the clock by the latch output of the synchronization circuit, and the clock switching from the normal clock source is performed. Do not disturb the output.

[Embodiment] FIG. 2 is an embodiment configuration diagram showing one embodiment of the clock switching circuit of the present invention.

In FIG. 2, reference numerals 10-1 and 10-2 denote first and second synchronization circuits provided for switching to the CLK1 side. The synchronization circuit 10-1 located at the preceding stage constitutes a five-stage latch circuit in which the master / slave FF24 is sequentially connected by the slave output. As is well known, the master / slave FF 24 is composed of a preceding master FF section 24a and a succeeding slave FF section 24b, takes in an input to the master FF section 24a at a leading edge of a clock, generates a master latch output, and generates a master latch output at a trailing edge of the clock. The output of the master FF unit 24a is transferred to the slave FF unit 24b to generate a slave output. The output of the last master / slave FF of the first synchronization circuit 10-1 is a slave inverted output.

The second synchronization circuit 10-2 has a four-stage latch configuration in which a one-stage latch circuit is added to a conventional three-stage latch configuration by connecting slave outputs.
Is output to the clock switching circuit 22 which will be described later.

On the other hand, for the second clock CLK2 side, the first clock
A five-stage third synchronization circuit 10-3 in which the slave outputs of the master / slave FF24 are connected similarly to the CLK1 side,
A fourth synchronizing circuit 10-4 having a four-stage latch configuration in which one stage is added to the stage latch configuration is provided.

The first synchronizing circuit 10-1 and the second synchronizing circuit 10-2 separated into the pre-stage latch unit and the post-stage latch unit include a NOR gate 26-1.
And the third synchronization circuit 10-3 and the fourth synchronization circuit 10-4 are also connected via a NOR gate 26-2. The circuit part 12- composed of the NOR gates 26-1 and 26-2
2 constitutes a part of the select circuit which will be clarified later.

The select signal c (SEL) is supplied to the first synchronization circuit 10-1 on the clock CLK1 side via the NOR gate 28-1 provided in the select circuit 12-1. When the select signal c changes from 1 to 0, the clock CLK2 changes to CL.
A command is issued to switch to K1, and when it changes from 0 to 1, a command is issued to switch from clock CLK1 to CLK2. In addition, NOR
A power-on reset signal is applied to the other input of the gate 28-1. The power-on reset signal is effective only for a certain period of time from when the power of the device is turned on until the device is stabilized, and is fixed to 0 at the time of switching. -1 indicates an allowable state.

Here, the select signal c changes to 0 and the NOR gate 28
The latch input when the output of -1 becomes 1 becomes a select valid signal, and the latch input when the select signal c becomes 1 and the output of the NOR gate 28-1 becomes 0 becomes a select invalid signal. Define.

The output of the NOR gate 28-1 is further provided as a latch input to the third synchronization circuit 10-3 on the second clock CLK2 side via the NOR gate 28-2. For this reason, if the latch input to the first synchronization circuit 10-1 on the first clock CLK1 side is a select valid signal, the third input on the second clock CLK2 side
The latch input to the synchronization circuit 10-3 is always a select invalid signal.

NOR gates 26-1 and 26-2 provided in a circuit section forming part 12-2 of the select circuit control the connection state between the preceding and succeeding stages of the synchronization circuit section depending on the state of the select signal c. For example, when the select signal c changes from 1 to 0 in order to instruct switching on the first clock CLK1 side, the NOR gate 26
-1 is given an output 0 from the NOR gate 28-2 to be in an allowable state, and accordingly, the first synchronization circuit 10-1 and the second synchronization circuit 10-2 receiving the latch input of the select valid signal.
To perform a total of nine stages of latch operation.

On the other hand, the output 1 is given from the NOR gate 28-1 to the NOR gate 26-2, and the NOR gate 26-2 is placed in the prohibited state, and the third synchronization circuit 10-3 and the fourth synchronization circuit 10-4 are electrically connected. To separate.
Fourth synchronization circuit 10- separated by NOR gate 26-2
Since the output of the NOR gate 26-2 placed in the inhibited state is 0, the side 4 is placed in the latch input state of the select invalid signal as in the case of the third synchronization circuit 10-3 in the preceding stage, and is therefore separated. Third and fourth synchronization circuits 10-3 and 10
-4 performs the latch operation of the select invalid signal in parallel.

The latch stages except the last stage of the first synchronization circuit 10-1 and the second synchronization circuit 10-2 are driven by the chop pulse from the chop circuit 14-1. The chop circuit 14-1 inverts the first clock CLK1 by the inverter 38, inputs the inverted clock to the delay circuit 40 using a monostable multivibrator or the like, and takes out the OR of the output of the delay circuit 40 and the inverter 38 by the OR gate 42. .

Specifically, as shown by the clock a, inverted clock, and chop pulse b in the main part timing chart of FIG. 3, the clock a (CLK1) is synchronized with the trailing edge of the inverted clock, which is the falling edge of the inverted clock. Thus, a chop pulse b having a narrow pulse width is created.

A similar chop circuit 14-2 is provided on the second clock circuit CLK2 side, and the chop circuit 14-2 includes an inverter 38, a delay circuit 40, and an OR gate 42.

The chop pulse generated by the chop circuit 14-1 is transmitted to all the master / slave FFs 24 of the first synchronization circuit 10-1 via the inverter 16-1 operating as a skew driver.
And a clock for a latch operation to all master / slave FF24 except the last stage of the second synchronization circuit 10-2.

Similarly, on the second clock CLK2 side, the chop circuit
The third synchronizing circuit 10- through the inverter 30-2 which operates the chop pulse from 14-2 as a skew driver.
All master / slave FF24 and fourth synchronization circuit 10
A clock for latch operation is supplied to all master / slave FF24 except for the last stage of -4.

For the master / slave FF24 at the last stage of the second synchronization circuit 10-2 and the fourth synchronization circuit 10-4, an EX-NOR gate 18 as a mismatch detection circuit for detecting a mismatch between a master input and a slave output. -1, 18-2 are provided. That is, EX
−NOR gates 18-1 and 18-2 are the last master / slave F
When the master input and the slave output of F24 match, an output 1 is generated. However, due to the progress of the latch operation of the select valid signal or the select invalid signal, the latch output of the eighth stage is obtained, Until the ninth-stage latch output is obtained, the values do not match.
The NOR gates 18-1 and 18-2 invert the previous output 1 to 0 to generate a mismatch detection output.

The output of the EX-NOR gate 18-1 as a non-coincidence detection circuit is input to one of the NOR gates 20-1 operating as chop gates. -1 is allowed, and a chop pulse is output from the chop circuit 14-1 to the master / slave FF24 at the final stage to perform a latch operation.

This point is the fourth synchronization circuit 10-4 on the second clock CLK2 side.
EX-NO provided in the last master / slave FF24
The same applies to the R gate 18-2, and the EX-NOR gate 18
NOR gate 20-2 using the output of -2 as a chop gate
When a non-coincidence detection output, which becomes output 0, is obtained, the NOR gate 20-2 is allowed and the chop circuit 1
The chopping pulse from 4-2 is supplied to the master / slave FF24 at the last stage to perform a latch operation.

A clock switching circuit 22 is provided following the second synchronization circuit 10-2 and the fourth synchronization circuit 10-4, and the clock switching circuit 22 is a NOR gate 34-1 that selects the first clock CLK1.
And a NOR gate 34-2 for selecting the second clock CLK2;
A NOR gate 36 is provided to collectively output the outputs of the OR gates 34-1 and 34-2 to a circuit unit such as a CPU or a memory.

The inverted master output of the master FF24a of the last-stage master / slave FF24 of the second synchronization circuit 10-2 is applied to the NOR gate 34-1 for switching and selecting the first clock CLK1.
−NOR gate 20− when mismatch is detected by NOR gate 18-1
Fall of the chop pulse received from 1, ie, clock
The master inversion output 0 is generated by the latch operation by taking in the ninth latch output synchronized with the trailing edge of CLK1. This master inversion output 0 puts the NOR gate 34-1 in an allowable state,
After the first clock CLK1 is inverted by the NOR gate 34-1 and further inverted by the NOR gate 36 and returned to the original state, the first clock CLK1 is output to a circuit unit such as a CPU or a memory.

Here, the master at the last stage of the second synchronization circuit unit 10-2
The master inverted output of the FF unit 24a becomes the output 0 when the latch operation of the select valid signal for switching to the clock CLK1 side is performed, and at this time, the synchronization circuit 10 on the clock CLK2 side is used. For -3 and 10-4, since the select invalid signal is latched, EX-NO
The R gate 18-2 detects a mismatch, and the chopping pulse from the NOR gate 20-2 latches the last master / slave FF24, that is, the inverted master output when the first master FF unit 24a latches. Has switched from output 0 to output 1 so far, NOR gate 34-2 has been placed in an inhibit state, its output is fixed at 0, and therefore NOR gate 36 is placed in an allowed state, and NOR gate 3 First from 34-1
The clock CLK can be effectively taken out as a switching output without being hindered by the second clock CLK2.

As to the disconnection side, the second and fourth synchronization circuits 10-2 and 10-4 at the subsequent stage will be described later, as will be apparent from the operation description.
In the latch operation of the number of latch stages, the state shifts to the clock stop state before the clock switching.

FIG. 4 shows a second clock CLK2 in the embodiment of FIG.
6 is an operation timing chart showing an operation when switching from the state of switching output to the output of the first clock CLK1.

In FIG. 4, the select signal c is changed from 1 to 0 at time t1.
, The latch input to the first synchronizing circuit 10-1 becomes a select valid signal, and the first and second synchronizing circuits 10-1 and 10-2 are connected according to the permissible state of the NOR gate 26-1. Therefore, the latch operation is possible in nine stages.

At the same time, the latch input to the third synchronizing circuit 10-3 becomes a select invalid signal, and since the NOR gate 26-2 is in the inhibited state, the fourth synchronizing circuit 10-4 is disconnected and the latch input is similarly invalidated. Signal, and is in a state in which the latch operation of the select invalid signal can be performed in parallel.

When the select signal changes from 1 to 0 at time t1, time
After the time t1, the first synchronizing circuit is synchronized with the leading edge of the chop pulse obtained from the chop circuit 14-1, that is, the falling edge.
The latch operation of the master FF unit 24a in the first-stage master / slave FF 24 in 10-1 is performed, and then the transfer to the slave FF unit 24b is performed at the trailing edge of the same chop pulse, that is, at the rising edge. The latch output d of the stage rises from 0 to 1. Similarly, every time a chop pulse is obtained, the master FF section 24a and the slave F
The latch operation of the F section 24b is alternately repeated, and the latch outputs e to
The latch output changes from 1 to 0 as shown in g. First
Since the output h of the final stage (fifth stage) of the synchronization circuit 10-1 is a slave inverted output, the latch output h changes from 1 to 0 conversely. For this reason, the inputs of the NOR gate 26-1 both become 0, the output i of the NOR gate 26-1 rises from 0 to 1, and the latch input to the second synchronization circuit 10-2 is used as the select valid signal. For the first, second, and third stages of the second synchronization circuit 10-2, the latch outputs j to j in FIG.
As shown in FIG. 1, the trailing edge (rising) of the chop pulse b
Changes from 0 to 1 to obtain a latch output.

Then, at time t3, when the slave output 1 from the eighth master / slave FF24 changes from 0 to 1, the slave output m of the ninth master / slave FF24, which is the final stage at this time, is as shown in FIG. As is clear from the main part timing chart, the output 1 is in the state, and therefore, the EX-NOR gate 1
8-1 detects an input / output mismatch and produces an output 0, and puts the NOR gate 20-1 in an allowable state. NOR gate 2 on mismatch detection
When a new chop pulse b is obtained at time t4 after 0-1 becomes the allowable state, the last master / slave FF
The master FF unit 24a in 24 performs a latch operation at the leading edge of the chop pulse b, and generates a master inverted output = 0 as an inverted latch output for a latch input 1. Subsequently, when the trailing edge of the chop pulse comes at time t5, the slave FF unit 24b
Is performed, the slave output m changes from 0 to 1, whereby the two inputs of the EX-NOR gate 18-1 return to the same state again, and the coincidence output of the EX-NOR gate 18-1 causes The permission state of the NOR gate 20-1 is released,
After that, the master / slave at the last stage of the second synchronization circuit
The supply of the chop pulse to FF24 is stopped. At the timing of time t4 when the master inverted output changes from 1 to 0, the NOR gate 34-1 of the clock switching circuit 22 enters the permissible state, and the switching output of the first clock CLK1 becomes effective via the NOR gates 34-1 to 36. Done. That is, the first clock CLK1
Starts output in synchronization with the trailing edge of the first clock CLK1.

On the other hand, on the clock CLK2 side which is the disconnection side, as shown by the latch outputs o to y of the third synchronization circuit and the fourth synchronization circuit in the timing chart of FIG. 4, if the clock CLK2 is completely synchronized with the first clock CLK1. If the second clock CLK2 is obtained, the third synchronization circuit 10-3 and the fourth
The synchronization circuit 10-4 sequentially latches the select invalid signal as the latch input in parallel in synchronization with the chop pulse from the chop circuit 14-2. As a result, first, the fourth synchronizing circuit 10-4 changes the latch output w from 1 to 0 by the latch operation by the third chop pulse.
When the input of the R gate 18-2 becomes non-coincidence, the non-coincidence detection output 0 is output to the NOR gate 20-2 to be in an allowable state, and the fourth synchronization circuit 10 is output at the timing of the leading edge (fall) of the next chop pulse. The latch operation of the master FF section 24a of the master-slave FF 24 at the final stage of -4 is performed, and the inverted master output changes from 0 to 1 so that the NOR gate 34 of the clock switching circuit 22 becomes active.
Is prohibited, and as a result, a stopped state of the second clock CLK2 output from time t2 until that time is created. That is, from time t2, both outputs of the two clocks CLK1 and CLK2 are stopped.

On the other hand, in the third synchronization circuit 10-3, the latch output s of the final stage, that is, the slave inverted output, changes from 0 to 1 after time t2 through five latch operations by the chop pulse, and the initial state before the switching is restored. Recover.

Next, in the embodiment of FIG.
The operation when the clock source of CLK1 is not connected will be described.

FIG. 5 shows a signal state of the chop circuit 14-1 when the clock source of the first clock CLK1 is not connected. That is, the input to the inverter 38 becomes 0 and the output of the inverter 38 is inverted to 1 due to the disconnection of the clock source, and as a result, the outputs of both the delay circuit 40 and the inverter 38 become 1
The output of the OR gate 42 is fixed at 1. The state of the output 1 of the OR gate 42 is the same as the stopped state in which the clock CLK1 is turned off. Therefore, for example, if the select signal is set to 1 by a power-on reset and the switching to the clock CLK2 is commanded, the operation on the clock CLK1 is prohibited by fixing the chop pulse to the clock off, and the second clock CLK2
The circuit section on the side operates effectively, and the switching state to the clock CLK2 can be created correctly.

FIG. 6 is an explanatory diagram showing a signal state of the clock switching circuit unit 22 when the power supply to the clock source of the clock CLK1 in FIG. 2 is cut off.

NOR gate 3 by stopping power supply to clock source
The input line of the clock CLK1 for 4-1 is fixed to level 1 by a pull-up resistor to the power supply, and the NOR gate 34
Since -1 is placed in the disabled state, its output is always 0, and the normal clock CLK2 from the NOR gate 36 is effectively output without disturbing the clock CLK2 from the normal NOR gate 34-2.
Can be output.

[Effects of the Invention] As described above, according to the present invention, two clocks oscillated from a clock oscillation source are dynamically switched while a clock source is normally connected and a power supply is connected. At the same time, if one clock source is unconnected or the power is not supplied even if it is connected, the clock can be effectively switched to the clock from the normal clock source, and the clock can be duplicated. Can greatly improve the reliability of the device.

[Brief description of the drawings]

FIG. 1 is a view for explaining the principle of the present invention; FIG. 2 is a block diagram of an embodiment of the present invention; FIG. 3 is a timing chart of main parts of the present invention; FIG. 4 is an operation timing chart of the present invention; FIG. 6 is an explanatory diagram of a chop circuit signal state of the present invention when the power source is not connected; FIG. 6 is an explanatory view of a clock switching circuit signal state when the clock source power supply is stopped; FIG. 7 is a configuration diagram of a conventional circuit; 6 is an operation timing chart of FIG. In the figure, 10-1: first synchronization means (circuit) 10-2: second synchronization means (circuit) 10-3: third synchronization means (circuit) 10-4: fourth synchronization means (circuit) 12: Select means 12-1, 12-2: Select circuit section 14-1: First chop means (circuit) 14-2: Second chop means (circuit) 16-1: First driver means (skew driver) 16-2: Second drive means (skew driver) 18-1: First mismatch detecting means (EX-NOR gate) 18-2: Second mismatch detecting means (EX-NOR gate) 20-1: First gate means (NOR gate) 20-2: Second gate means (NOR gate) 22-1: First clock switching circuit (NOR gate) 22-2: Second clock switching circuit (NOR gate) 22: Clock switching circuit 24: Master・ Slave FF 24a: Master FF section 24b: Slave FF section

Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 1/04-1/14

Claims (4)

(57) [Claims] A clock switching circuit for dynamically switching between two clocks (CLK1, CLK2) is divided into a former stage and a latter stage for synchronizing clocks when switching to a first clock (CLK1). Master / slave FF
First and second synchronizing means (10-1, 10-2) comprising multi-stage latches; and a first stage and a second stage for synchronizing clocks when switching to the second clock (CLK2). Master / slave FF separated
Third and fourth synchronizing means (10-3, 10-4) composed of multi-stage latches using the first synchronizing means (10-1) when switching to the first clock (CLK1). The second synchronizing means (10-2) is connected in series, and the third synchronizing means (10-3) and the fourth synchronizing means (10-4) are separated from each other.
-1), a select invalid signal is applied to the third and fourth synchronizing means (10-3, 10-4), and a select invalid signal is input to the third and fourth synchronizing means (10-3, 10-4). The third synchronization means (10-3) and the fourth synchronization means (10-4) are connected in series, and the first synchronization means (10-1) and the second synchronization means (10-2) are connected. And a select valid signal is applied to the third synchronization means (10-3), and the first and second synchronization means (10-1, 10-
Select means (12) for inputting a select invalid signal to 2)
And a first chop means (14) for generating a chop clock having a narrow pulse width synchronized with the trailing edge of the first clock (CLK1).
-1); a second chop means (14) for generating a chop clock having a narrow pulse width synchronized with the trailing edge of the second clock (CLK2)
-2); the chopping clock of the first chopping means (14-1) is set to each of the latch stages of the first synchronizing means (10-1) and the second chopping means.
A first driver means (16-1) for supplying to each latch stage except a final latch stage of the synchronization means (10-2) to sequentially latch a select valid signal or a select invalid signal; and the second chop means (14) -2) the chop clock is supplied to each latch stage of the third synchronization circuit (10-3) and the fourth synchronization circuit (10-3).
Second driver means (16-1) for supplying to each latch stage except the last latch stage of the synchronization means (10-4) to sequentially latch the select valid signal or the select invalid signal; and the second synchronization means ( (18-1) first mismatch detecting means for detecting a mismatch between the master input and the slave output of the last latch stage of (10-2); and the master input of the last latch stage of the fourth synchronizing means (10-4). And a second mismatch detecting means for detecting a mismatch between the slave output and the slave output; and (18-2); when the mismatch detecting output of the first mismatch detecting means (18-1) is obtained, the first chopping means (14- (20-1) first gate means for supplying the chop clock of (1) to the final latch stage of the second synchronization means (10-2); and mismatch detection of the second mismatch detection means (18-2) When the output is obtained, the second chop means (14-2) (20-2) second gate means for supplying a chop clock to the final latch stage of the fourth synchronizing means (10-4); and supply of the chop clock by the first gate means (20-1). The switching output of the first clock (CLK1) is allowed by the master latch output of the select valid signal synchronized with the trailing edge of the clock output from the final latch stage of the second synchronization means (10-2), and the master latch output of the select invalid signal Prohibits switching output of the first clock (CLK1)
Clock switching means (22-1); synchronized with the trailing edge of the clock output from the final latch stage of the fourth synchronization means (10-4) by the supply of a chop clock by the second gate means (20-2). The first latch that allows the switching output of the second clock (CLK2) by the master latch output of the selected valid signal, and inhibits the switching output of the second clock (CLK2) by the master latch output of the select invalid signal.
And a clock switching means (22-2). 2. The first and second chop means (14-1, 14).
-2) a clock inverting circuit, a delay circuit for delaying an output of the inverting circuit over a chop pulse width, and an OR circuit for extracting a logical sum of the delay circuit and the clock inverting circuit The clock switching circuit according to claim 1, wherein: 3. The first and second synchronization means (10-1, 10-
2) and third and fourth synchronization means (10-3, 10-4)
When a select valid signal is input, a latch output is generated at the final stage by input of chop clocks for all latch stages, and when a select invalid signal is input, the second and fourth synchronizing means (10-2, 10 4. The clock switching circuit according to claim 1, wherein a latch output is generated by the input of chop clocks corresponding to the number of latch stages of (4), and clock switching is performed through a stop period of both clocks after application of the select signal. 4. The first and second mismatch detecting circuits 18-1, 18
2. The clock switching circuit according to claim 1, wherein an exclusive OR circuit is used as -2).