JPS628052B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention proposes a high-precision, high-bit D/A (digital/analog) converter.

Various types of D/A converters have been put into practical use, but those for high-speed data generally have a configuration in which the accuracy of the single resistor that makes up the circuit has a large effect on the accuracy of the D/A converter itself. Therefore, in order to improve this, high-precision resistors are essential and expensive.

The present invention has been made in view of the above circumstances, and its purpose is to provide high-speed data D/
It is an object of the present invention to provide a high-precision, high-bit D/A converter that is capable of A conversion, is less affected by variations in characteristics of constituent elements, particularly resistors, and has less deterioration in accuracy due to temperature changes.

Another object of the present invention is to provide a D/A converter that uses IGFETs (insulated gate field effect transistors), can be integrated with high precision, is easy to manufacture, is highly reliable, and is inexpensive. is to provide.

Still another object of the present invention is to provide a D/A converter suitable for applications in digital processing and reproduction of signals with a wide dynamic range, such as speech synthesis.

The present invention will be explained in detail below based on the drawings.

FIG. 1 is a block diagram showing the basic configuration of a D/A converter according to the present invention. This D/A converter is a first D/A converter that converts the upper M bits of N-bit binary digital data into analog data.
It consists of an A conversion circuit 1 and a second D/A conversion circuit 2 that converts lower (N-M) bits into analog data.

First, the first D/A conversion circuit 1 will be explained. This D/A conversion circuit 1 includes a decoder 11, a voltage dividing circuit 1,
2 and a switching circuit 13. The voltage divider circuit 12 consists of 2 ^M equal resistors connected in series.
Both ends are connected to the fixed potential V _REF and the substrate potential V _E , respectively, which are to be used as reference potentials, and the divided voltage output terminals drawn out from both ends of each resistor are connected to the switching circuit 1.
It is connected to 3. The decoder 11 to which M-bit data is input issues a signal according to the input content to the switching circuit 13, and switches the two potentials V ₁ and V ₂ corresponding to the M-bit data input to the decoder 11 to the switching circuit 13. It is designed to be obtained from These potentials V ₁ and V ₂ are obtained by converting the upper M bit data of the N-bit data a ₀ , a ₁ ...a _N-1 from the lower side to a _NM , a _N-M+1 ... a _N-1 . , if the minimum output voltage step of the first D/A conversion circuit 11 is e _M , then V ₁ = (a _NM・2 ⁰ +a _N-M+1・2 ¹ +... +a _N-1・2 ^{M- 1} )・e _M …(1) V ₂ =V ₁ +e _M …(2) It is a potential expressed as, specifically, voltage divider circuit 1
Out of the ^2M resistors composing 2, the potential at both ends of the resistor selected corresponding to M bits of input data, that is, the potential at adjacent divided voltage output terminals, in other words, the potential at two adjacent potentials. be. In addition, e _M is below (3)
It is expressed by the formula.

e _M = (V _REF - V _E )/2 ^M ...(3) Output potential of such switching circuit 13
V ₁ and V ₂ are provided to the second D/A conversion circuit 2 as reference potentials.

Next, the second D/A conversion circuit 2 includes a (N-M) bit input matching circuit 21, clock oscillators 22, 2
It consists of an ^NM counter (counting circuit) 23, an R-S flip-flop 24, switch transistors 25 and 26 consisting of IGFETs, and a low-pass filter 27, and the output of the low-pass filter 27 is used as the output V _OUT of the D/A converter of the present invention. .

Now, from equation (2), V ₂ −V ₁ = e _M , so the minimum output voltage step e _N of the second D/A conversion circuit is e _N = e _M /2 ^NM , but equation (3) Substituting , it becomes e _N =(V _REF −V _E )/2 ^N (4). The lower (NM) bit data is a ₀ , a ₁
...a _NM-1 , then V _OUT = (a ₀・2 ⁰ +a ₁・2 ¹ +… +a _NM-1・2 ^NM-1 )e _N +V ₁ , which is expressed by equation (1) and (4). Substituting the formula, V _OUT = (a ₀・2 ⁰ +a ₁・2 ¹ +…+a _NM-1・2 ^NM-1 +a _NM・2 ^NM …a _N-1・2 ^N-1 )×(V _REF − V _E )/2 ^N (5), which is taken out as the analog output of the D/A converter according to the present invention.

Therefore, this second D/A conversion circuit 2 has (N−
M) switch transistors 25 whose on and off states are reversed depending on the contents of bit input data;
V _{1 of} the potential to be input to the low-pass filter 27 within a certain period of time by controlling the on/off of 26
This is a pulse width modulation type in which the selection time and _V2 selection time are changed according to the contents of input data. That is, the counter 23 counts the clocks generated by the clock oscillator 22, and each time the count becomes 0 (once for every ^NM clock input), it issues a signal V3 to reset the R-S flip-flop 24, and also outputs a signal _V3 to reset the R-S flip-flop 24. Match circuit 2
Output to 1. The match circuit 21 generates a signal _V4 to set the R-S flip-flop 24 when its two inputs, that is, the (N-M) bit input and the counted contents match. switch transistor 2
5 and 26 are turned on by the output ₅ and the Q output _V5 of the R-S flip-flop 24, respectively, so that the input signal _V6 of the low-pass filter 27 has _V1 and _V2 alternating, and _V2 ( or V ₁ ) becomes a signal determined by the contents of the N-M bit input data. The low-pass filter 27 then smoothes the pulsed signal _V6 .

FIG. 2 is a schematic circuit diagram showing a specific example of the configuration of a D/A converter according to the present invention. 14 in this example
Among the bit data A ₀ , A ₁ to A ₁₃ , the upper 8 bits of data A ₆ , A ₇ to A ₁₃ are transferred to the first D/A conversion circuit 1.
The data of the lower 6 bits is also sent to the decoder 11 of
A ₀ , A ₁ to _{A 5} are supplied to the coincidence circuit 21 of the second D/A conversion circuit 2 . The voltage dividing circuit 12 of the first D/A conversion circuit 1 is formed by connecting ²⁸ resistors 4 of equal value in series, and divides the voltage between V _REF and _VE to ²⁸ . Therefore, the voltage step (e _M ) between the divided voltage output terminals is (V _REF -V _E )/ ²⁸ .
The voltage dividing output terminals between the resistors 4 and the potential V _E terminal in the voltage dividing circuit 12 are connected to the drain of the switch transistor 25 via IGFETs 5, 5, . . . , respectively. Further, the divided voltage output terminal between the resistors 4 and the voltage V _REF terminal are connected to the drain of the switch transistor 26 via IGFETs 6, 6, . . . , respectively. The IGFETs 5, 5, 6, 6, and so on constitute the switching circuit 13, and each of the ²⁸ outputs of the decoder 11 is connected to the IGFET 6 connected to the V _REF side of each resistor 4, and the IGFET 5 connected to the V _E side. The IGFETs 6 and 5 are connected to these gates in such a way that they can be made conductive at the same time, and outputs V ₂ and V ₁ corresponding to the input upper 8 bits of data are obtained by the conduction of a pair of IGFETs 6 and 5, and these are turned on by a switch. The signal is applied to transistors 26 and 25, respectively.

The matching circuit 21 of the second D/A converter 2 receives 6-bit data A ₀ to A ₅ at 100 MHz.
A counter 2 of ²⁶ counts the clock oscillator 22 of
The 6-bit counter output of 3 is also input to the matching circuit 21. And as mentioned above, counter 2
The signal _V3 generated by the counter 23 each time the count of 3 becomes 0 is connected to the reset terminal R of the R-S flip-flop 24, and the coincidence signal V4 generated when the coincidence circuit 21 detects a coincidence between both inputs is connected to the R-S flip-flop ₂₄ . It is applied to the set terminal S of the S flip-flop 24, and the switch transistors 26 and 25 are turned on and off by the Q output V ₅ and the output ₅ of the R-S flip-flop 24, respectively. The sources of both transistors 26 and 25 collectively input a pulse width modulated signal V ₆ to a low-pass filter 27, and its output V _OUT
It is designed so that it can be taken out.

In the case of the D/A converter of the present invention configured as described above, the potentials V 1 and V 2 according to the upper 8 bits of input data A ₆ to A ₁₃ are as shown in equations ( ₁ ) and ( ₂ ) above. is the first
It is obtained from the D/A conversion circuit 1.

On the other hand, in the second D/A conversion circuit 2, the third
As shown in Figure A, a pulse of _V3 appears periodically (every time ²⁶ clocks are input to the counter 23), and the R-S flip-flop 24 is reset. As a result, the signal ₅ becomes high level as shown in FIG. 3D, the switch transistor 25 is turned on, and V ₆ =V ₁ as shown in FIG. 3E. Therefore, the count contents of the counter 23 are periodically updated to the coincidence circuit 2.
Since the input data _A0 to _{A5 are equal to the input data A0 to A5} , a pulse of _V4 appears at that timing, and the R-S flip-flop 24 is set. This allows the third
As shown in FIG. 3C, V ₅ becomes high level, the switch transistor 26 is turned on, and V ₆ =V ₂ as shown in FIG. 3E. Therefore, the output V _OUT of the low-pass filter 27 is as shown in _FIG .
The signal is smoothed to a level determined by the time at _V1 and the time at _V2 , and in short, analog signals corresponding to the input data _A0 to _A13 are obtained.

In the D/A converter of the present invention configured as described above, since the first D/A conversion circuit uses a resistive voltage division method, variations in the conduction resistance of the IGFET are directly affected by the D/A converter. Does not affect the accuracy of A conversion output.
Furthermore, even if the values of the resistors that make up the voltage divider circuit differ by 1%, V ₁ and V ₂ will only differ by 1% of the minimum step voltage, which in the case of the embodiment is only 0.004 of the value of V _REF - _VE . %.

As described above, according to the present invention, a high-bit D/A converter capable of high-speed data conversion with high precision and guaranteed monotonicity can be realized. Since an IGFET can be used as a switching element, it can be highly integrated, and even if there are variations in the conduction resistance of the IGFET or the values of the resistances that make up the voltage divider circuit, this has little effect on accuracy. Since there is no need for trimming to obtain high-precision resistors as in the past, manufacturing becomes easier.
It can be provided at a low price and has increased reliability. Since the D/A converter of the present invention guarantees monotonicity and is capable of D/A conversion of high-bit, high-speed data, it can be applied to digital processing of signals with a wide dynamic range and their reproduction. suitable for

Furthermore, in the present invention, a pulse width modulation type circuit is used as the second D/A conversion circuit. Although this type generally does not require high-precision parts and is suitable for stable high-bit D/A conversion, it has the drawback of slow conversion speed.
For example, even if a 100MHz high-speed counter is used, 14-bit D/A conversion requires 160μs to set the pulse width, and 2 to 5 times longer to obtain a flat output through a low-pass filter. do.
However, in the present invention, N-M bits out of N bits are subjected to D/A conversion by this conversion circuit, so high-speed use is possible by appropriate bit allocation. That is, when converting 6-bit data using a 100 MHz high-speed counter as in the embodiment, the pulse width setting is 640 ns, and a flat output can be obtained in about 3 μs even through a low-pass filter.

Furthermore, since the device of the present invention does not use an internal amplifier such as an operational amplifier, there is no need to adjust the offset voltage, and the present invention has excellent effects such as less deterioration in accuracy due to temperature changes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of a D/A converter according to the present invention, FIG. 2 is a schematic circuit diagram showing a specific example of the configuration, and FIGS. 3A to 3F are operation explanatory diagrams. 1, 2...D/A conversion circuit, 11...decoder, 12...voltage divider circuit, 13...switching circuit, 21...matching circuit, 22...clock oscillator, 23...counter, 24...R -S flip-flop, 25, 26... switch transistor, 27... low pass filter.

Claims (1)

[Claims] means for decoding the upper M bits of 1N bits of digital data; means for dividing the voltage between the first reference potential and the second reference potential using ^2M resistors; A first D/A conversion circuit equipped with a means for selectively taking out two adjacent potentials according to the output, a 2 ^NM counting circuit provided for data of lower (NM) bits, and the counting circuit. Based on the counting contents, one of the two potentials is selected for the period determined by the (NM) bit data of the 2 ^NM clock period, and the other potential is selected for the remaining clock period. A D/A converter comprising a second D/A converter circuit having means for combining the two selected potentials.