JPS6174418A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To prevent glitch by applying pulse width modulation by means of a D/A converting circuit to a low-order bit with a prescribed elapsed time after a digital data is inputted. CONSTITUTION:A converting circuit 1 decodes (11) a high-order M-bit of an N-bit digital data, a reference voltage (between Vref and VE) is divided (12) by 2M sets of resistors, close voltage V1, V2 are extracted and fed to switching transistors TRs25, 26 of a D/A converting circuit 2 for data in low-order (N-M)- bit. The circuit 2 selects one of the two voltages during a period decided by the data of (N-M)-bit in a clock period Tp of 2N<->M shorter than one D/A conversion period Tc and selects the other during the other clock period, both the two voltages V1, V2 are cut off during the remaining period Tc-Tp to cause the high impedance state. Then the voltages V1, V2 appear alternately in the synthesized voltage V14, which is smoothed by an LPF30 and outputted.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a high precision, high pitch D/A (digital/analog) converter, and is applicable to devices equipped with various D/A converters, such as Speech synthesizer and CD (compact disc)
It is used by players, etc.

(b) Conventional technology D/A converters of various types have been put into practical use.Generally, D/A converters are equipped with a decoding circuit for inputting digital data, but the bits of this decoding circuit are Glitches occur due to discrepancies in processing times between each process. For example, when digital data changes from 011...1 to 100...0, if the most significant bit is decoded earliest, it will temporarily become 111...1, and the analog output will be A spike-like noise appears. This noise is a glitch.

Furthermore, there are some types of D/A converters, such as integral type D/A converters, that require a predetermined period of time until the converted output becomes stable.

For the above reasons, generally a sample hold circuit is provided at the subsequent stage of the D/A converter circuit to stabilize the output of the D/A converter circuit and perform sampling at the running point. That is, as shown in FIG. 3, the output of the D/A conversion circuit (4I) is applied to the sampling and hold circuit (43) via a switch (42) that is closed after the circuit output is stabilized. This sampling hold circuit (0) which has an operational amplifier (45) applies its output to the low bass filter control and outputs analog data to the output terminal (47).

Here, if the D/A converter circuit (Inc.) is highly accurate, the constituent elements of the sampling and hold circuit (43) that receives the output thereof must also be constructed with highly accurate elements, which is disadvantageous in that it is small and expensive. .

Japanese Unexamined Patent Publication No. 57-26621 has a D/A as shown in Fig. 4.
A converter is introduced. Although this method does not require an expensive sampling and holding circuit, it may cause the errors described below and has the disadvantage that the glitch described above is unavoidable. This conventional D/A converter includes a first D/A converter circuit (51) that inputs the upper M bits of N-bit digital data, and a first D/A converter circuit (51) that inputs the lower (N-M) bits of digital data. A second input circuit inputs the output of the A conversion circuit l51).
It is equipped with a D/A conversion circuit. The M-bit digital data is decoded by a decoding means, and the decoded signal is input to the switch circuit shaft. This switch circuit selectively outputs two nearby potentials according to the decoded signal from among the means $ for dividing the voltage between the first reference potential Vref and the second reference potential Vg using seven resistors.

Therefore, these two adjacent potentials vl, v2 (vl) vl) are s bi,
This schematically represents a region where an analog quantity corresponding to 7tco+'di## exists.

The second D/A conversion circuit [Co., Ltd.] specifies the above-mentioned adjacent 2% range more precisely based on the digital data of the lower (N-M) bits.
-M counting circuit (branch) and coincidence circuit 5 that checks the coincidence between (N-M) bits of digital data and the counting circuit (branch) output.
, the R-8 flip-flop ■, which is set by the power of this matching circuit and reset by the output from the counting circuit, and this R-B
-Y The flip-flop includes two gate circuits (61) that selectively output the two adjacent potentials at the output, and a low-pass filter that inputs the combined output of both gate circuits.

In this conventional D/A converter, the period at which one N-bit digital data is input (one D/A conversion period, Ta) is often asynchronous with the period Tf of the clock oscillation circuit. , T c = I × 2N-'X T f ...
- (6) I: It is difficult to make it a natural number. Therefore, usually Tc is lX2
Select Tf to be greater than N-'XTf.

Synthetic output of gate circuit [11 (61) ■6 always has Vt
Or, since vl is output, (T c − engineering
During the period (excess period) (N-M×Tf), the potential of vl or Vt is output to the output terminal -, resulting in an error l.

Digital data is sequentially ao, al, etc. starting from the lower bit.
, aN-1, Vout is generally Vou *=
(a O-2+a l ・2￥・+aN-1-j'-'
)%(vref-VE)/ε=VX+t...
...It can be expressed as (7).

For example, if the high voltage side potential v2 of two potentials close to the period (To-IX xTf) is output to the output terminal (2), then t=(Vt-Vz)xt Tc-Ix2' -MxT f
)/Tc, , (B). Here, N = 16 (bits), M = 8 (pips)), I = 1 (pulse width modulation 4 times), TO: (2N - “+4) x Tf < 4
(Vt is output to the output terminal as xTf period error), the lower (N L - M ) bit data is set as aO=1, a1~
If aN-M-1=Q, then Vt-VX = (i-1) cut V ref V x )/
2Nε=255X4/260X(Vref-VE)/2
592 (Vref-VE)/2N -- (91. D/A converter) 1L S B (Least 5
1gn1, ficant Bi Riha(Vref-
From VB )/2N tel, equation (9) represents an error of about 4 LSB.

On the other hand, in order to eliminate the error expressed by formula (85), (6
) Even if Tf is selected so that the equation holds true,
In the circuit shown in FIG. 4, the glitch generated by the decoding means S is directly output to the output terminal (63), causing an output error.

(c) Problems to be solved by the invention As mentioned above, in the conventional example, it is necessary to employ an expensive sampling and holding circuit that is commensurate with the accuracy of the D/A converter, that is, the characteristics of the components have been carefully examined. Alternatively, there are problems in that the above-mentioned error C occurs, or jiglitches occur due to mismatches in processing times for each bit of the decoding means for receiving digital data. The present invention aims to provide a D/A converter that solves these problems.

B) Means for Solving the Problems The present invention provides means for decoding the upper M bits of N-bit digital data, which divides the voltage between the first reference potential and the second reference potential using seven resistors. a first D/A conversion circuit comprising means for selectively extracting two adjacent potentials from the voltage dividing means according to the output of the decoding means; provided, 2N
- " counting circuit, based on the count contents of the counting circuit, (N-M) bits out of 2N- " clock period (TP) which is shorter than one D/A conversion period (Tc). Select one of the two potentials for a period determined by the data,
During the remaining clock period, there is a means for selecting the other potential, a means for synthesizing the two selected potentials, a means for outputting the output of the synthesizing means, and for the remaining period (Tc-Tp), neither of the two potentials is selected. The D/A converter is characterized in that it is coupled with a second D/A converter circuit having means for bringing the output means into an impedance state without selecting the output means.

(e) Function The present invention does not output the above error (2N-Tp) because it does not output any of the two points near the output terminal during the remaining period (Tc-Tp) and maintains the high impedance. The above-mentioned glitch can be prevented by delaying the start timing of one clock period TPO by a certain period of time (a period during which the decoding means is stabilized) from the input timing of digital data.

(f) Embodiment FIG. 1 is a block diagram showing the basic configuration of a D/A converter according to the present invention. FIG. 2 is the sixth waveform diagram explaining the operation. This D/A converter converts the upper M bits of N-bit binary digital data into analog data, and converts the lower (N - M) bits into analog data. Second D/A conversion port 2 for converting into
It is made up of.

First, to explain the first D/A conversion circuit 1, this D/A
The i-conversion circuit 1 includes a decoder 112, a voltage dividing circuit 12, and a switching circuit 13. The voltage dividing circuit 12 is made up of 2i equal resistors connected in series, and both ends are connected to a fixed potential Vref, which is to be a reference potential, and a substrate potential Vv, respectively, and a large divided voltage is output from both ends of each resistor. The terminals are connected to a switching circuit 13. The decoder 11 to which M-bit data is input emits six signals to the switching circuit 16 according to the input contents, and the M-bit data input to the decoder 11
Two potentials Vff and V2 corresponding to bit data
is obtained from the switching circuit 13. These potentials Vl and V2 are N-bit data 60.61...
Data of the upper M bits of aN-1 from the lower side a
N-y, aN-M+1...aN-1, and the first D
When the minimum output voltage step of the /A conversion circuit 11 is eM, V 1 = (a NM, f-4-a NM+1-
'l early-+aN-1? ”>-e,-(11V 2 =V
s +6M ・・・・・・It is the potential expressed by (2). Specifically, it is the potential of the resistor selected corresponding to M bits of input data from among the two resistors configuring the voltage divider circuit 12. The potentials at both ends, that is, the potentials of adjacent divided voltage output terminals, in other words, two potentials that are close to each other. Note that - is expressed by the following formula (3).

eM=rVref-Vl/2M--(31 The output potential V1°V2 of such a switching circuit 16 is
It is designed to be applied to the A conversion circuit 2 as a reference potential.

Next, the second D/A conversion circuit 2 includes a coincidence circuit 21 with (N-M) bit input, a clock oscillation circuit 22, a counter (counting times g) 23 of 24M, and R-87! J flop flop 24,
Switching transistor 25.2 consisting of IGFET
6. Control circuit 27 is turned off.

Sate (21 type Yo') V 2 ” V t = eIM
The minimum output voltage step value of the second D/M conversion circuit is ~=v2N""M, but by substituting equation (3), we get e, = (Vref-Vm)/2N・" ...(4) The lower (NM) bit data is aO*a1...
~-When the edge is reached, v out= <aO# t+g ・2'+"+%-
M-12N-5N+v l, but by substituting equations (1) and (4) into this, ■0ut=(ao・20+a1.
21+・+-7 Fee a-sama Ku・aN-1・2'-')X(
Vref-VE)/2N, , -(5), which is taken out as an analog output of the D/A converter according to the present invention.

The control circuit 27 receives a control signal WC whose period corresponds to one D/A conversion period Tc and a clock from the oscillation circuit 22, and waits for a certain period T from the rising timing of this control signal.
After a delay of m, reset No. 1 ■7 is given to the counter 26.

This fixed time Tm is set to a time during which digital data changes in the first D/AK conversion circuit 1 and an analog output V1°2 corresponding to the data is stably output. The control circuit 27 creates a gate signal Vll that is set to a high level during a clock period Tp of 2''1 after the generation of this reset No. 1 v7, and outputs this gate signal Vll to each of It is attached to one input terminal.

The second D/A conversion circuit 2 controls the on/off state of the switching transistors 25 and 260, whose on/off states are reversed depending on the contents of the (N-M) bit input data.
This is a pulse width modulation type in which (1) 1 selection time TQ and 12 selection time Tr within a fixed time period of the potential to be input to the low-pass filter 3σ are changed according to the contents of input data. That is, the counter 26 counts the clock generated by the clock oscillation circuit 22 after the reset signal V7 is generated from the control circuit 27, and provides the clock to the control circuit 27 each time the count reaches O (once for each clock 2N-1 input). and generates a signal v8 which should reset the R-8-y flip-flop 24.

The counted contents are output to the matching circuit 21. Matching circuit 21
is the R-8 flip when the input of (N-M) bits matches the count contents.

A signal 9 to set the flop 24 is generated.

The R-8 flip-prop 24 outputs a Q output VtO and a Q output V+o by the set signal V9 and reset signal v8.
are supplied to the respective ant-games) 28,29, and each ant-games) 28,29 are each supplied with a switch transistor 25.
．． 26 are supplied with switch signals V13 and Vl2 that turn on the switch transistors 25 and 26. Therefore, the point 3) 1, which is formed by combining the outputs of the respective switch transistors 25 and 26, is once (7) D/Aff period rI! J'
I'cop, period 1m5TQl is ■1, i was period T
V2 is assigned to r, and the remaining period (To-Tp=Tc
-Tq-Tr )ic is brought into a high impedance state by cutting off these two potentials Vl and V2. This composite signal Vl4ha2'[Vt, 'izkatir
The period of L, , v2 (or Vl) is a signal determined by the contents of (NM) bits of input data. The low-pass filter 30 then smoothes the pulsed signal V14.

(f) Effects of the Invention In the present invention, the second D/A conversion circuit performs the pulse width modulation operation after a certain period of time Tm has elapsed after inputting digital data, so the first modulation circuit is provided with a plurality of first modulation circuits. Glitches that occur until the decoder stabilizes can be prevented. Also, one D/A conversion circuit is used in the second D/A conversion circuit.
/A The pulse width modulation is executed within a shorter period Tr of the conversion period Ta, and the remaining period f'Ik
J (To-TP), the first D/mu conversion circuit output vt,
Since neither vz is output and is in a high impedance state, vl or vl is output during the period (Tc-Tp).
There is no risk of the above-mentioned error l occurring as in the conventional example where .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of a D/A converter according to the present invention, and FIG. 2 is a waveform diagram for explaining the operation. FIGS. 3 and 4 are block diagrams of different conventional examples. (1)...First D/A conversion circuit, l...
...Decoding means (decoder), (121...
Voltage dividing means, ■...Switching circuit, (2).
...Second D/A conversion circuit, mouth...-number circuit, ■...clock forced circuit, mu...
・2N-M counter, (24i...R-S flip 70s, 1000...control circuit, installation (support)...
...Switching transistor, @e...
-AND gate, can...Low pass filter. Figure 1 7.1 Figure 2 3T;ZI Figure 4

Claims (1)

[Claims] (1) means for decoding the upper M bits of N-bit digital data; means for dividing the voltage between the first reference potential and the second reference potential by 2^M resistors; A first D/A conversion circuit equipped with means for selectively taking out two adjacent potentials according to the output of the decoding means, and a 2^
N^-^M counting circuit, based on the counting contents of the counting circuit, 2^N^ shorter than one D/A conversion period (Tc)
- Means for selecting one of the two potentials during a period determined by (N-M) bit data of the M clock period (Tp) and selecting the other potential for the remaining clock period; means for synthesizing the two selected potentials, means for outputting the output of the synthesizing means, and means for bringing the output means into a high impedance state without selecting any of the two potentials during the remaining period (Tc-Tp). A D/A converter comprising: a second D/A conversion circuit comprising: