JPH0375100B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a high-precision, high-bit D/A (digital/analog) converter, and is applicable to devices equipped with various D/A converters, such as It is used in voice synthesizers, CD (compact disc) players, etc.

[Prior art]

D/A converters generally include a decoding circuit for inputting digital data, but glitches occur due to mismatches in processing times for each bit of this decoding circuit. For example, when digital data changes from "011...1" to "100...0", if the most significant bit is decoded earliest, it temporarily becomes "111...1" and spike-like noise appears in the analog output. This noise is a glitch.

Furthermore, there are some types of converters, such as integral type D/A converters, that require a predetermined amount of time until the converted output becomes stable.

For the above reasons, a sample hold circuit is generally provided at the subsequent stage of the D/A conversion circuit, and sampling is performed when the output of the D/A conversion circuit becomes stable. That is, as shown in FIG.
1 output is applied to a sample hold circuit 43 via a switch 42 which is closed after the circuit output becomes stable. Capacitor 44 and operational amplifier 4
This sample-and-hold circuit 43 having a circuit 5 provides its output to a low-pass filter 46 and outputs the output terminal
Output analog data to 7.

Here, if the D/A conversion circuit 41 is highly accurate, a sample hold circuit 43 that receives its output
The components must also be constructed with high-precision elements, which has the disadvantage of being expensive.

Japanese Unexamined Patent Publication No. 57-23321 has a D/
A converter is introduced. Although this does not require expensive sample and hold circuits, it does have the disadvantage of introducing the errors described below and the unavoidable glitches described above. This conventional D/A converter has a first D/A converter circuit 51 which inputs the upper M bits of N bits of digital data, and a first D/A converter circuit 51 which inputs the lower (NM) bits and the first D/A converter circuit 51 which inputs the upper M bits of N bits of digital data.
A second D/A that inputs the output of the A conversion circuit 51
A conversion circuit 52 is provided. The M-bit digital data is decoded by decoding means 53, and the decoded signal is input to switch circuit 54.
This switch circuit selectively outputs two nearby potentials according to the decoded signal from among the means 55 that divides the voltage between the first reference potential Vref and the second reference potential _VE using ^2M resistors. do. These two adjacent potentials V1 and V2 (V2>V1) roughly represent a region where an analog quantity corresponding to N-bit digital data exists.

The second D/A conversion circuit 52 specifies the range between the two adjacent potentials more precisely based on the digital data of the lower (NM) bits, and includes a clock oscillation circuit 56, a 2 NM counting circuit 57, and a 2 ^NM counting circuit 57. , (N-
M) A coincidence circuit 58 which checks the coincidence between the bit digital data and the output of the counting circuit 57, an R-S flip-flop 59 which is set by the output of this coincidence circuit 58 and reset by the output of the counting circuit 57,
Two gate circuits 60 and 61 that selectively output the two adjacent potentials at the output of the S flip-flop 59.
and a low-pass filter 62 that inputs the combined output of both gate circuits.

In this conventional D/A converter, the period (1
The D/A conversion period Tc) and the period Tf of the clock oscillation circuit 56 are often asynchronous, so Tc=1×2 ^NM ×Tf (6) I: It is difficult to set it to a natural number. Therefore, Tf is usually selected so that Tc is larger than I×2 ^NM ×Tf.

The composite output V6 of gate circuits 60 and 61 always has
Since V1 or V2 is output, (Tc−I×
2 ^NM ×Tf) (surplus period), the potential of V1 or V2 is output to the output terminal 63, resulting in an error ε.

Digital data is sequentially converted from low-order bit to a ₀ , a ₁
..., a _N-1 , Vout is generally Vout=(a ₀・2 ⁰ +a ₁・2 ¹ +… +a _N-1・2 ^N-1 )×(Vref −V _E )/2 ^N +ε = It can be expressed as Vx+ε...(7).

For example, if the potential V2 on the high voltage side of two potentials close to each other is output to the output terminal 63 during a period of (Tc - I x 2 ^NM x Tf), the error ε is as follows: ε = (V2 - Vx) x (Tc - I×2 ^NM ×Tf)/Tc...(8) Here, N=16 (bits), M=8 (bits), I=1 (pulse width modulation once),
Tc = (2 ^NM + 4) x Tf (V2 is output to the output terminal as a 4 x Tf period error), and the data of the lower (NM) bits are set as a ₀ = 1, a ₁ to _{a NM-1} = 0. Then, V2−Vx=( ²⁸⁻¹ )×(Vref−V _E )/2 ^N ε=255×4/260×(Vref−V _E )/2 ^N ≒3.92(Vref−V _E )/2 ^N ...(9) becomes. 1LSB (Least) of D/A converter
Significant Bit) is (Vref−V _E )/2 ^N , so equation (9) represents an error of about 4 LSB.

On the other hand, in order to eliminate the error expressed by equation (8), (6)
Even if Tf is selected so that the equation holds true, in the circuit of FIG. 4, the glitch generated by the decoding means 53 will be output as is to the output terminal 63, causing an output error.

In this way, it is necessary to adopt an expensive sample-and-hold circuit that matches the accuracy of the D/A converter, that is, the characteristics of the components have been carefully examined, or to generate the above-mentioned error ε, or to receive digital data. There is a problem in that glitches occur due to inconsistencies in processing times for each bit of the decoding means. Therefore, the applicant of the present application proposed a D/A converter that solves these problems in Japanese Patent Application No. 197507-1983.

As shown in FIG. 5, the present invention includes a decoder 81 that decodes the upper M bits of N-bit digital data _Do , and ^2M resistors connected between the first reference potential Vref and the second reference potential _VE . A first D is provided with a voltage dividing circuit 82 that divides the voltage according to the voltage dividing circuit 82, and a switching circuit 83 that selectively extracts two adjacent potentials V1 and V2 corresponding to the digital data D _o corresponding to the output of the decoder 81 from the voltage dividing circuit 82. /A conversion circuit 71
A counter 93 of 2 ^NM is provided for data of the lower (NM) bits, and one D/A conversion period (Tc) is calculated based on the count contents of the counter 93.
One of the two potentials is selected for the period determined by the (NM) bit data of the 2 ^NM clock period (Tp) shorter than 2 NM, and the other potential is selected for the remaining clock period. The oscillation circuit 92, the coincidence circuit 91, and the control circuit 97
and R-S flip-flop 94, AND gates 98, 99, switching transistors 95, 9
6, etc., and means such as a low-pass filter 100 that synthesizes and outputs the two selected potentials, and in the remaining period (Tc-Tp), neither of the two potentials is selected and the output means is set to high. It also includes a second D/A circuit 72 designed to be in an impedance state. In such a D/A converter, during the remaining period (Tc-Tp), neither of the two potentials V1 and V2 in the vicinity of the output terminal is outputted, and a high impedance is maintained, so that the above-mentioned error ε is not outputted.
Furthermore, the above-mentioned glitch can be prevented by delaying the start timing of the 2 ^NM clock period Tp by a certain period of time (a period during which the decoding means is stabilized) from the input timing of digital data.

[Problem that the invention seeks to solve]

Now, the invention of Japanese Patent Application No. 59-197507 as described above can solve the conventional problems to a certain extent, but when the upper M bits fluctuate greatly, the first D/A
The time required for the output of the conversion circuit 71, and thus the output of the D/A converter as a whole, to become stable becomes longer. In particular, in the case of a high-bit voltage converter, the number of bits M handled by the voltage dividing circuit 82 is large, and the time required for the output voltage of the circuit to transition is large, and the conversion speed is limited by the time it takes for the output voltage to stabilize. The problem is that it is difficult to increase the speed.

To solve this problem, it is possible to lower the resistance value of the resistor string that makes up the voltage divider circuit 82 and to increase β of the MOSFET that makes up the switching circuit 83. However, when configured with an IC, This results in an increase in chip area and requires the use of an expensive process, making it impossible to avoid an increase in chip cost.

[Means for solving problems]

The present invention has been made in order to solve the problems of the prior art.
A decoder is provided to decode bit data,
Another object of the present invention is to provide a D/A converter that can convert data with a high number of bits at high speed by determining two adjacent potentials V1 and V2.

The D/A converter according to the present invention has a first
a second decoding means for decoding the upper L (L<M) bits of the N-bit digital data;
decoding means, means for dividing the voltage between the first reference potential and the second reference potential using 2 ^M resistors, and a voltage of 2 ^NM shorter than one D/A conversion period Tc from the voltage dividing means. The clock period Tp and the period T _L shorter than the remaining clock period Tc - Tp are defined as the remaining clock period (Tc - Tp - T _L ) is the proximity 2 according to the output of the first decoding means.
A first device comprising means for synthesizing and extracting a potential and two adjacent potentials corresponding to the output of the second decoding means.
A D/A conversion circuit is provided for the lower (N-M) bit data, and a 2 ^NM counter is provided for the data of the N-M bits during the period Tp based on the count contents of the counter. means for selecting one of the two potentials taken out by the first D/A conversion circuit during a predetermined period and the other potential for the remaining period; output means for synthesizing and outputting the selected potentials; and a second D/A conversion circuit having means for selecting neither of the two potentials and placing the output means in a high impedance state during the remaining period Tc-Tp.

[Effect]

In the present invention as described above, during the period T _L , the switching circuit outputs two adjacent potentials based on the data of the most significant L bit, so even if the input digital data changes greatly, the first D The time required for the output voltage of the /A conversion circuit, and hence the output voltage as a whole, to become stable can be shortened.

Furthermore, the period during which the output is made high impedance can be shortened, making it possible to improve output accuracy. Furthermore, if the accuracy is at the conventional level, faster conversion is possible.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a D/A converter according to the present invention, and FIG. 2 is a waveform diagram for explaining its operation.

The present invention includes a first D/A conversion circuit 1 that converts upper M bits into analog data, and a lower (N
-M) A second D/A conversion circuit 2 for converting bits into analog data, and the second D/A conversion circuit itself is the same as that in Japanese Patent Application No. 59-197507 shown in FIG. It is.

The upper M bits of the N-bit digital data D _o are input to the M-bit decoder 11,
Also, the upper L bits of data D _o (L<M)
are input to the L-bit decoder 12, which supplies signals corresponding to the respective input contents to the switching circuit 14. The voltage divider circuit 13 is made up of 2 ^M equal resistors connected in series, and is connected between the first reference potential Vref and the second reference potential V _E , and the voltage divided by the voltage drawn from both ends of each resistor. The pressure output terminal is connected to a switching circuit 14.

The switching circuit 14 is controlled on and off by the inputs of the decoders 11 and 12, and the voltage dividing circuit 13
The potential of any two of the divided voltage output terminals of the input data _D
[Fig. 2 E, W] and outputs it to the switching transistor 2 of the second D/A conversion circuit 2.
Give to 5 and 26 respectively. Second D/A conversion circuit 2
The control circuit 27 supplies a timing signal V15 to the switching circuit 14 as shown in FIG. 2D.

A control signal WCK (FIG. 2A) defining the D/A conversion period Tc is inputted to the control circuit 27 from an external circuit. Accordingly, the data D _o is updated as shown in FIG. 2B.

The switching circuit 14 selects two potentials V1M and V2M (V2M>V1M) corresponding to the M-bit data input to the M-bit decoder 11 during the clock period Tp (see FIG. 2), which is 2 ^NM shorter than Tc. The signal is then applied to the sources of the switching transistors 25 and 26 of the second D/A conversion circuit 2.

During the remaining clock period (Tc-Tp), two potentials V1L and V2L (V2L>V1L) corresponding to the L-bit data input to the L-bit decoder 12 are combined with the aforementioned V1M and V2M.

V1M, V2M, V1L obtained in this way,
V2L converts the upper M bits of a ₀ , a ₁ , a ₂ ...a _N-1 of N-bit data D _o from the lower side to a _NM ,
a _N-M+1 , a _N-M+2 ...a _NL , a _N-L+1 , ...a _N-1 , and the minimum output voltage step of the first D/A conversion circuit 1 is e _M Then, V1M=(a _NM・2 ⁰ +a _N-M+1・2 ¹ +… +a _N-1・2 ^M-1 )e _M ……(1) V2M=V _1M +e _M ……(2) V1L = (a _NL・2 ⁰ +a _N-L+1・2 ¹ +… +a _N-1・2 ^L-1 )e _M ……(3) V2L=V _1L +e _M ……(4) However, e _M = (Vref−V _E )/2 ^M (5) This is the potential expressed as follows. Specifically, the voltage dividing circuit 13
This is the potential at both ends of the resistor selected in response to M-bit or L-bit input data among the ^2M resistors constituting the resistor, that is, the potential at the adjacent divided voltage output terminals.

The output voltage of such a switching circuit 14
V1M, V2M, V1L, and V2L are given as second D/A conversion circuit reference potentials.

Next, the second D/A conversion circuit 2 will be explained. Reference numeral 21 denotes a matching circuit which inputs the lower N-M bits, checks whether this input data matches the count value of the counter 23, and at the timing of the match, outputs the second matching circuit.
A match signal V9 shown in the figure is generated. This signal V9
is applied to the set terminal S of the R-S flip-flop 24. The oscillation circuit 22 provides a clock to the counter 23 for counting purposes, and the control circuit 27
give to The control circuit 27 is based on this clock.
A reset signal V7 (FIG. 2C) that rises after T _n has elapsed since the rise of WCK is issued to the counter 23.
When the count reaches 0, the counter 23 emits a reset pulse V8 (FIG. 2), which is sent to the control circuit 2.
7 and R-S to the reset terminal R of the flip-flop 24. Since the R-S flip-flop 24 receives the coincidence signal V9 and reset pulse V8 as described above, its set output V10 changes as shown in FIG.
Further, the complementary signal 10 is applied to the AND gate 29. After the reset signal V7 is generated, the control circuit 27 generates a gate signal V11 (FIG. 2) which remains at a high level for a clock period Tp of 2 ^NM , and uses this as the other input to the AND gates 28 and 29.
AND gates 29 and 2 shown in Figure 2
The outputs V12 and V13 of 8 are applied to the gates of IGFET (insulated gate field effect transistor) switching transistors 26 and 25. The sources of the transistors 25 and 26 are connected together and connected to a low-pass filter 30, and the input signal thereof is smoothed and becomes the output Vout of the second D/A conversion circuit 2 or the present invention device.

Now, the minimum output voltage step e _N of the second D/A conversion circuit is e _N = e _M /2 ^NM , but by substituting equation (5), e _N = (Vref - V _E )/2 ^N ...(6) becomes. The lower (NM) bit data is a ₀ , a ₁
...a _NM-1 , the output Vout is Vout = (a ₀・2 ⁰ +a ₁・2 ¹ ... +a _NM-1・2 ^NM-1 )e _N +V1M, and then equations (1) and (6) are Substituting Vout = (a ₀・2 ⁰ +a ₁・2 ¹ +… +a _NM-1・2 ^NM-1 +2 _NM・2 ^NM +… +a _N-1・2 ^N-1 ) × (Vref−V _E )/2 ^N ...(7) This is taken out from the low-pass filter 30.

Next, the operation of the present invention device will be explained in more detail.

After inputting the control signal WCK, the control circuit 27 generates a reset signal V7 after T _n has elapsed based on the clock count from the oscillation circuit 22, and sets the timing signal V15 to a high level after T _n -T _L has elapsed.

During the period T _n , the digital data changes in the first D/A conversion circuit 1, and the corresponding analog output V1M or the composite value of V1M and V1L (hereinafter collectively referred to as V1) and V2M or V2M It is defined as the time required for the composite value of V2L and V2L (hereinafter collectively referred to as V2) to reach a stable value, that is, the time required for the rise period to end and a stable state to be reached as shown in Figure 2 E. put.

Therefore, during the period T _n -T _L in the first half of the period T _n , both the switch corresponding to the output of the L bit decoder 12 and the switch corresponding to the output of the M bit decoder 11 are closed, and in the second half of the period T _n , the switch corresponding to the output of the M bit decoder 11 is closed. That is, during the period T _L , the switching circuit 14 is controlled by the signal V15 so that only the switch corresponding to the output of the M-bit decoder 11 is closed.

Due to this operation, T _n −T _L in the first half of period T _n
During this period, the effective on-resistance can be lowered compared to when only the switch corresponding to the upper M bit data is turned on, and the rises of V1 and V2 can be made steeper. In FIG. 2D, solid lines indicate the state of change in V1 and V2 in the case of the device of the present invention, and broken lines indicate the state of change in V1 and V2 of the D/A converter shown in FIG.

As is clear from these comparisons, in the present invention, V1,
The rise time of V2, that is, T _n can be shortened.

Next, after the reset signal V7 is generated, the control circuit 27
^The AND gate 28,
Give to 29.

The second conversion circuit 2 should control the on and off of switching transistors 25 and 26, which are turned on and off in the opposite way, according to the contents of the N-M bit input data, and input the data to the low-pass filter 30. It is a pulse width modulation type in which the V1 selection time T _Q [Fig. 2 N] and the V2 selection period T _R [Fig. 2 R] within a fixed potential time are changed according to the contents of input data. .

That is, the counter 23 counts the clock output from the oscillation circuit 22 after the reset signal V7 is input.
Each time the content becomes 0, that is, each time 2 ^NM clocks are counted, a reset pulse V8 is generated.
(The reset pulse V8 is also generated when the reset signal V7 is input from the control circuit 27 and becomes 0.) On the other hand, the counter 23 outputs the count contents to the coincidence circuit 21, and the input of the N-M bits and the count contents match. When this happens, a match signal V9 is generated and the R-S flip-flop 24 is set. Set output V10 and reset output 1 of R-S flip-flop 24
0 is given to the AND gates 28 and 29, respectively, so the AND gate 28 is given to each high and low.
From then on, V13 shown in Figure 2 is the AND gate 2.
9 outputs V12 shown in FIG.

The smaller (or larger) the value of the N-M bit data is, the shorter (or longer) the period T _Q during which V12 is at a high level, and conversely the longer (or shorter) the period T _R during which V13 is at a high level. . V like this
12, V13 are given to transistors 26, 26, so during the period Tc, _TQ is V2, and the period
V1 is given to T _R , and the remaining period (that is, the counter 23 counts 2 ^NM and returns to 0, and the control circuit 2
After setting the gate signal V11 of 7 to low level)
At Tc-Tp, both transistors 25 and 26 are turned off, and the collective connection point 31 on the source side of the transistors 25 and 26 becomes in a high impedance state. FIG. 2 shows the potential V14 at the connection point 31. In other words, the potentials V2 and V1 alternate between Tc,
The time is determined according to the contents of the lower N-M bits of the input data _Do. The low-pass filter 30 smoothes and outputs V14.

〔effect〕

In the present invention, when there is a large change such that the upper L bits of N-bit input data change, the period until the decoder constituting the first D/A conversion circuit stabilizes, or V1, V2 Period until stabilization
T _n can be shortened and high-speed conversion becomes possible.
In other words, the period during which the output of the D/A converter is in a high impedance state can be shortened, making it possible to cope with cases where the conversion speed is high. Furthermore, when the conversion speed is slow, the ratio of the period (T _n ) in which the output is in high impedance during one sampling period (Tc) can be reduced, and accuracy can be improved. In addition, since the second D/A conversion circuit performs the pulse width modulation operation after a certain period of time T _n has elapsed after inputting digital data, it is possible to stabilize the decoders 11 and 12 in the first conversion circuit. The present invention has excellent effects such as being able to prevent glitches.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a D/A converter according to the present invention, FIG. 2 is a time chart for explaining its operation, and FIGS. 3 and 4 are block diagrams of a conventionally known D/A converter. FIG. 5 is a block diagram of the D/A converter of the prior application. 1...First D/A conversion circuit, 2...Second D/A conversion circuit, 11...M bit decoder, 1
2...L bit decoder, 13...Voltage divider circuit, 1
4...Switch circuit, 21... Match circuit, 22...
...Oscillation circuit, 23...Counter, 24...R-S
Flip-flop, 25, 26... Switching transistor, 27... Control circuit, 28, 29...
...AND gate, 30...low pass filter.

Claims (1)

[Scope of Claims] 1. A first decoding means for decoding the upper M bits of N-bit digital data, a second decoding means for decoding the upper L (L<M) bits of the N-bit digital data, and a second decoding means for decoding the upper M bits of the N-bit digital data. Means for dividing the voltage between the first reference potential and the second reference potential using ^2M resistors, and one D/A from the voltage dividing means.
The period T _P of the ^2NM clock shorter than the conversion period T _C and the period T _L shorter than the remaining period T _C −T _P are the first
The first adjacent two potentials corresponding to the output of the decoding means are selectively taken out, and the period T _{C - T P - T L excluding the periods T P and T L from} the D/A conversion period T _C
said first proximity 2 according to the output of the decoding means of
a first D/A conversion circuit comprising means for synthesizing and extracting a potential and two second adjacent potentials corresponding to the output of the second decoding means; A 2 ^NM counter is provided for this purpose, and based on the counting contents of the counter, the period determined by the NM bit data of the period T _P is determined by the first D/A conversion circuit extracted by the first D/A conversion circuit. means for selecting one of the two adjacent potentials of 1 and the other potential for the remaining period; output means for synthesizing and outputting the selected potential; and for the remaining period T _C - T _P A D/A converter comprising: a second D/A converter circuit having means for setting the first output means to a high impedance state without selecting either of the two potentials.