JPH1198019A - D/a conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate glitch noise of timing deviation at the time of switching by decoding each bit through pre-stage processing which performs segment latch of a digital signal to high and low order bits and different logical processing and selecting and a switching a converter resistance tap with a signal that is decoded in each bit again after latch processing. SOLUTION: An 8-bit digital signal 101 of a conversion object is inputted to a decoder 2 through a buffer 1, it is divided into low and high order bits, they are performed logical processing by gate circuits which are different stages and are outputted as low and high order bits 102 and 103. In such cases, although the deviation at a bit position occurs, both latches 3 and 4 perform processing at first transition of a clock signal 104 at the time of latch, the bits 102 and 103 are inputted to a D/A converter 7 as a signal that is synchronized with the signal 104 and does not have deviation and as decode signals 107 and 108 which do not have deviation by decoders 5 and 6, and a desired digital signal 109 is produced and outputted by performing selection switching of a resistance tap for D/A conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A conversion circuit, and more particularly to a D / A conversion circuit having a built-in decoder circuit for reducing glitch noise.

[0002]

2. Description of the Related Art The configuration of a conventional D / A conversion circuit (hereinafter, referred to as a first conventional example) incorporating a decoder circuit of this kind is shown in a block diagram of FIG. As shown in FIG. 3, in this conventional example, a digital signal 101 (“0”, “1”,..., “7”) is input, and a clock signal 104 is input.
, And an output signal 110 of the latch 8, and the D / A conversion logic signal is divided into an upper bit and a lower bit, and a lower bit 102 and an upper bit, respectively. And a D / A converter 10 receiving the input of the lower bits 102 and the upper bits 103 output from the decoder 9 and performing D / A conversion to output an analog signal 109.
And is provided.

In FIG. 3, an 8-bit digital signal 101 to be converted is input to a latch 8 and latched via a clock signal 104, and an output signal 110 is input to a decoder 9. In the decoder 9, the 8-bit digital signal 110 is divided into lower bits and upper bits, decoded and output as lower bits 102 and upper bits 103, respectively, and input to the D / A converter 10. The D / A converter 10 receives the input of the lower bit 102 and the upper bit 103 and receives the input of the D / A converter 10 provided in the D / A converter 10.
A conversion resistor tap is selected corresponding to each bit, and a desired analog signal 109 is generated and output. In the first conventional example, as described above,
After the digital signal 101 input to the latch 8 is latched in the latch 8, a resistor tap selection for D / A conversion is performed by the decoder 9 receiving the output, and the lower bit 102 and the upper bit 103 are selected. In the decoding process corresponding to the above, there is a difference in the number of stages of the gate circuit due to the configuration, and the timing at which the switch for selecting the resistance tap of the D / A converter 10 is switched
A time lag occurs in accordance with the conversion code, and as a result, glitch noise occurs on the analog signal output from the D / A converter.

FIG. 4 is a block diagram showing a configuration of another conventional example (hereinafter, referred to as a second conventional example) intended to reduce the glitch noise. This conventional example is designed to reduce the occurrence of the glitch noise.
A conversion circuit, as shown in FIG. 4, (“0”,
8-bit digital signal 1 of "1",..., "7")
01, a latch 8 for performing a latching process via a clock signal 104, and a digital signal 110 output from the latch 8 for performing a logical process. Bits and lower bits, and the lower bits 102 and the upper bits 103, respectively.
And latch circuits 11 and 12 for individually latching the lower bit 102 and the upper bit 103 output from the decoder 9 via a clock signal 104, respectively.
And a D / A converter 13 that receives the outputs of D and A and performs D / A conversion and outputs an analog signal 109. The latch circuit 11 includes a latch 11-1, a latch 11-2,..., A latch 11-16, and the latch circuit 12 includes a latch 12-1, a latch 1
2-2,..., And latches 12-16.

[0005] In FIG. 4, an 8-bit digital signal 101 to be converted is input to a latch 8 and latched via a clock signal 104, and a digital signal 110 output from the latch 8 is input to a decoder 9. .
In the decoder 9, an 8-bit digital signal 11
0 is divided into a lower bit and an upper bit, decoded and output as a lower bit 102 and an upper bit 103, respectively, and input to the corresponding latch circuits 11 and 12. In latch circuits 11 and 12, lower bit 102 and upper bit 103 are latched again via clock signal 104. In this case, in the latch circuit 11, the lower bits 102 are subjected to timing adjustment between the bits by the latches 11-1 to 11-16.
2, the upper bit 103 includes the latches 12-1 to 12-1.
According to 12-16, timing adjustment between each bit is performed. The lower-order bit 111 and the upper-order bit 112 whose timing has been adjusted in this manner are supplied to the D / A converter 10.
Is input to In the D / A converter 10, upon receiving the input of the lower bit 111 and the upper bit 112, a resistor tap for D / A conversion provided in the D / A converter 10 converts each of these taps. The signal is selected and switched according to the bit, and a desired analog signal 109 is generated and output. In this conventional example, the “shift” in the timing of the lower bits and the upper bits is
By using the above two-stage latch circuit, it is possible to apparently correct and reduce the size, and it is possible to reduce the glitch noise. However, the configuration of the latch circuit requires separate latch circuits for the lower bit and the upper bit, respectively, thereby increasing the circuit scale. In addition, in the latch circuit, the output data decoded from the input data is further reduced. Therefore, a timing for latch processing until the time is obtained is required, so that a time delay corresponding to one cycle of the clock signal occurs, and the sampling time increases.

It is to be noted that a conventional D having a decoder circuit is used.
As other examples of the / A conversion circuit, other than the above, for example,
Examples are described in the D / A converter of JP-A-56-1436326 and the digital / analog converter of JP-A-60-256228. In the former conventional example (JP-A-56-1436326), N
Bit digital data is divided into lower bits and upper bits, and the data of the divided upper bits is divided into D bits.
By creating a reference voltage used for lower bit conversion based on the analog voltage obtained by the / A conversion,
D / A conversion is intended to improve the D / A conversion accuracy by reducing the influence of “variation” occurring in the D / A conversion operation.
An A-converter has been proposed, but the conventional example is not a proposal that aims to reduce glitch noise, which is an object of the present invention, but a proposal that has a different technical base with a different purpose from the present invention. is there. In the latter conventional example (JP-A-60-256228), in a segment type digital / analog converter, a decoder circuit is provided with a latch function, and the digital output is used to continuously and selectively switch. The constant current value of the constant current source is added to extract a desired D / A conversion output signal as an analog current output, thereby obtaining the glitch and
Digital-to-analog converters have been proposed to reduce the occurrence of noise.
Despite the challenge of noise reduction, its D / A
The technical idea relating to the conversion function is a proposal based on a fundamentally different technical base from the present invention.

[0007]

The conventional D / A described above.
In the conversion circuit, in the case of the first conventional example, "delay" of timing is applied to a signal for selecting a switch corresponding to a lower bit and an upper bit due to a circuit configuration of a decoder.
The level of the transient “whisker” -like glitch noise generated on the D / A conversion output signal increases as the amount of the “shift” increases, and the rising edge of the analog signal output increases. There is a disadvantage that the convergence time at the fall increases.

Further, in the case of the second conventional example, by providing two stages of latch circuits as means for reducing the occurrence of glitch noise, the "shift" between the lower bits and the upper bits can be apparent. Although it is considered above that they are aligned, for example, in the case of an 8-bit D / A conversion circuit, in the second-stage latch circuit, 16 bits are used as the lower bits and the upper bits, respectively. The number of latches required increases the occupied area of the D / A conversion circuit, thereby increasing the manufacturing cost. By providing two stages of latch circuits, the delay time from the digital input signal to the analog output signal is obtained. But,
There is a disadvantage that the time is increased by the time corresponding to one cycle of the clock signal, that is, by the sampling time.

[0009]

A digital-to-analog converter according to the present invention is provided with a first digital signal for converting a digital signal to be converted into a low-order bit and a high-order bit of the digital signal and performing a decoding process. Decoding means, first latch means for latching a decode signal output from the first decode means in response to the lower bit, and an output corresponding to the upper bit from the first decode means. Second latch means for latching a decoded signal to be output, second decoding means for decoding and outputting a decoded signal output from the first latch means, and decode output from the second latch means. Receiving a pair of decode signals output from the second and third decode means, and It is characterized in that it is at least provided with a configuration and D / A converting means for generating and outputting an analog signal which is D / A converted in response to Le signal. .

The decode signal output from the first decoding means in response to the lower bit and the upper bit is supplied to the corresponding first and second latch means at the rising edge of the common clock signal. It may be latched at the timing,
The second and third decoding circuits may include at least the same number of gate circuits.
Further, the digital signal to be converted may be input to the first decoding unit via a predetermined buffer.

[0011]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG.
A buffer 1 to which an 8-bit digital signal 101 (“0”, “1”,..., “7”) is input;
And a decoder 2 for performing logical processing by dividing the output signal into lower bits and upper bits, and outputting as a lower bit 102 and an upper bit 103;
2 that latches 2 through a clock signal 104.
A latch 4 for latching the upper bits 103 via a clock signal 104, a decoder 5 for inputting a decode signal 105 output from the latch 3 and performing logical processing,
The decoder 6 which receives the decode signal 106 output from the latch 4 to perform logical processing, and receives the decode signal 107 and the decode signal 108 output from the decoder 5 and the decoder 6 to perform D / A conversion, The D / A converter 7 that outputs the analog signal 109 is provided.

In FIG. 1, an 8-bit digital signal 101 to be converted is input to a decoder 2 via a buffer 1. In the decoder 2, the 8-bit digital signal is divided into lower-order bits and upper-order bits, and logical processing is performed by gate circuits of different stages, and decoded and output as lower-order bits 102 and upper-order bits 103. To the latch 3 and the latch 4 which operate. In latches 3 and 4, these lower bits 102 and upper bits 103
Are latched via clock signal 104, and decode signal 1 output from latches 3 and 4
05 and 106 are input to the corresponding decoder 5 and decoder 6 and subjected to logical processing, and output as decode signal 107 and decode signal 108, respectively. The lower decode signal 107 and the upper decode signal 108 output from the decoders 5 and 6 are
The A / D converter 7 receives the input signal, and in the D / A converter 7, the selection of the A / D conversion resistor tap is performed by the decode signal 107 and the decode signal 108. An analog signal 109 corresponding to the input digital signal 101 is output.

In this case, in the decoding process performed in the decoder 1, since the contents of data such as the number of bits are generally different between the lower bits and the upper bits, the lower bits and the upper bits are different. Are different in the number of stages of the gate circuit required in the decoding process corresponding to. As a result, the timing of the lower bits 102 and the upper bits 103 output from the decoder 2 has a “shift” due to the bit position. These decode outputs are latched by the latches 3 and 4. At this time, since the latch process is performed at the rising edge of the clock signal 104, the lower bit 102 and the upper bit 103 are synchronized with the clock signal 104. Then, the "shift" of the timing
Are output from the latches 3 and 4 as a signal having no signal, and are input to the corresponding decoders 5 and 6. The decoder 5 and the decoder 6 are each configured by a gate circuit having the same number of gate stages.
The lower-order decode signal 107 and the upper-order decode signal 108 which are decoded and output by these decoders are input to the D / A converter 7 as signals having no "shift" in the timing between them. In the D / A converter 7, the selection of the D / A conversion resistor tap is switched by the decode signal 107 and the decode signal 108 having no “shift”, and the desired digital signal 1
09 is generated and output. Therefore, the digital signal 109 is output as an analog signal from which glitch noise has been removed due to a “shift” in the timing when the selection of the resistor tap is switched.

The following Table 1 shows the generated glitches calculated according to the circuit type of the built-in decoder.
The difference between the energy (pVs) and the required layout occupation area (μm ² ) of the latch circuit portion is displayed.
There are three types of circuit types: a stage latch circuit type (second conventional example: A), a single latch / decoder circuit type (this embodiment: B), and a conventional circuit type (first conventional example: C). ing.

[0016]

[Table 1]

As is apparent from Table 1, in the present embodiment, the glitches are smaller than those of the first conventional example.
The energy of noise is reduced to about one-fifth, and the layout occupation area of the latch circuit is reduced to 70% or less as compared with the second conventional example.

FIG. 2 shows the two-stage latch circuit type (second conventional example: A), the latch / decoder one-body circuit type (this embodiment: B) and the conventional circuit type (second example) shown in Table 1 above. 1 is a diagram showing relative output waveforms of glitch noise in three types of circuit formats C) by voltage output display based on simulation results, in which the horizontal axis represents time (ns), and the vertical axis represents time. The axis indicates the output voltage (V).

[0019]

As described above, according to the present invention, when a digital signal is divided into lower bits and upper bits and latched, the digital signal is divided into lower bits and upper bits before performing the latch processing. Decoded by different logical processing, the decoded output of the lower bit and the upper bit are individually latched through a predetermined clock signal, and the latch output is again decoded for each of the lower bit and the upper bit. By selecting and switching the resistance taps of the D / A converter in accordance with the output signal, the timing shift of the signal after the decoding process of the lower bit and the upper bit is performed as compared with the first conventional example. Can be reduced to achieve the effect of significantly reducing glitch noise in the analog output signal. In order to reduce glitch noise, two stages of latch circuits are provided, and the circuit scale is significantly reduced as compared with the second conventional example in which two latch processes are performed. There is an effect that the size can be reduced and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing simulation results of glitch noise output levels in the present embodiment and a conventional example.

FIG. 3 is a block diagram showing a first conventional example.

FIG. 4 is a block diagram showing a second conventional example.

[Explanation of symbols]

 1 Buffer 2, 5, 6, 9 Decoder 3, 4, 8 Latch 7, 10, 13 D / A Converter 11, 12 Latch Circuit

Claims (4)

[Claims] 1. A digital signal to be converted is inputted,
First decoding means for performing a decoding process by classifying the digital signal into lower bits and upper bits, and a first latch which latches a decode signal output from the first decoding means corresponding to the lower bit. Latching means, second latching means for latching a decoding signal output from the first decoding means in accordance with the upper bit, decoding processing of the decoding signal output from the first latching means A second decoding means for decoding and outputting a decoded output from the second latch means; and a pair of second decoding means for outputting a decoded output from the second and third decoding means. D / A conversion means for receiving an input of the decoded signal, generating and outputting an analog signal which has been D / A converted in accordance with the digital signal, and D / A, characterized in that it is configured with Ku and also
Conversion circuit. 2. A decoding signal output from the first decoding means in response to a lower bit and an upper bit is supplied to the corresponding first and second latch means, respectively, at the rising edge of a common clock signal. 2. The D / A conversion circuit according to claim 1, wherein the D / A conversion circuit is latched at a timing. 3. The second and third decoding circuits according to claim 1, wherein
2. The D / A conversion circuit according to claim 1, wherein the D / A conversion circuit includes at least the same number of gate circuits. 4. The D / A conversion circuit according to claim 1, wherein said digital signal to be converted is inputted to said first decoding means via a predetermined buffer.