JPS60256228A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To improve the converting accuracy of a converter by providing a latch to an electric switch of high-order m bits to eliminate glitch caused by variance of decoder drive. CONSTITUTION:An input means of a D/A converter is provided with a decoder driver inputting high-order 3 bits MSB, -MSB, 2 bits, -2 bits and 3 bits, -3 bits, each driver produces outputs A-C and inverted outputs A-C, the low level is taken nearly as the same degree and the high level is lowered sequentially from the high-order bit to the low-order bit. The output A-C and the inverted outputs A-C are fed to a segment decoder and a circuit having a latch circuit controlled by clocks phi, -phi. Then the switching is attained at each level RV, the clocks phi, -phi are adjusted so as to match the time difference between the driver and the segment decoder thereby eliminating glitch due to the variance of decode driving thereby improving the conversion accuracy of the converter.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a digital-to-analog converter (hereinafter referred to as a DA converter), and is particularly suitable for use in a one-chip IC, and is suitable for high-speed DA conversion with a frequency band of 200 MHz or more. Concerning vessels.

[Background of the invention]

Conventional ODA converters include, for example, an R, -2 resistance ladder type or an equal current addition type. In particular, as shown in FIG. 1, a compromise type is widely used in which the upper m bits are of the current adding type and the lower n bits are of the R-2R ladder type. In the figure, (m+n) bits of digital human power is added and an analog output is taken out.

The upper m-bit digital input is processed by a segment decoder, which sequentially turns (2ITl-1) switches from off to on, and outputs an analog output from 0 to -(2") according to the digital input cover turn. 1)X
IoX"R, maf(Dl[value is obtained. The lower n bit digital input directly switches n switches arbitrarily from off state to on state, and depending on the digital input cover turn, -2 2n 3 voltage values from 0 to -(1-")XL Voltage can be extracted with high accuracy.The advantages of l) A converter in the same figure are:
It is as follows.

(1) - Since the upper m bits are of the equal current addition type, there is less whisker-like noise, that is, glitches, which are likely to occur when switching the upper bits.

(2) Since it is only necessary to create an equal current circuit, the conversion product is improved when integrated into an IC.

(m10 low K (constant)) 1 chip I pit DA converter
In converting into C, the following drawbacks also occur.

(1) The decode driver is required to be high-speed. Therefore, if the decode driver is not high-speed, the waveform of the decode driver output varies, causing glitches.

(2) Although the driver shown in FIG. 1 adjusts the time delay of the decode driver and segment decoder, it is difficult to adjust the time. For this reason, the top n
A glitch occurs every time one bit and the lower n bits switch.

[Purpose of the invention]

An object of the present invention is to simultaneously and effectively realize both the reduction of glitches and the improvement of conversion accuracy in a l)A converter in which the upper part is a segment current addition type and the lower part is an IL-21% ladder type. The purpose is to provide circuits.

[Summary of the invention]

The present invention eliminates glitches caused by variations in decode drivers by providing a latch in the current switch of the upper m bits.

That is, the upper m bits are segment IItt11. This is an additive type L-2R ladder type DA converter (with the lower n bits) having a circuit configuration in which a segment decoder and a latch circuit are integrated.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. This figure shows three decode drivers, seven segment decoders, and part of the latch circuit when m=3. FIG. 3 explains the timing of this figure. The configuration and operation of the present invention will be explained with reference to FIGS. 2 and 3. The upper 3 bits input, i.e. MSB (MSB)
2 bits (2 bits) - 3 bits (3 bits) applied to the code driver 1n-I, Rm 2. Lum 3゜RB
l l 几B2+几113. HICII 几c2. R
c3 allows the high levels of A, B, and C to be different, and the low levels to be the same. A,,B,C and A,B,
Depending on each level with C and VR, SWI, SW2゜SW3
. . . sequentially turns on the current switches of the output stage. A, B, C and A, B, C are R, 4I.

Ril, Rcl, etc. and the parasitic capacitance of the transistor deteriorate the rising and falling waveforms. The larger the time constants of the rising and falling waveforms, the more glitches will occur in the analog output waveform of the output stage. In order to remove glitches, a latch circuit made up of four transistors is turned on and off using φ and φ, thereby suppressing the occurrence of glitches due to sensitivity of the time constant. Assuming that the rise and fall times of the output waveform of the decode driver are T2, the clocks φ and φ of the latch circuit are set to be in the hold mode when the rise and fall are correct, and are set to the sample mode when they are not. Let τ be the time from the moment the latch circuit switches from the hold mode to the sample mode until 5W1 (SWI) etc. settle.

φ and φ are determined so that τ3 and τ2 do not overlap.

The case where the upper m bits are 3 bits is explained, but in general, the smaller m is, the smaller the parasitic capacitance caused by the transistor can be. becomes smaller. The latch circuit prevents glitches and FL-
This helps eliminate both glitches based on differences in the weights of the 2R ladder.

Further, φ and φ can be adjusted to match the time difference between the driver and the segment decoder shown in FIG.

〔Effect of the invention〕

According to the present invention, there are the following effects.

(1) Glitches caused by variations in the output waveform of the decode driver can be removed.

(2) Dalits caused by switching between the upper m bits and the lower n bits can be removed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a main part of a DA converter according to the prior art and the present invention, FIG. 2 is a circuit diagram of a main part of a DA converter according to the present invention, and FIG.

Claims (1)

[Claims] Digital data input means, an input circuit which takes digital data as input, and whose outputs have low levels of the same level and whose high levels decrease sequentially from the most significant bit to the least significant bit; A decoding circuit controlled by the output signal of the input circuit, a constant current source selectively switched by the decimal encoded digital output from the decoding circuit, and means for adding the selected constant current and taking it out as an analog current output. A segment type digital-to-analog converter comprising a segment type digital-to-analog converter, characterized in that the decoder circuit has a latch function.