JPH01133424A - Da converting circuit - Google Patents
Da converting circuitInfo
- Publication number
- JPH01133424A JPH01133424A JP29241387A JP29241387A JPH01133424A JP H01133424 A JPH01133424 A JP H01133424A JP 29241387 A JP29241387 A JP 29241387A JP 29241387 A JP29241387 A JP 29241387A JP H01133424 A JPH01133424 A JP H01133424A
- Authority
- JP
- Japan
- Prior art keywords
- bits
- digital signal
- circuit
- decoder
- resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 24
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、デジタル信号をアナログ信号に変換する為の
ＤＡ変換回路に関するもので、特に変換部を構成する素
子の素子数を大幅に削減したＤＡ変換回路に関する。Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a DA conversion circuit for converting a digital signal to an analog signal, and in particular significantly reduces the number of elements constituting the conversion section. The present invention relates to a DA conversion circuit.
（ロ）従来の技術
昭和５８年９月２５日付でオーム社より発行された’Ａ
／Ｄコンバータ入門」第１５２頁及び第１５３頁には、
抵抗分割型のＤＡ変換回路が記載されている。前記抵抗
分割型のＤＡ変換回路は、第２図に示す如く、基準電圧
端子（１）とアース間に複数の抵抗（２１）、（２ｔ）
・・・（２ｎ）を直列接続し、前記複数の抵抗（２＋）
、（２＊）・・・（２ｎ）の接続点に複数のスイッチ（
Ｓ、）、（ａｔ）・・・（３ｎ）の一端を接続し、前記
複数のスイッチ（３ｔ）、（３＊）・・・（３ｎ）の他
端を共通にアンプ（４）の入力端に接続し、前記複数の
スイ・７チ（３，）、（３ｔ）・・・（３ｎ）をデコー
ダ（５）の出力信号により制御し、入力端子（６）に印
加されるデジタル信号に応じたアナログ信号を出力端子
（７）に得るものである。この抵抗分割型のＤＡ変換回
路は、比較的精度が良く、本質的に単調性が確保される
という長所がある為、現在多用されている。(b) Conventional technology 'A published by Ohmsha on September 25, 1980
/D Converter Introduction” pages 152 and 153,
A resistance division type DA conversion circuit is described. As shown in FIG. 2, the resistance division type DA conversion circuit has a plurality of resistors (21) and (2t) between the reference voltage terminal (1) and the ground.
...(2n) are connected in series, and the plurality of resistors (2+) are connected in series.
, (2*)...(2n) have multiple switches (
S, ), (at)...(3n) are connected, and the other ends of the plurality of switches (3t), (3*)...(3n) are commonly connected to the input terminal of the amplifier (4). The plurality of switches (3,), (3t)...(3n) are controlled by the output signal of the decoder (5), and in response to the digital signal applied to the input terminal (6). The output terminal (7) is used to obtain an analog signal. This resistor-divided type DA conversion circuit is currently widely used because it has relatively high accuracy and essentially ensures monotonicity.
（ハ）発明が解決しようとする問題点
しかしながら、前記第２図のＤＡ変換回路は、入力デジ
タル信号のビット数に応じて直列抵抗（２＋）、（２＊
）・・・（２ｎ）及びスイッチ（３，）、（ａｔ）・・
・（３ｎ）の個数が決まる為、前記入力デジタル信号の
ビット数が多くなると、前記抵抗及びスイッチの個数が
多くなり、実現が困難になるという問題があった。(c) Problems to be Solved by the Invention However, the DA converter circuit shown in FIG. 2 has series resistors (2+), (2*
)...(2n) and switch (3,), (at)...
- Since the number of (3n) is determined, there is a problem that as the number of bits of the input digital signal increases, the number of resistors and switches increases, making implementation difficult.
例えば最近のデジタルオーディオ分野等においては、１
６ビツトのＤＡ変換回路が使用されているが、１６ビツ
トの場合、抵抗及びスイッチの数がそれぞれ６５５３６
個必要となる。For example, in the recent digital audio field, 1
A 6-bit DA conversion circuit is used, but in the case of 16-bit, the number of resistors and switches is 65536 each.
pcs are required.
（ニ）問題点を解決するための手段
本発明は、上述の点に鑑み成されたもので、入力デジタ
ル信号を上位ビット及び下位ビットに分離する手段と、
分離きれた上位ビット及び下位ビットのデジタル信号を
それぞれデコードする第１及び第２デコーダと、該第１
及び第２デコーダの出力信号に応じて上位ビット及び下
位ビットのデジタル信号にそれぞれ対応するアナログ電
圧を発生する第１及び第２変換部と、該第１及び第２変
換部の出力信号を加算する加算回路とを設け、前記第１
変換部の基準電圧をＶｒに、前記第２変換部の基準電圧
をＶｒ／２’に設定したことを特徴とする。(d) Means for solving the problems The present invention has been made in view of the above points, and includes means for separating an input digital signal into upper bits and lower bits;
first and second decoders that respectively decode the separated upper bit and lower bit digital signals;
and first and second converters that generate analog voltages respectively corresponding to the upper bit and lower bit digital signals according to the output signal of the second decoder, and add the output signals of the first and second converters. an adder circuit, the first
The present invention is characterized in that the reference voltage of the converter is set to Vr, and the reference voltage of the second converter is set to Vr/2'.
（＊）作用
本発明に依れば、入力デジタル信号を２つに分け、それ
ぞれアナログ信号に変換した後加算する様にしているの
で、変換部を構成する抵抗及びスイッチの個数を大幅に
削減することが出来る。(*) Effect According to the present invention, the input digital signal is divided into two parts, each converted into an analog signal, and then added, so the number of resistors and switches that make up the conversion section can be significantly reduced. I can do it.
（へ）実施例
第１図は、本発明の一実施例を示す回路図で、（８）は
入力デジタル信号が印加される入力端子、（９）は前記
デジタル信号の上位ビットを選択する第１選択回路、（
１０）は前記デジタル信号の下位ビットを選択する第２
選択回路で、前記第１及び第２選択回路（９）及び（１
０）は、分離手段を構成している。また、（１１）は前
記第１選択回路（９）の出力信号をラッチする第１ラッ
チ回路、（１２）は前記第２選択回路（１０）の出力信
号をラッチする第２ラッチ回路、（１３）は前記第１ラ
ッチ回路（１１）の出力をデコードする第１デコーダ、
（１４）は前記第２ラッチ回路（１２）の出力をデコー
ドする第２デコーダ、（長）は第１基準電圧端子（１６
）とアースとの間に直列接続された第１乃至第４抵抗（
１７）乃至（２９）と一端が前記第１乃至第４抵抗（１
７）乃至（２０）の各接続点に接続され、他端が共通接
続された第１乃至第４スイツチ（２１）乃至（２４）と
から成る第１変換部、（亜）は第２基準電圧端子（２６
）とアースとの間に直列接続された第５乃至第８抵抗（
２７）乃至（３０）と一端が前記第５乃至第８抵抗（２
７）乃至（３０）の各接続点に接続され、他端が共通接
続された第５乃至第８スイツチ（３１）乃至（３４）と
から成る第２変換部、（３５）は前記第１及び第２変換
部（長）及び（翻）の出力信号を加算する加算回路、及
び（３６）は出力アナログ信号が得られる出力端子であ
る。(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which (8) is an input terminal to which an input digital signal is applied, and (9) is a terminal for selecting the upper bit of the digital signal. 1 selection circuit, (
10) is a second selector for selecting the lower bits of the digital signal.
a selection circuit, the first and second selection circuits (9) and (1);
0) constitutes a separation means. Further, (11) is a first latch circuit that latches the output signal of the first selection circuit (9), (12) is a second latch circuit that latches the output signal of the second selection circuit (10), and (13) ) is a first decoder that decodes the output of the first latch circuit (11);
(14) is a second decoder that decodes the output of the second latch circuit (12); (long) is the first reference voltage terminal (16);
) and the ground, the first to fourth resistors (
17) to (29), one end of which is connected to the first to fourth resistors (1
7) A first conversion unit consisting of first to fourth switches (21) to (24) connected to each connection point of (20) and whose other ends are commonly connected; (sub) is a second reference voltage; Terminal (26
) and the ground, the fifth to eighth resistors (
27) to (30) and one end of which is connected to the fifth to eighth resistors (27) to (30).
7) A second conversion section consisting of fifth to eighth switches (31) to (34) connected to each of the connection points of (30) and whose other ends are commonly connected; An adder circuit adds the output signals of the second converter (long) and (trans), and (36) is an output terminal from which an output analog signal is obtained.
いま、入力デジタル信号を４ビツトとすれば、上位２ビ
ツトのデジタル信号が第１選択回路（９）で選択され、
第１ラッチ回路（１１）でラッチされ、第１デコーダ（
１３）に印加される。また、下位２ビツトのデジタル信
号が第２選択回路（１０）で選択きれ、第２ラッチ回路
（１２）でラッチされ、第２デコーダ（１４）に印加さ
れる。前記第１及び第２デコーダ（１３）及び（１４）
は、２ビツトのデジタル信号をデコードし、第１乃至第
４スイツチ（２１）乃至（２４）及び第５乃至第８スイ
ツチ（３１）乃至（３４）を開閉制御する為の第１及び
第２制御信号を発生する。Now, if the input digital signal is 4 bits, the upper 2 bits of the digital signal are selected by the first selection circuit (9),
It is latched by the first latch circuit (11), and the first decoder (
13). Further, the lower two bits of the digital signal are selected by the second selection circuit (10), latched by the second latch circuit (12), and applied to the second decoder (14). the first and second decoders (13) and (14);
are first and second controls for decoding a 2-bit digital signal and controlling opening/closing of the first to fourth switches (21) to (24) and the fifth to eighth switches (31) to (34). Generate a signal.
すなわち、前記第１及び第２デコーダ（１３）及び（１
４）は、それぞれ２ビツトのデジタル信号「００」、「
０１」、「１０」、「１１」を４種類の制御信号’ｏｏ
ｏｉハｒｏｏｉｏハ’０１００．、’ｔｏｏｏ、に変換
するものである。その為、例えば第１デコーダ（１３）
に「１０」のデジタル信号が印加された場合には、’０
１００．の制御信号が発生し、第２スイツチ（２２）が
閉となり、また第２デコーダ（１４）に「０１」のデジ
タル信号が印加された場合には、’００１０．の制御信
号が発生し、第７スイツチ（３３）が閉となる。その場
合、第１乃至第４抵抗（１７）乃至（２０）の値を等し
く設定するとともに、第１基準寛圧端子（１６）にＶｒ
の基準電圧を印加すれば、第１変換部（長）の出力電圧
Ｖ、は、となる。また、第５乃至第８抵抗（２７）乃至
（３０）の値を等しく設定するとともに、第２基準電圧
端子（２６）にＶｒ １ ／ ４の基準電圧を印加すれ
ば、第２変換部（翻）の出力型、ｔＥ ｖ ＊は、とな
る。その為、加算回路（３５）の出力信号Ｖ、は、とな
る、従って、入力デジタル信号が「１００１、の場合、
出力アナログ信号は９Ｖｒ／１６となる。That is, the first and second decoders (13) and (1
4) are 2-bit digital signals "00" and "00", respectively.
01", "10", and "11" as four types of control signals 'oo
oi ha rooio ha'0100. , 'toooo'. Therefore, for example, the first decoder (13)
When a digital signal of "10" is applied to '0',
100. When a control signal of '0010. A control signal is generated, and the seventh switch (33) is closed. In that case, the values of the first to fourth resistors (17) to (20) are set equal, and the first reference voltage terminal (16) is connected to Vr.
If a reference voltage of V is applied, the output voltage V of the first converting section (long) is as follows. Furthermore, if the values of the fifth to eighth resistors (27) to (30) are set equal and a reference voltage of Vr 1/4 is applied to the second reference voltage terminal (26), the second conversion unit (conversion unit) )'s output type, tE v *, is as follows. Therefore, the output signal V of the adder circuit (35) is as follows. Therefore, when the input digital signal is "1001",
The output analog signal will be 9Vr/16.
第１図のＤＡ変換回路の場合、第１変換部（坏）の抵抗
及びスイッチの個数は第１選択回路（９）の選択ビット
数Ｎ、に対し、２Ｎ１個に設定される。すなわち、Ｎ１
−２とすれば、抵抗及びスイッチの個数はそれぞれ４個
となる。また、第２変換部り翻）の抵抗及びスイッチの
個数も第２選択回路（１０）の選択ビット数をＮ、とす
れば、２Ｎ！個となる。更に、第１変換部（す）の基準
電圧をＶｒとすれば、第２変換部（翻）の基準電圧はＶ
ｒ／ ２”となる。従って、第１及び第２変換部（す）
及び（翻〉の抵抗及びスイッチのトータル個数は（２Ｎ
Ｉ ＋ ２Ｎ ｔ ）個となる。In the case of the DA converter circuit shown in FIG. 1, the number of resistors and switches in the first converter is set to 2N1 for the number N of selected bits in the first selection circuit (9). That is, N1
-2, the number of resistors and switches will be four each. Furthermore, the number of resistors and switches in the second converter (transformed by the second converter) is also 2N, assuming that the number of selection bits of the second selection circuit (10) is N! Become an individual. Furthermore, if the reference voltage of the first converter is Vr, the reference voltage of the second converter is Vr.
r/2". Therefore, the first and second converters
The total number of resistors and switches is (2N
I + 2N t ) pieces.
ちなみに、第２図の従来のＤＡ変換回路においては、２
（Ｎ１＋Ｎり個の抵抗及びスイッチを必要とする。By the way, in the conventional DA conversion circuit shown in Fig. 2, 2
(Requires N1+N resistors and switches.
上述の如く、第１図のＤＡ変換回路を用いれば、従来の
ＤＡ変換回路に比べ、抵抗及びスイッチの数を大幅に削
減出来、これは入力デジタル信号のビット数が増加する
ほど顕著となる。例えば、入力デジタル信号を１６ビツ
トとした場合、第２図のＤＡ変換回路は、抵抗及びスイ
ッチをそれぞれ６５５３６個必要とするのに対し、第１
図のＤＡ変換回路は抵抗及びスイッチをそれぞれ５１２
個用いればよい。尚、実施例の場合は、入力デジタル信
号を上位、下位２つに分けた場合について説明したがζ
人力デジタル信号を３以上に分離してもよく、その場合
、下位ビットの基準電圧は、全ビット数から下位ビット
数を減算した値を犯とすればよい。As mentioned above, by using the DA conversion circuit of FIG. 1, the number of resistors and switches can be significantly reduced compared to the conventional DA conversion circuit, and this becomes more noticeable as the number of bits of the input digital signal increases. For example, when the input digital signal is 16 bits, the DA conversion circuit shown in Fig. 2 requires 65536 resistors and 65536 switches.
The DA conversion circuit in the figure has 512 resistors and switches each.
Just use one. In the case of the embodiment, the case where the input digital signal is divided into upper and lower two is explained, but ζ
The human digital signal may be separated into three or more parts, and in that case, the reference voltage of the lower bits may be a value obtained by subtracting the number of lower bits from the total number of bits.
（ト）発明の効果
以上述べた如く、本発明に依れば、抵抗分割型のＤＡ変
換回路を用いる場合、抵抗及びスイッチの個数を大幅に
削減することが出来る。その為、特に入力デジタル信号
のビット数が多いデジタルオーディオ分野に用いて好適
である。(G) Effects of the Invention As described above, according to the present invention, when using a resistance division type DA conversion circuit, the number of resistors and switches can be significantly reduced. Therefore, it is particularly suitable for use in the digital audio field where the number of bits of the input digital signal is large.
第１図は、本発明の一実施例を示す回路図、及び第２図
は従来のＤＡ変換回路を示す回路図である。
（９）、 （１０）・・・選択回路１． （１３）、（
１４）・・・デコーダ、 （長）、（翻）・・・変換部
、 （１７）乃至（２０）、（２７）乃至（３０）・・
・抵抗、 （２１）乃至（２４）、（３１）乃至（３４
）０．・スイッチ、 （３５）・・・加算回路。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional DA conversion circuit. (9), (10)...Selection circuit 1. (13), (
14)...decoder, (long), (translation)...conversion unit, (17) to (20), (27) to (30)...
・Resistance, (21) to (24), (31) to (34
)0.・Switch, (35)...addition circuit.
Claims (1)
分離する手段と、分離された上位ビットのデジタル信号
をデコードする第１デコーダと、分離された下位ビット
のデジタル信号をデコードする第２デコーダと、前記第
１デコーダの出力信号に応じて前記上位ビットのデジタ
ル信号に対応するアナログ電圧を発生する第１変換部と
、前記第２デコーダの出力信号に応じて前記下位ビット
のデジタル信号に対応するアナログ電圧を発生する第２
変換部と、前記第１及び第２変換部の出力信号を加算す
る加算回路とから成り、前記第１変換部の基準電圧をＶ
ｒとするとき、前記第２変換部の基準電圧をＶｒ／２＾
Ｎ（ただし、Ｎは前記上位ビットのデジタル信号のビッ
ト数）に設定したことを特徴とするＤＡ変換回路。(1) means for separating an input digital signal into upper bits and lower bits; a first decoder that decodes the separated upper bit digital signal; and a second decoder that decodes the separated lower bit digital signal; a first converter that generates an analog voltage corresponding to the upper bit digital signal according to the output signal of the first decoder; and an analog voltage corresponding to the lower bit digital signal according to the output signal of the second decoder. the second which generates the voltage;
It consists of a conversion section and an addition circuit that adds the output signals of the first and second conversion sections, and sets the reference voltage of the first conversion section to V.
When r, the reference voltage of the second conversion section is Vr/2^
N (where N is the number of bits of the digital signal of the upper bits).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29241387A JPH01133424A (en) | 1987-11-19 | 1987-11-19 | Da converting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29241387A JPH01133424A (en) | 1987-11-19 | 1987-11-19 | Da converting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01133424A true JPH01133424A (en) | 1989-05-25 |
Family
ID=17781464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29241387A Pending JPH01133424A (en) | 1987-11-19 | 1987-11-19 | Da converting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01133424A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0594159A (en) * | 1991-04-26 | 1993-04-16 | Matsushita Electric Ind Co Ltd | Liquid crystal driving device |
| JPH06202596A (en) * | 1993-01-07 | 1994-07-22 | Nec Corp | Liquid crystal driving circuit |
| WO2001041311A1 (en) * | 1999-11-30 | 2001-06-07 | Yamaha Corporation | Digital-to-analog converter |
| JP2007041537A (en) * | 2005-08-04 | 2007-02-15 | Korea Advanced Inst Of Science & Technol | Digital to analog converter using time division sampling for driving flat panel display, method of implementing the same, and data driver circuit using the same |
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|---|---|---|---|---|
| JPS5610738A (en) * | 1979-07-09 | 1981-02-03 | Yokogawa Hokushin Electric Corp | Digital-to-analog converter |
| JPS56146326A (en) * | 1980-04-16 | 1981-11-13 | Sanyo Electric Co Ltd | Digital-to-analog converter |
| JPS58133031A (en) * | 1982-02-02 | 1983-08-08 | Toshiba Corp | Digital-analog conversion circuit |
| JPS61107816A (en) * | 1984-10-31 | 1986-05-26 | Fuji Electric Co Ltd | Digital-analog converting circuit |
-
1987
- 1987-11-19 JP JP29241387A patent/JPH01133424A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5610738A (en) * | 1979-07-09 | 1981-02-03 | Yokogawa Hokushin Electric Corp | Digital-to-analog converter |
| JPS56146326A (en) * | 1980-04-16 | 1981-11-13 | Sanyo Electric Co Ltd | Digital-to-analog converter |
| JPS58133031A (en) * | 1982-02-02 | 1983-08-08 | Toshiba Corp | Digital-analog conversion circuit |
| JPS61107816A (en) * | 1984-10-31 | 1986-05-26 | Fuji Electric Co Ltd | Digital-analog converting circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0594159A (en) * | 1991-04-26 | 1993-04-16 | Matsushita Electric Ind Co Ltd | Liquid crystal driving device |
| JPH06202596A (en) * | 1993-01-07 | 1994-07-22 | Nec Corp | Liquid crystal driving circuit |
| WO2001041311A1 (en) * | 1999-11-30 | 2001-06-07 | Yamaha Corporation | Digital-to-analog converter |
| JP2007041537A (en) * | 2005-08-04 | 2007-02-15 | Korea Advanced Inst Of Science & Technol | Digital to analog converter using time division sampling for driving flat panel display, method of implementing the same, and data driver circuit using the same |
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