JPH04418B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a digital-to-analog (D/A) conversion circuit that converts a multi-bit (N) digital signal, each having a certain weight, into an analog signal represented by ^2N voltage levels. In particular, the present invention relates to a D/A conversion circuit that performs D/A conversion using a voltage dividing circuit consisting of a resistor network in which a large number of resistors are connected in series. [Background technology and its problems] In general, D/
When converting an N-bit digital signal into an analog signal represented by ^2N voltage levels, a D/A conversion circuit that performs A conversion conventionally uses a resistor network consisting of ^2N resistors connected in series. The reference voltage is divided into ^2N stages by the decoding output of the N-bit decoder that decodes the N-bit digital signal, and the ^2N switches are controlled by the decoding output of the ^N -bit digital signal. It was configured to output levels selectively. In the 2-bit D/A converter circuit shown in FIG. 1, which shows the basic circuit configuration of a conventional D/A converter circuit, four resistors 2A and 2B are connected in series between the ground and the reference input terminal 1. , 2C, and 2D. The above four resistors 2A, 2
B, 2C, and 2D have mutually equal resistance values,
The reference voltage V _REF supplied to the reference input terminal 1 is divided into four, and 0V _REF , 1/4V _REF , 1/2V _REF , 3/4V
The four levels of signal levels of _REF are set at each output terminal 3a, 3b, 3.
A voltage dividing circuit 3 is configured to apply voltages to voltages c and 3d. Four switches 5A, 5 are provided between each output terminal 3a, 3b, 3c, 3d of the voltage dividing circuit 3 and the analog signal output terminal 4.
B, 5C, and 5D are controlled by respective decode outputs X ₀ , _{X 1 ,} X ₂ , and X ₃ of a 2-bit decoder 6 that decodes 2-bit B 0 and B ₁ digital signals. The 2-bit decoder 6 receives the 2-bit B ₀ ,
Decode the digital signal of B ₁ and get X ₀ = ₀・
₁ , X ₁ = B ₀ · _{1 ,} X ₂ = ₀ · B ₁ , _{and X 3 =} B ₀ · B ₁ . The 2-bit decoder ₆ uses the first decoding output
control the first switch _5A provided between the
When B ₀ =0 and B ₁ =0, the first switch 5
Close A. Similarly, the decoder 6
are the second and third decoding outputs X ₁ , X ₂ , X ₃
When the logic is "1", the second to fourth switches 5B, 5C, and 5D are closed. In the 2-bit D/A conversion circuit shown in FIG. 1 as described above, as shown in Table 1, an analog signal with four signal levels obtained by converting a 2-bit digital signal into an analog signal is obtained at the signal output terminal 4. It will be done.

[Purpose of the invention]

Therefore, in view of the above-mentioned problems with conventional D/A conversion circuits, the present invention aims to reduce the number of circuit components and makes it possible to integrate a multi-bit D/A conversion circuit with a small chip size. The present invention provides a D/A conversion circuit with a new configuration. [Summary of the Invention] In order to achieve the above-mentioned object, a D/A conversion circuit according to the present invention provides a D/A conversion circuit that connects a decoder that decodes an N-bit digital signal, a reference input terminal to which a reference voltage is applied, and the ground. A voltage divider circuit consisting of 2N ^-1 resistors connected in series is connected between each of the (2N ^-1 +1) output terminals of the voltage divider circuit and the analog signal output terminal, and A switching device consisting of (2 ^N-1 +1) analog switches each having an on-resistance sufficiently larger than the resistance value of each of the above-mentioned resistors, which is determined according to the linearity allowed for the output from the signal output terminal. circuit, selectively controlling each analog switch of the switching circuit by the decoded output of the decoder, and controlling each of the (2 ^N-1 +1) analog switches constituting the voltage dividing circuit. By closing two analog switches connected to each output terminal on both ends of the resistor at the same time or closing one of them, an N-bit digital signal is converted to an analog signal represented by 2 ^N voltage levels. It is characterized in that it is output from a signal output terminal. [Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 3 is a circuit diagram showing an embodiment of a 2-bit D/A conversion circuit, and shows the basic circuit configuration of the D/A conversion circuit according to the present invention. In FIG. 3, 21 is the first data input terminal to which the lower bit _B0 of the 2-bit _B0 , _B1 digital signal is supplied, and 22 is the upper bit as well.
B ₁ is the second data input terminal supplied.
Further, 23 is a reference input terminal to which a reference voltage V _REF is applied, and 24 is an analog signal output terminal. In the 2-bit D/A conversion circuit shown in FIG. 3, ^{2N-1 resistors 25A and} 25B, that is, two resistors 25A and 25B, having mutually equal resistance values R are connected in series between the ground and the reference input terminal 23. ing. Above 2
The resistors 25A and 25B are connected to the reference input terminal 2.
Divide the reference voltage V _REF applied to 3 into two, 0V _REF ,
A voltage dividing circuit 26 is configured to provide signal levels in (2 ^N-1 +1) stages, ie, three stages, 1/2 V _{REF and V REF .} Each output terminal 26a, 26b, 26 of the voltage divider circuit 26 which provides the above-mentioned three levels of signal levels.
c is connected to the analog signal output terminal 24 through three analog switches 27A, 27B, and 27C, each having an on-resistance r that is sufficiently larger than the resistance value R of each of the resistors 25A and 25B.
Then, the three analog switches 27A, 2
7B and 27C are, for example, MOS (Metal Oxide)
The decode outputs _{X 0 , X 1} , _and It is becoming more and more controlled. The _decoder 28 decodes the 2 _{- bit B 0 , B 1} digital _signal to obtain X ₀ = _{0.1 +} B _{0.1 = 1} Outputs decoded outputs _{X 0} , X ₁ , and X _{2 where 0}・₁ +B ₁ X ₂ =B 0・B 1. The decoder 28 then outputs its first decoded output.
X ₀ controls the first analog switch 27A between the first output terminal 26a of the voltage dividing circuit 26 and the analog signal output terminal 24, and
The first analog switch 27A is closed when the decoded output _X0 of is logic "1". Similarly, the decoder 28 controls the second and third analog switches 27B and 27C using its second and third decode outputs X ₁ and X ₂ . Table 2 shows the operation of the 2-bit D/A conversion circuit configured as described above.

[Table] That is, in this embodiment, each bit B 0 _{and B 1 of} the digital signal supplied to the first and second data input terminals 21 and 22 are both logic "0".
, the first decoded output ^X0 of the decoder 28 causes the first analog switch 27A to
is closed. Therefore, the first voltage divider circuit 26
A signal level of 0V _REF at the output terminal 26a of is applied to the analog signal output terminal 24. Also, each bit B ₀ and B ₁ of the above digital signal is
When B ₀ =1 and B ₁ =0, the first and second analog switches 27 are controlled by the first and second decoded outputs X ₀ and X ₁ of the decoder 28.
A and 27B are closed. Here, in this embodiment, each resistor 25 constituting the voltage dividing circuit 26
Analog switches 27A, 27B, 27C whose on-resistance r is sufficiently larger than the resistance value R of A, 25B
each output terminal 26 of the voltage divider circuit 26 via
a, 26b, 26c and analog signal output terminal 24
Since the first and second analog switches 27A and 27B are both closed, the first output terminal 26 of the voltage dividing circuit 26
A signal level of 1/4 V _REF , that is, _1/2 of the potential difference between the potential 0 V _REF of a and the 1/2 V REF of the second output terminal 26 b is applied to the analog signal output terminal 24 . Each of the above analog switches 27A, 27B, 27
The value of each on-resistance r of C is determined according to the linearity allowed for the output from the analog signal output terminal 24, and for example, each of the resistors 25A and 25B constituting the dividing circuit 26 By setting the resistance value to five times the resistance value R of , it is possible to ensure linearity of about 10% in the output from the analog signal output terminal 24 . Furthermore, each bit B ₀ , B ₁ of the above digital signal
When B ₀ =0 and B ₁ =1, the second decode output _X1 causes the second analog switch 27
B is closed, and a signal level of 1/2V _REF is applied to the analog signal output terminal 24. Furthermore, each bit B ₀ ,
When both B ₁ are logic "1", the second and third decode outputs X ₁ and X ₂ close the second and third analog switches 27B and 27C, and the signal level becomes 3/4V _REF . The signal is applied to the analog signal output terminal 24. Therefore, at the analog signal output terminal 24,
The 2-bit B ₀ and B ₁ digital signals supplied to the first and second data input terminals 21 and 22 are set to four voltage levels (0V _REF , 1/4V _REF , 1/2V _REF , 3
/4 V _REF ) can be obtained. The embodiment shown in FIG. 3 above is a 2-bit D/A conversion circuit having the basic circuit configuration of the D/A conversion circuit according to the present invention, but the present invention is limited to the above embodiment. Instead, it can be applied to an N-bit D/A conversion circuit that converts an N-bit digital signal into an analog signal represented by ^2N voltage levels. The embodiment shown in FIG. 4 corresponds to the conventional 4-bit D/A conversion circuit shown in FIG.
4 bits B ₀ , B ₁ , supplied to 2, 33, 34
Two decoders 35A, 35B decode the digital signals of B ₂ and B ₃ , and the decoder 35A,
Eight resistors 38A,
It is equipped with a voltage dividing circuit 39 formed by connecting 38B...38H in series, and operates as shown in Table 3.

〔Effect of the invention〕

As is clear from the description of the embodiments described above, according to the present invention, a D/A conversion circuit that converts a multi-bit digital signal into an analog signal can be configured with a small number of elements, so that it is possible to configure a D/A conversion circuit that is suitable for integration into an integrated circuit. A conversion circuit can be provided, and the intended purpose can be fully achieved.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing the configurations of conventional D/A conversion circuits. FIG. 1 shows a 2-bit D/A conversion circuit, and FIG. 2 shows a 4-bit D/A conversion circuit.
A conversion circuit is shown. FIG. 3 is a circuit diagram showing the basic circuit configuration of the D/A conversion circuit according to the present invention, and shows an embodiment of the 2-bit D/A conversion circuit. FIG. 4 is a circuit diagram showing an embodiment of a 4-bit D/A conversion circuit. 21, 22, 31, 32, 33, 34...Data input terminal, 23, 37...Reference input terminal, 2
4, 40...Analog signal output terminal, 25A, 2
5B, 38A, 38B...38H...Resistance, 2
6, 39... Voltage divider circuit, 27A, 27B, 2
7C, 37A, 37B... 37L... Analog switch, 28, 35A, 35B... Decoder.

Claims (1)

[Claims] A voltage divider circuit comprising a decoder that decodes a 1N-bit digital signal, and ^2N-1 resistors connected in series between a reference input terminal to which a reference voltage is applied and the ground. , connected between each of the (2 ^N-1 +1) output terminals of the voltage divider circuit and the analog signal output terminal, and determined according to the linearity allowed for the output from the analog signal output terminal. A switching circuit consisting of (2 ^N-1 +1) analog switches each having an on-resistance sufficiently larger than the resistance value of each of the above-mentioned resistors, and each analog switch of the above-mentioned switching circuit is equipped with a decode output of the above-mentioned decoder. of the (2N ^-1 +1) analog switches connected to each output terminal at both ends of each resistor constituting the voltage divider circuit. 1. A digital-to-analog conversion circuit, which converts an N-bit digital signal into an analog signal represented by ^2N voltage levels at the same time or by closing one circuit, and outputs the analog signal from an output terminal.