JP2797349B2 - A / D converter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AD converter, and more particularly, to an AD converter formed on a semiconductor chip.

[Conventional technology]

Conventionally, this type of A / D converter includes a load resistor R and ladder resistors r _{1 to} r ₃ connected in series between a power supply terminal 1 of a power supply V _DD and a ground terminal, as shown in FIG. Comparators 2 and 3 are provided.

Load resistor R and the ladder resistor r ₁ ~r ₃ by divided voltage V ₁ ~V ₃ and the output D of the 2-bit compared by the comparator 2 and voltage input from the input terminal 4 of the analog signal _1, I was getting D _2. However, the voltage of the analog signal at the input terminal 4 is the voltage
When V ₂ is greater than, the decoding switches 5 to connect the voltages V ₁ to the comparator 2, compares the voltage V ₃ is smaller than the voltage V ₂ unit 2
Connect to

[Problems to be solved by the invention]

Since the above-described conventional AD converter uses a ladder resistor, even if the semiconductor process is miniaturized, the layout of the ladder resistor cannot be simply reduced in order to obtain a predetermined resistance value. However, there is a disadvantage that the miniaturization of the semiconductor chip is hindered. In addition, there is a drawback that layout restrictions are imposed to make each ladder resistance value uniform.

[Means for solving the problem]

The A / D converter of the present invention comprises a plurality of MOS transistors each having a different channel length and connected in series in the order of the channel length.
It comprises a transistor and at least one full adder for adding the outputs of the respective MOS transistors.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram of a first embodiment of the present invention.

As shown in FIG. 1, the first embodiment is a 2-bit output A / D converter, which is pulled up from a power supply terminal 1 of a power supply voltage V _DD via pull-up resistors R _{1 to} R _3. including the N-channel type MOS transistors Q ₁ to Q ₃ of which are connected in series to the channel length sequence with different channel lengths, the full adder FA1 for adding the output of each of the MOS transistors Q ₁ to Q _3.

The channel length of the MOS transistors Q ₁ to Q ₃ is not increased in the order of the MOS transistors _{Q 1, Q 2, Q 3} , the channel width is the same. Therefore, the magnitude of the threshold voltage corresponds to the magnitude of the channel length. The gates of the MOS transistors Q _{1 to} Q ₃ are connected to an analog signal input terminal 4.

Now, upon application of a voltage of the analog signal to the input terminal 4, each of the MOS transistors Q ₁ transistor exceeds the threshold voltage of the to Q ₃ are input terminals A~ of the full adder FA1 sequentially become conductive state of MOS transistors Q ₁ Three-bit information is obtained in C. When this is fully added by full adder FA1, 2-bit outputs ₁ , ₂ of the truth values shown in Table ₁ are output.

 FIG. 2 is a circuit diagram of a second embodiment of the present invention.

As shown in FIG. 2, in the second embodiment, a 3-bit output is obtained, and N-channel MOS transistors Q _{1 to} Q _{7 are used.}
Channel length of They become sequentially larger from MOS transistors Q _1, the channel width is the same. Therefore, the magnitude of the threshold voltage corresponds to the magnitude of the channel length.

Now, when the voltage of the analog signal is applied to the input terminal 4,
Among the MOS transistors Q _{1 to} Q _7, the transistors exceeding the threshold voltage are sequentially turned on from the MOS transistor Q _1, and the input terminals A to C of the full adder FA 1 and the input terminals EG of the full adder FA 2 are connected. 7-bit information is obtained at the input terminal D of the full adder FA3. This 7-bit information is used as a full adder FA
By performing full addition in 1 to FA4, 3-bit outputs ₁ to ₃ of truth values shown in Table 2 are obtained.

[Effects of the Invention] As described above, the present invention has an effect capable of coping with miniaturization and high integration of a semiconductor process by combining MOS transistors having sequentially different channel lengths in series instead of the ladder resistance.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIG. 3 is a circuit diagram of an example of a conventional A / D converter. . 1 ... power supply terminal, 2, 3 ... comparator, 4 ... input terminal, 5
…… Decode switch, FA1 to FA4 …… Full adder, R ……
Load resistor, R ₁ ~R ₇ ...... pull-up resistor, r ₁ ~r ₃ ...... ladder resistance, Q ₁ ~Q ₇ ...... N-channel type MOS transistor.

Claims (5)

(57) [Claims] A MOS transistor string having a plurality of MOS transistors having different channel lengths connected in series in ascending order of channel length, wherein a drain terminal of each MOS transistor is a resistor; Each element is connected to the first reference voltage source by pull-up connection,
The source terminal of the MOS transistor having the shortest channel length of the MOS transistor string is connected to a second reference voltage source, and the gate terminal of each of the MOS transistors is commonly connected to an analog signal input terminal. The drain terminals of the MOS transistors are respectively connected to the addition input terminals of the adder, and the inverted addition output of the adder becomes a digital signal output obtained by AD converting an analog signal supplied to the analog signal input terminal. An A / D converter characterized in that: 2. The A / D converter according to claim 1, wherein said MOS transistor string is composed of three MOS transistors, and said adder is a full adder. 3. The A / D converter according to claim 1, wherein said MOS transistor string is composed of seven MOS transistors, and said adder is a seven-addition input adder composed of four full adders. vessel. 4. Each MOS of said MOS transistor string
The A / D converter according to claim 1, wherein the transistor is an n-channel MOS transistor. 5. The respective MOS transistors of the MOS transistor string.
The A / D converter according to claim 1, wherein the transistor is a p-channel MOS transistor.