JP3090811B2 - D / A converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter used for various electronic devices, and more particularly to a D / A converter suitable for integrated circuits.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional resistive voltage dividing D / A converter. Terminal 51 to which reference voltage Vref is supplied
And 2 ^k between the grounded terminals 52, for example. Resistance R2 ⁰ equal to ~ R2 ^k Are connected in series. Resistance R
2 ⁰ ~ R2 ^k , And a terminal 52 has a switch SW2 ⁰ for extracting a divided voltage. ~ SW2 ^k Are connected to each other. These switches SW2 ⁰ ~ SW
^2k Is connected to an output terminal 54 via an impedance converter 53.

On the other hand, a decoder 56 is connected to an input terminal 55 to which a digital signal DS is supplied. This decoder 56 has the switch SW2 ⁰ ~ SW2 ^k , A logic circuit L2 ⁰ composed of, for example, a NAND circuit or the like. ~ L2 ^k Is provided, and the input terminal 5
5 is supplied to these logic circuits L2
⁰ ~ L2 ^k And the corresponding switch SW2 ⁰ ~ SW2 ^k Is driven, and an analog voltage corresponding to the input digital signal is output from the output terminal 54.

[0004]

In the conventional D / A converter, when the number of bits of input data is increased in order to improve the resolution, the number of resistors increases. Therefore, the number of switches and logic circuits provided corresponding to these resistors also increases. In particular, since a logic circuit has a large number of elements, the increase in the number of logic circuits greatly affects the circuit scale. Therefore, when the number of logic circuits increases, this D
When the / A converter is formed as a MOS LSI, there is a problem that the area occupied by the chip becomes very large and the manufacturing cost rises.

An object of the present invention is to solve the above-mentioned problems. It is an object of the present invention to suppress the increase in the number of resistors and logic circuits and to convert a multi-bit digital signal, thereby suppressing the increase in the area occupied by a chip. D / A suitable for integrated circuits
It seeks to provide a converter.

[0006]

A D / A converter according to the present invention is provided between a first reference power supply and a second reference power supply and has a plurality of resistors connected in series. Are connected in series with each other, control means for controlling connection / disconnection of the extension resistance means to the resistance string circuit according to the number of bits of the digital signal, and an odd number of the resistance string circuit and the extension resistance means. First switch means constituted by a plurality of switches for extracting a divided voltage from each of the third connection points, and a plurality of switches for extracting a divided voltage from each even-numbered connection point of the resistor string circuit and the extended resistance means And the first and second switches according to signals other than the least significant bit or the most significant bit of the digital signal. A first logic circuit for selecting a switch constituting the means, a third switch means connected to the first and second switch means, and a signal corresponding to the least significant bit or the most significant bit of the digital signal. And the third
And a second logic circuit for controlling one of the switch means and selecting one of the first and second switch means.

[0007]

That is, in the present invention, the control means controls connection and disconnection of the extended resistance means to the resistance string circuit according to the number of bits of the digital signal. The first switch means constituted by a plurality of switches extracts a divided voltage from each odd-numbered connection point of the resistor string circuit and the extended resistance means, and the second switch means constituted by the plurality of switches. The means extracts a divided voltage from each even-numbered connection point of the resistor string circuit and the extended resistance means. The first logic circuit selects a switch constituting the first and second switch means in accordance with a signal other than the least significant bit or the most significant bit of the digital signal, and outputs a required amount from the resistance string circuit and the extended resistance means. Take out the voltage. The second logic circuit controls the third switch means connected to the first and second switch means according to the least significant bit or the most significant bit signal of the digital signal. One of the switch means is selected to extract the divided voltage.

[0008]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, a reference voltage Vref is supplied.
The terminal 11 has a first extension circuit for extending the number of bits.
Path 12 is connected, and the number of bits is
A second extension circuit 14 for extension is connected.
Between the first and second extension circuits 12 and 14,
The resistor string circuit 15 is connected. The first
The extension circuit 12 is a switch 1 having one end connected to the terminal 11.
2a, 12b, the other end of the switch 12b and the switch 1
2a connected between the other ends of 2a^L Expansion resistors RL2
⁰ ~ RL2^L And the second extension circuit 14
Are switches 14a, 14 having one end connected to the terminal 13.
b, the other end of the switch 14b and the other end of the switch 14a
2 connected between each other^J Expansion resistors RJ2⁰ ~ RJ2^J
It is constituted by. The resistor string circuit 15
Is 2^K Equal resistors R2⁰ ~ R2^K Are connected in series
Has been continued. The resistor R2⁰ Is the first extension circuit 1
2 and the other end of the switch RL2 and the resistor RL2.^L Connection
The resistor R2^K Is the second extension
The other end of the switch 14a constituting the path 14 and the resistor RJ2⁰ of
Connected to the connection node.

The first and second extension circuits 12 and 14 and the resistor string circuit 15 are connected to first and second switch groups 16 and 17 for extracting a divided voltage. Switch SW2 ⁰ configuring first switch group 16
The end resistance RL2 ⁰ And RL2 ¹ (Not shown), hereinafter referred to as a switch SW2 ^{K-m + 1} Is connected to a resistor R2
⁰ And R2 ¹ Switch SW2 ^Kn The end resistance R2 ^K And the resistance RJ2 ⁰ Switch SW2 ^K Is connected to the terminal 13.

The switches constituting the second switch group 17
Switch SW2^Km One end of the resistor RL2^L _{And the resistor R2}0 of
Connected to the connection point,^Kn-1 One end of
Is the resistor R2^K-1 And R2^K Connected to the connection point of the switch
SW2^K-1 One end of the resistor RJ2^J-1 (Not shown) and resistor RJ
Two^J Connected to the connection point.

The first and second switch groups 16, 17
Is selected by the third switch group 18. That is, the switches SW2 ⁰ constituting the first switch group 16
~ SW2 ^{K-m + 1} ~ SW2 ^Kn ~ Switch SW2 ^K Is connected to one end of a switch SWa forming a third switch group 18, and SW2 forming a second switch group 17.
^Km ~ SW2 ^Kn-1 ~ SW2 ^K-1 Is connected to one end of a switch SWb constituting the third switch group 18. The other ends of these switches SWa and SWb are connected to an output terminal 20 via an impedance converter 19.

On the other hand, a digital signal D
S is supplied. First and second logic circuits 22 and 23 are connected to the input terminal 21. First logic circuit 2
2 decodes bits other than the LSB of the input digital signal DS, selects one of the first and second switch groups 16 and 17 one by one according to the decoded output signal, and turns on and off. I do. This first logic circuit 22
The decoding operation is controlled according to a bit switching signal BCH described later. The second logic circuit 23 selectively controls the switches constituting the third switch group 18 based on the LSB of the digital signal DS, and selects the first switch group 16 or the second switch group 17.

The input terminal 24 is supplied with a bit switching signal BCH. This bit switching signal BCH
, Depending on the number of bits of the digital signal supplied to the input terminal 21, first, the resistance RL2 ⁰ provided in the second expansion circuits 12 and 14 ~ RL2 ^L , Resistance RJ2 ⁰ ~ RJ2 ^J Are connected to the resistor string circuit 15 and the decoding operation of the first logic circuit 22 is specified. The input terminal 24 is connected to a third logic circuit 25. The third logic circuit 24 responds to the input bit switching signal BCH in accordance with the first and second extension circuits 12 and 14.
Switches 12a, 14a or switches 12b, 14
b is selectively controlled. The first logic circuit 22 includes switches 12a and 14 of the first and second extension circuits 12 and 14.
When a is turned on, the first and second switch groups 16,
The switches connected to the first and second extension circuits 12 and 14 are controlled so as not to be selected among the switches constituting the switch 17.

The operation of the above configuration will be described. The D / A converter shown in this embodiment can convert, for example, two types of digital signals by changing the number of resistors connected to the resistor string circuit 15 in accordance with the bit switching signal BCH. it can.

That is, first, the bit switching signal BCH
Depending on, the third logic circuit 25 first, when the switch 12b of the second expansion circuits 12 and 14, and 14b are turned on, one end of the resistor string circuit 15 resistance RL2 ⁰ ~ RL2
^L , Is connected to the terminal 11 via a switch 12b, the other end resistance RJ2 ⁰ of the resistor string circuit 15 ~ RJ2 ^J , And the switch 13b. In this state, 2 ⁿ When a bit digital signal is supplied, the digital signal other than the LSB is decoded by the first logic circuit 22. This first
Switches SW2 ⁰ constituting the first and second switch groups 16 and 17 by the decode output signal output from the logic circuit 22 of FIG. ~ SW2 ^K One of the switches is turned on. At the same time, the second logic circuit 2
3 decodes the LSB of the digital signal, controls the third switch group 18 by this decoded output signal,
First and second switch groups 16 and 17 are selected. Therefore, from the switches that are turned on in the third switch group 18, the resistance RL2 ⁰ ~ RL2 ^L , The resistor string circuit 15,
Resistance RJ2 ⁰ ~ RJ2 ^J Is output from the predetermined position. The extracted divided voltage is output from the output terminal 20 via the impedance converter 19.
That is, the first in response to the digital signal, if the X-th switch of the second switch group 16 and 17 is turned on, XVref / 2 ^K (K = 0, 1, 2, ... 2 ^K-1 ) The following divided voltage is taken out. This voltage is impedance-converted and output from the output terminal 20.

On the other hand, according to the bit switching signal BCH,
The third logic circuit 25 includes first and second extension circuits 12 and 14.
Are turned on, one end of the resistor string circuit 15 is connected to the terminal 1 via the switch 12a.
1 and the other end of the resistor string circuit 15 is connected to the terminal 13 via the switch 14a. In this state, 2 ^m is connected to the input terminal 21. When a digital signal of (m <n) bits is supplied, the digital signal other than the LSB is decoded by the first logic circuit 22.
At this time, the first logic circuit 22 outputs the bit switching signal BC
H, the decoding operation is controlled, and according to digital signals other than the LSB, the first and second switch groups 16, 1
7, the resistor string circuit 15
Select only the switch connected to. That is, a predetermined output connected to the resistor string circuit 15 among the switches forming the first and second switch groups 16 and 17 is set to 1 by the decoded output signal output from the first logic circuit 22. Is turned on. At the same time, the second logic circuit 23 decodes the LSB of the digital signal, controls the third switch group 18 by this decoded output signal, and controls the first and second switch groups 16, 1
Select 7. Therefore, the third switch group 18 outputs a divided voltage extracted from a predetermined position of the resistor string circuit 15. The extracted divided voltage is output from the output terminal 20 via the impedance converter 19.

In the above embodiment, when only the switch corresponding to the resistor string circuit 15 is selected, the first logic circuit 22 is controlled by the bit switching signal BCH. However, the present invention is not limited to this. The digital signal supplied to the input terminal 21 is processed in accordance with the bit switching signal BCH, and the processed digital signal is supplied to the first logic circuit 22, In response to the decoded output signal corresponding to the signal, the resistance string circuit 1
The switch corresponding to 5 may be selected. FIG. 2 shows a case where the present invention is also used for a 3-bit and 2-bit D / A converter, and the same parts as those in FIG. 1 are denoted by the same reference numerals.

In FIG. 1, a first extension circuit 12 is constituted by resistors RL1 and RL2, switches 12a and 12b constituted by a pair of P-channel and N-channel transistors, and a second extension circuit 14 is constituted by resistors RJ1 and RJ2. , And switches 14a and 14b each formed by a pair of P-channel and N-channel transistors.
The resistor string circuit 15 includes resistors R1 to R4.

The third logic circuit 25 includes the inverter circuit 2
5 includes _1, the switch 12a input terminal 24 via a third logic circuit 25, 12b, 14a, and is connected to 14b. That is, the input terminal 24 is connected to the switch 12
a, the gates of the P-channel transistors 14a and 1
2b, is connected to gate of the N-channel transistor 14b, via the inverter circuit 25 ₁ is connected switches 12a, gates and 12b of 14a of the N-channel transistor, the gates of P-channel transistor 14b.

The first and second switch groups 16 and 17 are constituted by switches SW1 to SW8 constituted by a pair of P-channel and N-channel transistors.
One end of each of the switches SW1 to SW7 is connected from the connection point of the resistances RL1 and RL2 to the connection point of the resistances RJ1 and RJ2, respectively, and one end of the switch SW8 is connected to the terminal 13.

The third switch group 18 is composed of switches SWa and SWb composed of a pair of P-channel and N-channel transistors. Switch S
One end of Wa is the switch SW2, SW4, SW6, S
One end of the switch SWb is connected to the other end of the switch SW8, and one end of the switch SWb is connected to the other end of the switches SW1, SW3, SW5, and SW7. The other ends of these switches SWa and SWb are connected to an impedance converter 19.

On the other hand, input terminals 21 ₁ LSB of the digital signal is supplied, a second containing the inverter circuit 23 ₁
Is connected to the third switch group 18 via the logic circuit 23 of FIG. That is, the input terminals 21 _1, a gate and SWb of P-channel transistor of the switch SWa
It is connected to the gate of the N-channel transistor, through the inverter circuit 23 ₁ is connected to the gate of the P-channel transistor gates and SWb of N-channel transistors of the switch SWa.

The input terminals 21 ₂ and 21 ₃ to which signals other than the LSB of the digital signal are supplied are connected to the NAND circuit N.
1 and N4 and first and second switch groups 16, 1 through a first logic circuit 22 including inverter circuits I1 to I6.
7 are connected to switches SW1 to SW8. That is, the input terminals of the inverter circuits I5 and I6 are connected to the input terminals 21 ₂ and 21 ₃ , respectively.
One input terminal of the NAND circuit N1 is connected to the input terminal 21 _2, and the other input terminal is connected to the input terminal 21 _3. The output terminal of the NAND circuit N1 is connected to the switches SW1, SW
2 connected to the gates of the two P-channel transistors, and through the inverter circuit I1, the switches SW1,
It is connected to the gate of the N-channel transistor of SW2.

Further, one input terminal of the NAND circuit N2 is connected to the output terminal of the inverter circuit I5, the other input terminal is connected to the input terminal 21 _3. The output terminal of the NAND circuit N2 is connected to the gates of the P-channel transistors of the switches SW3 and SW4, and the inverter circuit I2
2 are connected to the gates of the N-channel transistors of SW3 and SW4.

Furthermore, one input terminal of the NAND circuit N3 is connected to the input terminal 21 _2, and the other input terminal is connected to the output terminal of the inverter circuit I6. This NAND circuit N
The output terminal of the switch 3 is connected to the gates of the P-channel transistors of the switches SW5 and SW6, and is connected to the gates of the N-channel transistors of the switches SW5 and SW6 via the inverter circuit I3.

Further, one input terminal of the NAND circuit N4 is connected to the output terminal of the inverter circuit I5, and the other input terminal is connected to the output terminal of the inverter circuit I6.
The output terminal of the NAND circuit N4 is connected to switches SW7 and SW8.
Connected to the gates of the P-channel transistors of SW7 and SW8 via the inverter circuit I4.
It is connected to the gate of the channel transistor.

The digital signal supplied to the input terminal 21 ₃ is controlled by a logic circuit (not shown). This logic circuit is controlled according to bit switching signal BCH. That is, when operating this D / A converter as a 3-bit D / A converter, this logic circuit outputs the input digital signal as it is in accordance with the bit switching signal BCH. On the other hand, when operating the D / A converter as a 2-bit D / A converter, the logic circuit in accordance with the bit switching signal BCH, by inverting the digital signal supplied to the input terminal 21 _second input terminal and supplies to 21 _3.

The operation of the above configuration will be described.
When operating this D / A converter as a 3-bit D / A converter, the bit switching signal BCH is set to "1". In this case, the switches 12b and 14b of the first and second extension circuits 12 and 14 are turned on, and the resistors RL1, RL2, RJ1, and RJ2 are connected to the resistor string circuit 15. In this state, for example, A2, A1, A0 = “0, 0,
When a digital signal of 1 "(LSB) is converted, this digital signal is directly supplied to the input terminals 21 _{3 to} 21 ₁ via a logic circuit (not shown). Then, only the output of the NAND circuit N4 is" 0 ". And the switch SW7,
SW8 is turned on. Since A0 = “1”,
The switch SWb of the third switch group 18 is turned on,
The voltage taken out by the switch SW7 is output to the output terminal 20.

On the other hand, this D / A converter is a 2-bit D / A
When operating as an A converter, the bit switching signal BC
H is set to “0”. In this case, the switches 12a and 14a of the first and second extension circuits 12 and 14 are turned on, and the resistances RL1, RL2, RJ1, and RJ2 are output from the resistance string circuit 15.
Is disconnected. In this state, for example, A1, A0
= "0, 1" (LSB), the digital signal is converted into a digital signal A2, A1, A0 = "1, 0, 1" (LSB) through a logic circuit (not shown). It is converted and supplied to the input terminals 21 _{3 to} 21 ₁ . Then, only the output of the NAND circuit N2 becomes "0", and the switches SW3 and SW4 are turned on.
Since A0 = “1”, the third switch group 18
Is turned on, and the voltage taken out by the switch SW3 is output to the output terminal 20.

According to the above embodiment, the first logic circuit 22
The response to a signal other than the LSB of the digital signal is 1, and controls the second switch group 16 and 17, the resistor string circuit 15 or expansion resistance RL2 ⁰ ~ RL2 ^L , RJ2 ⁰ ~ RJ2
^J , The second logic circuit 23 controls the third switch group 18 according to the LSB of the digital signal, and selects the first and second switch groups 16 and 17. Therefore, when the number of bits of the digital signal is the same, the number of logic circuits can be reduced as compared with the conventional case, and the chip occupation area can be reduced when integrated. FIG. 3 shows the relationship between the number of bits and the number of elements in the circuit configuration of the present invention and the conventional circuit configuration.

As can be seen from the figure, in the case of the present invention, even if the number of bits increases, the number of elements can be reduced to half or less as compared with the conventional case. Therefore, the area occupied by the chip is reduced, which is extremely advantageous for miniaturization and cost reduction.

Further, according to the above embodiment, expansion resistance across the resistor string circuit 15 RL2 ⁰ ~ RL2 ^L , RJ2 ⁰
~ RJ2 ^J Are provided, and the connection and disconnection of the extension resistor to and from the resistor string circuit 15 are controlled by the third logic circuit 25 in accordance with the bit switching signal BCH. Therefore, one D
A plurality of digital signals can be converted by the / A converter.

Further, in the above embodiment, a plurality of digital signals having different numbers of bits can be converted into analog signals by one D / A converter. However, by using this D / A converter, one digital It is also possible to divide a signal into a plurality of bits and convert it into an analog signal. That is, for example, an adding means is provided at the output terminal 20,
First, D / A conversion is performed on nk bits out of n bits, then D / A conversion is performed on the remaining bits, and the result of adding the previous conversion output and the subsequent conversion output by adding means is obtained. Thus, an n-bit D / A conversion output can be obtained. In this way, in the case of the D / A converter shown in FIG. 2, a digital signal of 3 bits + 2 bits = 5 bits can be D / A converted. Therefore, according to this D / A converter, a D / A converter with more bits can be configured without increasing the number of resistors and switches.

In the above embodiment, the first and second switch groups 16 and 17 are controlled by the LSB of the input digital signal, and the third switch group 18 is controlled by other than the LSB of the input digital signal. It is also possible to control the third switch group 18 by the MSB of the digital signal and to control the first and second switch groups 16 and 17 by means other than the MSB. Of course, various modifications can be made without departing from the spirit of the present invention.

[0036]

As described in detail above, according to the present invention, it is possible to convert a multi-bit digital signal by suppressing an increase in the resistance and the logic circuit, and to suppress an increase in the area occupied by the chip to realize an integrated circuit. A suitable D / A converter can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram specifically showing FIG. 1;

FIG. 3 is a diagram showing a comparison between the number of elements of the present invention and a conventional element.

FIG. 4 is a configuration diagram showing a conventional D / A converter.

[Explanation of symbols]

11, 13 terminal, 12, 14 first and second extension circuit, 15 resistor string circuit, 16 first switch group, 17 second switch group, 18 third switch group, 20 ... output terminal, 21 ... input terminal, 22, 23, 2
5 ... first to third logic circuit, RL2 ⁰ ~ RL2 ^L , RJ2 ⁰
~ RJ2 ^J ... Expansion resistors.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-58-71722 (JP, A) JP-A-1-147912 (JP, A) JP-A-62-181529 (JP, U) (58) Survey Field (Int.Cl. ⁷ , DB name) H03M 1/76 H03M 1/68

Claims (2)

(57) [Claims] 1. A resistor string circuit disposed between a first and a second reference power supply and having a plurality of resistors connected in series, and an extension resistor means having a plurality of resistors connected in series; and a bit of a digital signal. Control means for controlling connection / disconnection of the extension resistor means to the resistor string circuit in accordance with the number; and a plurality of switches for taking out a divided voltage from each odd-numbered connection point of the resistor string circuit and the extension resistor means. First switch means, a plurality of switches for taking out a divided voltage from each even-numbered connection point of the resistor string circuit and the extended resistor means, and the digital signal A first switch for selecting a switch constituting the first and second switch means in accordance with a signal other than the least significant bit or the most significant bit of A logic circuit, third switch means connected to the first and second switch means, and controlling the third switch means according to a signal of the least significant bit or the most significant bit of the digital signal; First,
A second logic circuit for selecting one of the second switch means. A D / A converter comprising: 2. A digital-to-analog converter according to claim 1, wherein said third switch means is provided with an adder for adding a voltage output from said third switch means.
converter.