KR100514320B1 - Digital-to-analog converter - Google Patents

Abstract

A resistor string type D / A converter capable of multi-bit converting data without increasing the number of resistors is provided. The upper four bits of the converted data are applied to the decoder 1, and the lower four bits are applied to the decoder 3 through the inversion circuit 2. The decoder 1 decodes the upper four bits and turns on any one of the FETs F0 to F15 depending on the decoding result. As a result, one of the voltages at the connection points of the resistors r0 to r15 connected in series is selected and applied to the operational amplifier 6. Similarly, a voltage corresponding to the lower 4 bits of the converted data is applied to the operational amplifier 7. The output of the operational amplifier 7 becomes 1/16 by the resistors ra and rb, and this voltage is added to the voltage applied to the operational amplifier 6 to obtain an analog voltage corresponding to the converted data. .

Description

Digital / Analog Converter {DIGITAL-TO-ANALOG CONVERTER}

The present invention relates to a resistor string type digital to analog converter (hereinafter referred to as D / A).

A resistor string type D / A converter connects resistors of the same resistance value in series and outputs the voltage at each connection point as an analog voltage corresponding to the converted data. Increases. For this reason, especially when a semiconductor integrated circuit produces a resistance string type D / A converter in a narrow chip, the area occupied by the resistance becomes large, which is extremely undesirable, and the number of bits makes it impossible.

SUMMARY OF THE INVENTION The present invention has been made to solve such problems of the prior art, and an object thereof is to provide a D / A converter capable of multi-bitting the converted data without using a large number of resistors.

1 is a block diagram showing the configuration of a digital-to-analog converter according to a first embodiment of the present invention;

2 is a characteristic diagram showing conversion characteristics of the embodiment;

3 is a block diagram showing the structure of a digital-to-analog converter according to a second embodiment of the present invention;

4 is a block diagram showing the structure of a digital-to-analog converter according to a third embodiment of the present invention;

5 is a timing diagram for explaining the operation of the above embodiment.

In order to achieve the above object, the invention described in claim 5 includes: a plurality of resistors having the same resistance value connected in series; A first decoder which decodes the upper n bits of 2n bits of the transformed data; A first switch device for selecting and outputting voltages of the connection points of the plurality of resistors based on the outputs of the first decoder; An inversion device for inverting each bit of the lower n bits of the converted data; A second decoder that decodes the output of the inverting device; A second switch device for selecting and outputting voltages of the respective connection points of the plurality of resistors based on an output of the second decoder; A buffer amplifier to which an output of the second switch device is applied; And an operational amplifier subtracting a voltage multiplied by a second integer from an output of the buffer amplifier by a voltage multiplied by a first integer by an output of the first switch device, wherein the output terminal of the operational amplifier and the buffer amplifier A first resistor and a second resistor are connected in series between the output terminal, a terminal other than a terminal to which an output voltage of the first switch device is input, among the input terminals of the operational amplifier, the first resistor and the first resistor. Provides a digital-to-analog converter with connection points of two resistors.

Moreover, invention of Claim 6 is plural resistor of the same resistance value connected in series; a first decoder for decoding the most significant n bits of m × n bits of the transformed data, wherein m is 3 or more; A first switch device for selecting and outputting voltages of the connection points of the plurality of resistors based on the outputs of the first decoder; First to second m-2 inverting devices for inverting each bit of the median (m-2) × n bit of the converted data; A second to m-1 decoder for decoding the output of the first to m-2 inverting devices; A second to m-th switch device for selecting and outputting voltages of respective connection points of the plurality of resistors based on the outputs of the second to m-th decoders; A first through m-2 buffer amplifier to which an output of the second through m-1 switch device is applied; An (m-1) inverting device for inverting each bit of the least significant n bits of the converted data; An mth decoder for decoding the output of the (m-1) inverting device; An mth switch device for selecting and outputting voltages of the connection points of the plurality of resistors based on the outputs of the mth decoder; An (m-1) th buffer amplifier to which the output of the mth switch device is applied; And a voltage obtained by multiplying the outputs of the first through the (m-2) buffer amplifiers by the second through the m-1 constants, respectively, from a voltage multiplied by a first integer with an output of the first switch device, and An operational amplifier subtracting a voltage multiplied by an mth integer from an output of the (m-1) th buffer amplifier, the output terminal of the operational amplifier and an output terminal of the first to the first (m-1) th buffer amplifiers; The first resistor and each of the second to mth resistors are connected in series between each other, and terminals other than the terminal to which the output voltage of the first switch device is input among the input terminals of the operational amplifier, Provided is a digital-to-analog converter, to which a connection of each of the first resistor and the second to mth resistors is connected.

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EMBODIMENT OF THE INVENTION Hereinafter, the digital-to-analog converter which concerns on embodiment of this invention with reference to drawings is demonstrated. 1 is a block diagram showing the configuration of a digital-analog converter according to a first embodiment of the present invention. The D / A converter can convert 8-bit converted data into an analog signal. In this figure, the code DI is an input terminal to which the converted data is applied, the upper four bits of the converted data applied to the input terminal DI are applied to the decoder 1, and the lower four bits are the inverting circuit ( 2) is applied. The inversion circuit 2 inverts each of the input lower four bits and outputs the inverted signal to the decoder 3.

Reference numerals r0 to r15 denote resistances of the same resistance values connected in series. One end of the resistor r15 is connected to the high voltage VH, and one end of the resistor r0 is connected to the low voltage VL. Codes F0 to F15 are FETs controlled on / off by the output of the decoder 1, and each source of these FETs F0 to F15 is connected to a connection point of the resistors r0 to r15, and each drain is connected in common. It is connected to the non-inverting input terminal of the operational amplifier 6.

Further, symbols F0a to F15a are FETs controlled on / off by the output of the decoder 3, and each source of these FETs F0a to F15a is connected to a connection point of the resistors r0 to r15, and each drain is common. It is connected to the non-inverting input terminal of the operational amplifier (7). The operational amplifier 7 has an output terminal connected to an inverting input terminal and operates as a non-inverting amplifier of amplification degree 1, and its output is applied to the inverting input terminal of the operational amplifier 6 through a resistor rb (resistance value 15R). do. In the operational amplifier 6, a resistor ra (resistance value R) is inserted between the output terminal and the inverting input terminal, and the output terminal is connected to the output terminal DO. This operational amplifier 6,

Vo = (16/15) Va-(1/15) Vb ... (1)

However, Vo: output voltage of the operational amplifier (6)

    Va: voltage of the non-inverting input terminal of the operational amplifier 6

    Vb: output voltage of the operational amplifier 7

Is performed, and the result of the calculation is output to the output terminal DO as an analog voltage corresponding to the converted data.

In such a configuration, the decoder 1 which decodes the upper four bits when the converted data is " 00000000 " turns on the FET F0, whereby the voltage VL is non-inverted by the operational amplifier 6. It is supplied to the input stage. On the other hand, at this time, " 1111 " is output from the inversion circuit 2, and as a result, the decoder 3 turns on the FET 15a. As a result, the voltage VL + 15v (v: respective voltage drops of the resistors r0 to r15) at the connection point between the resistor r14 and the resistor r15 is supplied to the non-inverting input terminal of the operational amplifier 7. That is, in this case, the voltages Va and Vb are

Va = VL

Vb = VL + 15v

If you substitute this value in the above formula (1),

Vo = (16/15) VL-(1/15) (VL + 15v) = VL-v

As a result, the output analog voltage Vo is obtained.

Similarly, the output analog voltage with respect to the data to be converted can be obtained as follows.

Converted Data Va Vb Vo

00000001 VL VL + 14v VL- (14/15) v

00000010 VL VL + 13v VL- (13/15) v

00010000 VL + v VL + 15v VL + (1/15) v

00010001 VL + v VL + 14v VL + (2/15) v

00100000 VL + 2v VL + 15v VL + (17/15) v

2 is a characteristic diagram showing a relationship between the above-described converted data and an analog output voltage.

In this manner, according to the above embodiment, it is possible to convert 8-bit converted data into analog voltage by 16 resistors required for converting conventional 4-bit digital data into analog voltage. In general, 2 n bits of data can be converted using a resistor required to convert conventional n bits of data into an analog voltage. In this case, the series connection resistance, the upper n-bit FET, and the lower n-bit FET are respectively At the same time, the value of the resistance (rb) Shall be.

By the way, in the above embodiment, the converted data is divided into two and the circuits corresponding to the decoders and the FETs are provided, respectively. You can also arrange. For example, FIG. 3 shows a second embodiment of the present invention, wherein the decoder 11 corresponding to the upper n bits is divided by dividing 3n-bit transformed data every n bits. Four FETs 12, 12, ..., the inverting circuit 14 corresponding to the middle n bits, the decoder 15, and the FETs 16, 16, ... Corresponding inverting circuits 18, decoders 19, and FETs 20, 20 are provided. In addition, the symbols r0 to r ( -1) is the resistance of the same resistance value connected in series.

The voltage at the common connection point of the FETs 12, 12, ... is input to the operational amplifier 22, and the voltage at the common connection point of the FETs 16, 16, ... is gain 1 of the operational amplifier 23. ), And the voltage at the common connection point of the FETs 20, 20, ... is input to the operational amplifier 24 of gain 1. In addition, a resistor 27 (resistance value: between the output terminal of the operational amplifier 23 and the inverting input terminal of the operational amplifier 22). R) is inserted, and the resistor 28 (resistance value: between the output terminal of the operational amplifier 24 and the inverting input terminal of the operational amplifier 22 is -1) R) is inserted, and a resistor 26 (resistance value R) is inserted between the output terminal of the operational amplifier 22 and the inverting input terminal.

By such a configuration, the voltage at the common connection point of the FETs 16, 16, ... And the voltage at the common connection point of the FETs 20, 20, ... This is added to the voltage at the common connection point of the FETs 12, 12, ..., and this addition result is output from the operational amplifier 22 through the output terminal DO as an analog voltage corresponding to the converted data.

Next, a third embodiment of the present invention will be described. 4 is a block diagram showing the configuration of the above embodiment, and FIG. 5 is a timing diagram for explaining the operation of the above embodiment. The D / A converter shown in these figures is a circuit for converting 2n-bit converted data into an analog signal, and is characterized in that one series connection resistor is used twice by time division.

In Fig. 4, the sign DI is an input terminal, and 2n bits of transformed data are applied in time division by n bits (see Fig. 5 (a)). Reference numeral 30 is an n-bit decoder, and 31, 31, ... are resistors of the same resistance value connected in series. Reference numerals 32, 32, ... denote FETs controlled on / off by the output of the decoder 30, each source is connected to a connection point of the resistors 31, 31, ..., and each drain is a common connection point ( 34) is connected in common.

Reference numeral 35 is a sample hold circuit, and is composed of an FET 36, a holding capacitor 37, and an operational amplifier 38 operating as an amplifier having a gain of one. When the signal S1 (see FIG. 5B) supplied to the gate of the FET 36 is a logic "1" signal, the FET 36 is turned on, and the voltage at the common connection point 34 becomes the capacitor 37. ), While the signal S1 becomes a logic " 0 ", the FET 36 is turned off and the voltage charged in the capacitor 37 is maintained as it is. This held voltage is amplified by gain 1 by the operational amplifier 38 and output at the output stage.

Reference numeral 40 is an operational amplifier, a voltage of the common connection point 34 is applied to the non-inverting input terminal, and a resistor 41 (resistance value ( The output of the sample hold circuit 35 is applied through -1) R). In addition, a resistor 42 (resistance value R) is inserted between the output terminal of the operational amplifier 40 and the inverting input terminal. As a result, the voltage at the common connection point 34 and the output voltage of the sample and hold circuit 35 are reduced. The voltage obtained by adding the above voltage is output from the operational amplifier 40.

Reference numeral 45 is a separate sample and hold circuit, and is composed of a FET 46, a holding capacitor 47, and an operational amplifier 48 operating as an amplifier having a gain of 1, and a signal applied to a gate of the FET 46 ( When S2) (see Fig. 5C) is logic "1", the input voltage is sampled, and when logic "0", the input voltage is held. The output of the sample hold circuit 45 is output to the output terminal DO (see Fig. 5 (d)).

In this arrangement, first, data inverting each bit of the lower n bits of the converted data is supplied to the input terminal DI, and the signal S1 rises to the " 1 " signal (time t1 in Fig. 5). ). When the data is supplied to the input terminal DI, the decoder 30 decodes the data and turns on the FET 32 corresponding to the decoding result. As a result, the voltage corresponding to the lower n bits of the converted data is charged to the capacitor 37 via the common connection point 34 and the FET 36.

Next, the upper n bits of the to-be-converted data are applied to the input terminal DI, while the signal S1 is logic "0" and the signal S2 is logic "1" (time t2). When the upper n bits of the converted data are applied to the input terminal DI, the FET 32 corresponding to the data decoded by the decoder 30 is turned on, so that the voltage corresponding to the upper n bits of the converted data is turned on. The common connection point 34 is applied to the non-inverting input terminal of the operational amplifier 40. In addition, when the signal S1 becomes the "0" signal, the FET 36 is turned off, and then the charging voltage of the capacitor 37, that is, the voltage corresponding to the lower n bits of the to-be-converted data is changed to the sample hold circuit ( 35). This voltage is obtained by converting the lower n bits Twice the voltage. The output voltage of the sample hold circuit 35 is caused by the resistors 41 and 42. Then, by adding the voltage at the common connection point 34 and the operational amplifier 40, the analog voltage corresponding to the 2n-bit converted data from the operational amplifier 40 is output and supplied to the sample hold circuit 45.

At this time, since the signal S2 is a logic " 1 " signal, the above-described analog voltage is charged in the capacitor 47 and output from the output terminal DO through the operational amplifier 48.

Next, at time t3, data obtained by inverting the lower n bits of the data to be converted next is supplied through the input terminal DI, and at the same time, the signal S1 is "1" and the signal S2 is "0". Becomes Thereafter, conversion of the next to-be-converted data into an analog signal is performed in exactly the same manner as above.

According to the present invention, since each of the first to m-th data obtained by dividing the transformed data by every n consecutive bits is converted to an analog signal by a set of series-connected resistors, the number of resistors is increased. The effect of multiplying the converted data without any gain is obtained. Further, according to the inventions of Claims 3 and 4, since the selection means is used in time division, the effect of reducing the number of the selection means is obtained.

Claims (6)

delete delete delete delete A plurality of resistors of the same resistance value connected in series; A first decoder which decodes the upper n bits of 2n bits of the transformed data; A first switch device for selecting and outputting voltages of the connection points of the plurality of resistors based on the outputs of the first decoder; An inversion device for inverting each bit of the lower n bits of the converted data; A second decoder that decodes the output of the inverting device; A second switch device for selecting and outputting voltages of the respective connection points of the plurality of resistors based on an output of the second decoder; A buffer amplifier to which an output of the second switch device is applied; And An operational amplifier subtracting a voltage obtained by multiplying an output of the first switch device by a first integer and multiplying the output of the buffer amplifier by a second integer; A first resistor and a second resistor are connected in series between an output terminal of the operational amplifier and an output terminal of the buffer amplifier, and a terminal into which an output voltage of the first switch device is input among input terminals of the operational amplifier. A digital / analog converter, to which other terminals and a connection point of the first resistor and the second resistor are connected. A plurality of resistors of the same resistance value connected in series; a first decoder for decoding the most significant n bits of m × n bits of the transformed data, wherein m is 3 or more; A first switch device for selecting and outputting voltages of the connection points of the plurality of resistors based on the outputs of the first decoder; First to second m-2 inverting devices for inverting each bit of the median (m-2) × n bit of the converted data; A second to m-1 decoder for decoding the output of the first to m-2 inverting devices; A second to m-th switch device for selecting and outputting voltages of respective connection points of the plurality of resistors based on the outputs of the second to m-th decoders; A first through m-2 buffer amplifier to which an output of the second through m-1 switch device is applied; An (m-1) inverting device for inverting each bit of the least significant n bits of the converted data; An mth decoder for decoding the output of the (m-1) inverting device; An mth switch device for selecting and outputting voltages of the connection points of the plurality of resistors based on the outputs of the mth decoder; An (m-1) th buffer amplifier to which the output of the mth switch device is applied; And The voltage obtained by multiplying the outputs of the first through the (m-2) buffer amplifiers by the second through the m-1 constants, respectively, from the voltage multiplied by the first integer with the output of the first switch device and the first (m-1) an operational amplifier subtracting the voltage of the output of the buffer amplifier multiplied by the mth constant, Between the output terminal of the operational amplifier and the output terminal of the first through m-th buffer amplifier, each of the first resistor and the second through m-th resistor is connected in series, and the The digital-to-analog converter connected between terminals other than the terminal into which the output voltage of the said 1st switch apparatus is input, and each connection point of the said 1st resistor and said 2nd-mth resistor among the input terminals.