JPS59159035U

JPS59159035U - D/A converter

Info

Publication number: JPS59159035U
Application number: JP5446583U
Authority: JP
Inventors: 山田　恒雄
Original assignee: 株式会社ケンウッド
Priority date: 1983-04-12
Filing date: 1983-04-12
Publication date: 1984-10-25

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示す回路図、−第２図はそ
の動作例を示す波形図である。１・・・・・・レジスタ、２・・・・・・データセレク
タ、３・・・・・・Ｄ／Ａコンバータ、５，６・・量基
準電圧発生回路、７・・・・・・ホールド回路、８・・
・・・・加算器、Ｓ□・・間第１のスイッチ回路、Ｓ２
・・間第２のスイッチ回路。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram showing an example of its operation. 1... Register, 2... Data selector, 3... D/A converter, 5, 6... Quantity reference voltage generation circuit, 7... Hold Circuit, 8...
...adder, S□... first switch circuit, S2
...Second switch circuit.

Claims

[Scope of utility model registration request]

A register having two or more bits, a data selector that divides the register into N (N≧2) groups of one or more bits and selects and outputs each group, and a data selector that selects and outputs each group, and the data of each selected group. D to convert to analog signal
/A converter and N that generates reference voltages of different values ~ ' corresponding to the weights of the bits constituting each group.
D/A conversion is performed by selecting a circuit corresponding to the group selected by the data selector from among the N reference voltage generation circuits and inputting the reference voltage to the D/A converter. (N-1) hold circuits that hold analog signals of groups other than the final group among the analog signals converted by the D/A converter; a second switch circuit that is provided between the hold circuit and causes the corresponding hold circuit to hold analog signals other than the final group in conjunction with the data selector and the first switch circuit; and an analog signal of the final group. A D/A converter comprising: an addition circuit that adds the signal and the analog signal held in the hold circuit when the signal is obtained.