JPS60145367U - Averaging signal display circuit - Google Patents
Averaging signal display circuitInfo
- Publication number
- JPS60145367U JPS60145367U JP3305284U JP3305284U JPS60145367U JP S60145367 U JPS60145367 U JP S60145367U JP 3305284 U JP3305284 U JP 3305284U JP 3305284 U JP3305284 U JP 3305284U JP S60145367 U JPS60145367 U JP S60145367U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- ray tube
- cathode ray
- display
- display circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Closed-Circuit Television Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
一図は本考案の実施例を示すブロック図で、2:トリガ
発生回路、3:サンプリング・クロック、4:AD変換
器、5:メモリ、7:カウンタ、11:加算器、13:
メモリ、17:カウンタ、19:シフト回路、23’:
m示メモリ、24:ブラウン管、制御回路、28:ブラ
ウン管。One figure is a block diagram showing an embodiment of the present invention, 2: trigger generation circuit, 3: sampling clock, 4: AD converter, 5: memory, 7: counter, 11: adder, 13:
Memory, 17: Counter, 19: Shift circuit, 23':
m display memory, 24: cathode ray tube, control circuit, 28: cathode ray tube.
Claims (1)
と加算回路とシフト回路と表示用メモリとブラウン管と
ブラウン管の表示を制御する制御回路とにより構成され
、入力信号をサンプリング・クロツモに同期して、前も
って指定された回数(2のべき乗)だけAD変換し、そ
の結果を前記加算器により加算を行ない、前記シフト回
路でシフトする事により指定回数による除算を行なって
平均値を求め、これをブラウン管の制御回路に従ってプ
ランキング中に前記表示用メモリへ書込み、ブラウン管
に表示する平均化信号表示回路。It is composed of a digital converter, a sampling clock, a counter, a memory, an adder circuit, a shift circuit, a display memory, a cathode ray tube, and a control circuit that controls the display of the cathode ray tube, and synchronizes the input signal with the sampling clock. A/D conversion is performed a predetermined number of times (a power of 2), the results are added by the adder, shifted by the shift circuit, and divided by the designated number of times to obtain an average value. An averaged signal display circuit writes data into the display memory during planking according to a control circuit and displays the signal on a cathode ray tube.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3305284U JPS60145367U (en) | 1984-03-09 | 1984-03-09 | Averaging signal display circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3305284U JPS60145367U (en) | 1984-03-09 | 1984-03-09 | Averaging signal display circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60145367U true JPS60145367U (en) | 1985-09-26 |
Family
ID=30535136
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3305284U Pending JPS60145367U (en) | 1984-03-09 | 1984-03-09 | Averaging signal display circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60145367U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012230007A (en) * | 2011-04-26 | 2012-11-22 | Jvc Kenwood Corp | Frequency analyzer, frequency analysis method and program |
JP2013003054A (en) * | 2011-06-20 | 2013-01-07 | Yokogawa Electric Corp | Waveform measurement device |
-
1984
- 1984-03-09 JP JP3305284U patent/JPS60145367U/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012230007A (en) * | 2011-04-26 | 2012-11-22 | Jvc Kenwood Corp | Frequency analyzer, frequency analysis method and program |
JP2013003054A (en) * | 2011-06-20 | 2013-01-07 | Yokogawa Electric Corp | Waveform measurement device |
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