JPS59152654U - Scanning signal control circuit - Google Patents
Scanning signal control circuitInfo
- Publication number
- JPS59152654U JPS59152654U JP4796483U JP4796483U JPS59152654U JP S59152654 U JPS59152654 U JP S59152654U JP 4796483 U JP4796483 U JP 4796483U JP 4796483 U JP4796483 U JP 4796483U JP S59152654 U JPS59152654 U JP S59152654U
- Authority
- JP
- Japan
- Prior art keywords
- counter
- output
- scanning signal
- control circuit
- signal control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electron Beam Exposure (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は電子ビーム装置の軸合わせに使用した従来の走
査信号制御回路、第２図は本考案を電子ビーム装置の軸
合わせに使用した例を示した走査信号制御回路の概略図
、第３図及び第４図は該回路の動作の説明を補正する為
のものである。
１：発振器、２ｘ：ｘ方向軸合わせ用コイル、６：乗算
型ＤＡコンバータ、７：カウンタ、８：クロックパルス
発生器、９：データ変換用メモリ、１０：比較器、１１
：第１ゲート回路、１２：第２ゲート回路、１３：ゲー
ト回路。Fig. 1 is a conventional scanning signal control circuit used for axis alignment of an electron beam device, Fig. 2 is a schematic diagram of a scanning signal control circuit showing an example of using the present invention for axis alignment of an electron beam device, and Fig. 3 The figures and FIG. 4 are for correcting the explanation of the operation of the circuit. 1: Oscillator, 2x: Coil for x-direction axis alignment, 6: Multiplying DA converter, 7: Counter, 8: Clock pulse generator, 9: Memory for data conversion, 10: Comparator, 11
: first gate circuit, 12: second gate circuit, 13: gate circuit.
Claims (1)
パルス発生器からのパルスをカウントするカウンタの出
力の積をアナログ信号の形で出力する乗算型ｂＡコンバ
ータ、前記カウンタの出力を設定値と比較し、カウンタ
の出力が大きい場合、前記カウンタをダウンモードにし
、小さい場合、アップモードにし、等しい場合、前記ク
ロックパルス発生器からパルスがカウントされない様に
する制御系から成る走査信号制御回路。A multiplier bA converter that outputs the product of the output of an oscillator that generates an analog scanning signal and the output of a counter that counts pulses from a clock pulse generator in the form of an analog signal, and compares the output of the counter with a set value; A scanning signal control circuit comprising a control system that puts the counter in a down mode when the output of the counter is large, puts the counter in an up mode when it is small, and prevents pulses from being counted from the clock pulse generator when the output is equal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4796483U JPS59152654U (en) | 1983-03-31 | 1983-03-31 | Scanning signal control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4796483U JPS59152654U (en) | 1983-03-31 | 1983-03-31 | Scanning signal control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59152654U true JPS59152654U (en) | 1984-10-13 |
| JPS6342457Y2 JPS6342457Y2 (en) | 1988-11-07 |
Family
ID=30178504
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4796483U Granted JPS59152654U (en) | 1983-03-31 | 1983-03-31 | Scanning signal control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59152654U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6364254A (en) * | 1986-09-05 | 1988-03-22 | Hitachi Ltd | Charged particle optical system |
-
1983
- 1983-03-31 JP JP4796483U patent/JPS59152654U/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6364254A (en) * | 1986-09-05 | 1988-03-22 | Hitachi Ltd | Charged particle optical system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6342457Y2 (en) | 1988-11-07 |
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