JP2012230007A - Frequency analyzer, frequency analysis method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a frequency analysis device with small throughput and high accuracy.SOLUTION: An input buffer 31 stores input signals successively input from an input terminal In in a time T that is one period of a frequency of an extraction object. An operation part 32 cumulatively adds signal values at the same time during the time T of the input signal which the input buffer 31 stores whenever the time T passes. When the accumulation addition is performed a predetermined number of times, the operation part 32 divides an accumulation addition result by the number of times of the accumulation addition. In this way, a waveform in which a frequency except the extraction object in the input signal is removed and a level of a frequency component of the extraction object are obtained.

Description

  The present invention relates to a frequency analysis device, a frequency analysis method, and a program.

  Some audio reproducing apparatuses have a frequency analysis (spectrum analyzer) function for determining what frequency component the input sound contains and analyzing the level (energy) for each frequency band.

  As a method of analyzing the frequency, there are methods using FFT (Fast Fourier Transform) and DFT (Discrete Fourier Transform).

  As another method, there is a method in which a component of a desired frequency is extracted from input sound by a band pass filter and the level is detected (for example, see Patent Document 1).

JP 08-328593 A

  In the frequency analysis method using FFT or DFT, it is necessary to process an input signal with a window function and to perform FFT calculation or DFT calculation, and the processing amount (calculation amount) is large. For this reason, it can be realized with a DSP (Digital Signal Processor) with a large processing capability, but it is difficult to execute with a DSP with a small processing capability.

  Further, in the frequency analysis method using a bandpass filter, even if the pass band of the filter is steep, even an extra frequency is acquired, so the analysis accuracy is low. In addition, high calculation accuracy and a large calculation amount are required for level calculation and filter calculation. For this reason, it can be realized with a DSP (Digital Signal Processor) with a large processing capability, but it is difficult to execute with a DSP with a small processing capability.

  The present invention has been made in view of the current situation as described above, and an object thereof is to provide a frequency analysis technique with high accuracy and a small processing amount.

In order to achieve the above object, a frequency analysis device according to the first aspect of the present invention provides:
An input buffer for storing, as a signal segment, an input signal input at the predetermined time every predetermined time corresponding to one period of the extraction target frequency;
A register for holding a cumulative addition result obtained by cumulatively adding the signal values of the signal segments supplied from the input buffer at the predetermined time at the respective time points within the predetermined time; Each time, the cumulative addition result held in the register and the signal segment newly supplied from the input buffer are added together at the same time point within the predetermined time, and a new value is added. An operation unit for obtaining a cumulative addition result and holding the new cumulative addition result in the register;
It is characterized by providing.

  For example, the arithmetic unit divides the cumulative addition result by the cumulative addition number.

  In addition, for example, a plurality of the input buffers and the arithmetic units are installed corresponding to a plurality of extraction target frequencies.

In order to achieve the above object, a frequency analysis method according to a second aspect of the present invention includes:
An input process for holding an input signal input at the predetermined time as a signal segment for each predetermined time corresponding to one period of the extraction target frequency;
The signal unit held at every predetermined time is held in a cumulative addition result obtained by cumulatively adding the signal values at each time point within the predetermined time, and the held time is held each time the predetermined time elapses. A signal value at the same time point within the predetermined time is added to each of the cumulative addition result and the newly input signal fragment to obtain a new cumulative addition result, and the new cumulative addition result is retained. An arithmetic processing to be held instead of the cumulative addition result,
It is characterized by performing.

In order to achieve the above object, a computer program according to the third aspect of the present invention provides a computer,
An input procedure for holding, as a signal segment, an input signal input at the predetermined time every predetermined time corresponding to one period of the extraction target frequency;
The signal unit held at every predetermined time is held in a cumulative addition result obtained by cumulatively adding the signal values at each time point within the predetermined time, and the held time is held each time the predetermined time elapses. A signal value at the same time point within the predetermined time is added to each of the cumulative addition result and the newly input signal fragment to obtain a new cumulative addition result, and the new cumulative addition result is retained. Calculation procedure to be held instead of the cumulative addition result,
Is executed.

  According to the present invention, it is possible to provide a frequency analysis technique with high accuracy and a small processing amount.

1 is a configuration diagram of a frequency analysis device according to a first embodiment of the present invention. It is a flowchart for demonstrating the process of the frequency analyzer shown in FIG. It is a figure which shows the example of an input signal. It is a figure which shows the data sequence of an input signal. It is a figure which shows the data sequence of an input signal. It is a figure explaining the result of averaging. It is a figure which shows the waveform after averaging. It is a block diagram of the frequency analyzer which concerns on the 2nd Embodiment of this invention. It is a block diagram of the frequency analyzer which concerns on the 3rd Embodiment of this invention. It is a block diagram of the frequency analyzer which concerns on the 4th Embodiment of this invention.

Hereinafter, a frequency analysis method and a frequency analysis device according to embodiments of the present invention will be described.
The frequency analysis method of the present embodiment divides the input signal into one period of the target frequency and averages the signal strength (instantaneous value) at the same time in the divided signal. The frequency signal component is extracted. Since the extracted signal component is a waveform, the level can be obtained therefrom.

  More specifically, a natural sound such as music generally does not disappear in one cycle after the sound is produced, and the same waveform is repeated to some extent. The frequency analysis method according to the present embodiment is a method for extracting a desired sine wave using a feature in which this waveform is repeated.

For example, when it is desired to extract a waveform of 1 kHz from a plurality of sine waves constituting the input signal, the input signal is divided every wavelength of 1 msec.
The first waveform divided every 1 msec is called Frame1, the second waveform is called Frame2, and then Frame3, Frame4, and so on.

  When divided every 1 msec, the signal component having a wavelength of 1 msec has the same waveform in each frame. On the other hand, when the wavelength is other than 1 msec, the wavelength does not match in the time of 1 msec, so the waveform is shifted when comparing Frame 1 and Frame 2.

A sine wave with a wavelength of 1 msec has the same waveform in each frame of Frame 1, Frame 2, Frame 3,..., And averages multiple frames (averages signal components at relatively the same time in the frame) The waveform does not change.
On the other hand, for a sine wave having a wavelength other than 1 msec, the sine wave has periodicity and the average of one wavelength is 0, and when averaged, it becomes a value close to 0.
Thereby, a desired frequency component can be extracted from the audio signal by a simple process of addition and division.

ここで、ｆ₁は、目的（抽出対象）信号成分の周波数を示している。
ｆ₂は、入力信号に含まれている他の周波数信号成分の周波数を示している。
ｔは、各Ｆｒａｍｅにおける時刻を表し、ｔの添え字ｆ_ｓ／ｆ₁は、サンプリングされる間隔を表している。
ｎは、８Ｆｒａｍｅ中の何番目のＦｒａｍｅであるかを示している。 This principle will be described using mathematical formulas.
Frequency digitized by sampling a sine wave and the sine wave synthesis wave of frequency f ₂ of _{f 1} at the sampling frequency _{f s,} is divided into Frame length _f 1 / _{f s,} the relative positions of the eight Frame When the same data is averaged, the value is as follows.

Here, f ₁ indicates the frequency of the target (extraction target) signal component.
f ₂ indicates the frequency of another frequency signal component included in the input signal.
t represents the time in each frame, and the subscript f _s / f ₁ of t represents the sampling interval.
n indicates the numbered frame among the 8 frames.

If the frequency to be extracted is f _1, Frame is the length of _{f 1} / f _s. Since the next frame rotates 360 degrees between adjacent frames, the same waveform as that of the previous frame is output.

The sin part in the first half of the formula taking the addition average is as follows.

Since f ₂ having a period that does not match the length of the frame is within a range of ± 1 due to the nature of the sine wave, it becomes smaller than 1 when added and averaged.
Therefore, when the second half of the sin part is added up to ∞, the following expression is obtained.

In this way, when divided and averaged at intervals of a certain time, the waveform always appears in the same shape for the frequency at that time. Since different frequencies come out with different periods, they cancel out and approach zero by averaging.
As a result, a waveform having only a period in which the angular velocity is 2πf ₁ / f _s remains.

  Next, an embodiment of a frequency analysis apparatus that realizes the frequency analysis method will be specifically described.

[First Embodiment]
As shown in FIG. 1, the frequency analysis apparatus 100 according to the present embodiment includes an input buffer 31 connected to an input terminal In, an arithmetic unit 32 connected to the input buffer 31, and a control unit 33. This is an apparatus for extracting a waveform of a frequency component to be extracted from a waveform represented by a digital input signal input from a terminal In.

  The input buffer 31 has a capacity for storing each data (signal fragment) of the digital input signal sequentially input via the input terminal In for one period of T (= 1 / ft) of the frequency ft to be extracted. Have.

  The arithmetic unit 32 includes an addition result register 321 and an arithmetic circuit 329. The addition result register 321 has a capacity for storing data for one period T (= 1 / ft) of the frequency ft to be extracted.

  The arithmetic circuit 329 adds the data at the same time relative to each other in the input buffer 31 and the addition result register 321 and stores them in the addition result register 321. The arithmetic circuit 329 repeats the addition operation n times and then divides each data held in the addition result register 321 by n to obtain an average value.

  The control unit 33 includes a microprocessor and a memory, and controls the entire operation.

  The arithmetic unit 32 may be configured with a microprocessor and a memory, or may be configured with a DSP. Further, the entire input buffer 31 and operation unit 32 may be constituted by a microprocessor, a memory, and a DSP.

Next, the operation of the frequency analysis apparatus will be described with reference to FIGS.
FIG. 2 is a flowchart showing the operation of the control unit 33 of the frequency analysis apparatus 100.
First, the control unit 33 sets a frequency ft to be extracted (step S1).
Next, the control unit 33 sets the sampling frequency fs of the digital input signal (step S2).
The control unit 33 obtains one period T = 1 / ft of the waveform of the frequency ft (step S3).
The control unit 33 obtains the number of data m in one cycle T = T / {1 / (fs)} = fs / ft (step S4).

The control unit 33 determines the number n of additions of input data by the calculation unit 32 (step S5).
Next, the controller 33 sets the addition execution count i to an initial value 0 (step S6).
Next, the control unit 33 sets all addition data stored in the addition result register 321 to an initial value of 0 (step S7).

  On the other hand, a digital input signal is supplied to the input buffer 31 via the input terminal In. The control unit 33 supplies a transfer clock having the same frequency as the sampling frequency fs to the input buffer 31, and stores the digital input signal in the input buffer 31 while shifting (step S8).

  The control unit 33 determines whether or not one period T of the frequency ft to be extracted has elapsed, that is, whether or not m pieces of input data are stored in the input buffer 31 (step S9).

  When it is determined that the time T has not elapsed (the number of input data has not reached m) (step S9: NO), the process returns to step S8, and the input data storing operation is continued.

  On the other hand, when it is determined that T time has passed (the number of input data has reached m) (step S9: YES), the control unit 33 instructs the arithmetic circuit 329 to perform addition. In response to this instruction, the arithmetic circuit 329 acquires m pieces of input data stored in the input buffer 31 in parallel, and each of the acquired m pieces of data is stored in the addition result register 321 at that time. The corresponding addition data is added and stored again in the addition result register 321 (step S10).

  Next, the control unit 33 increments the addition execution count i by 1 (step S11).

  The control unit 33 determines whether or not the addition execution number i has reached the addition number n (step S12), and if it is determined that the addition execution number i has not reached the predetermined number n (step S12: NO) ), The process is returned to step S8, m input data are newly stored in the input buffer 31, and the process of adding the addition data stored in the addition result register 321 is repeated.

  On the other hand, when the addition execution number i reaches the addition number n (step S12: YES), the addition result register 321 divides the digital input signal by the period T, and each period T Thus, addition data obtained by adding the data at the same time relative to each other is obtained.

  The control unit 33 controls the arithmetic circuit 329 and divides each addition data stored in the addition result register 321 by the number of additions n (step S13). As a result, the average value of the data at the same point in time T of the digital input signal in the past nT period is obtained in the addition result register 321.

The computing unit 32 outputs the data stored in the addition result register 321 (step S14).
Thereafter, it is determined whether or not there is a stop instruction (step S15). If there is a stop instruction (step S15: YES), the process is terminated. On the other hand, if there is no stop instruction (step S15: NO), the addition result register 321 is reset to return all addition data to the initial value 0 (step S16), and the addition execution count i is returned to the initial value 0. (Step S17), the process returns to Step S8.

FIG. 3 is a diagram illustrating an example of an input signal.
4 and 5 are diagrams for explaining data values of the input signal shown in FIG.
The input data represents a combined signal of a sine wave with a frequency of 600 Hz, a sine wave with a frequency of 3000 Hz, and a sine wave with a frequency of 2500 Hz as shown in FIG. 3, and the amplitude of the signal component of 600 Hz as shown in FIG. Is added at a rate of 0.4 for the amplitude of the signal component of 0.25, 3000 Hz and 0.4 for the signal component of 2500 Hz.

  The sampling frequency fs is 25000 Hz. In this case, one sampling period Ts = 0.00004 sec = 0.04 msec = 40 μsec.

  If a 2500 Hz component is an extraction target, the cycle Tt is 0.0004 sec.

  In this case, the control unit 33 sets the extraction target frequency ft to 2500 Hz (step S1), sets the sampling frequency fs to 25000 Hz (step S2), and obtains one cycle T of the extraction target frequency ft as 0.0004 sec ( Step S3). Further, the number m of data input during one cycle T is specified as Tt / Ts = 10 (step S4). In addition, the number n of additions is set (step S5). Here, n = 8.

  Next, the addition execution count i is set to 0 (step S6), and all the addition data stored in the addition result register 321 is set to 0 (step S7).

Subsequently, the control unit 33 supplies a shift clock having a frequency fs to the input buffer 31 to capture an input signal.
When 10 pulses of the shift clock are supplied during the period T, 10 pieces of data shown in the period T1 in FIG. 4 are stored in the input buffer 31, and YES is determined in the step S9.
As a result, the corresponding data stored in the input buffer 31 and the data stored in the addition result register 321 are added together and stored in the addition result register 321 (step S10). Subsequently, the addition execution count i is updated to 1 (step S11), and 1 = i <n = 8 is determined in step S12 (step S12: NO).

  The control unit 33 supplies a shift clock of 10 clocks to the input buffer 31, and stores 10 data (first to 20th data) indicated by a period T2 in FIG. Corresponding data stored in the addition result register 321 are added together and stored in the addition result register 321 (step S10). Thereafter, the same operation is repeated until it is determined that i = 8 (step S12: NO).

For 4 and 5, represents the input signal stored in the input buffer 31 in the first period T1 [delta] ₁ and represents the input signal stored in the input buffer 31 in the second period T2 [delta] ₂ and, When the position (relative time point) of data in each period T is indicated by a number in [],
δ ₁ [0] = 0
δ ₁ [1] = 0.546489
δ ₁ [2] = 0.853894
δ ₁ [3] = 0.797907
・
・
・
δ ₂ [0] = 0.629929
δ ₂ [1] = 0.846078
δ ₂ [2] = 0.77058
δ ₂ [3] = 0.644442
・
・
・
It becomes.

The arithmetic unit 32 performs the addition of step S10 eight times, and then divides the addition result by a predetermined number n (= 8) in step S13. This division can also be realized by shifting each addition data stored in the addition result register 321 in the direction in which the 3-bit digit is reduced. The above addition and division are performed by adding and dividing data at the same time in the period T with respect to the data group stored in the input buffer 31, and is expressed by the following equation.
D1 = (δ ₁ [0] + δ ₂ [0] + δ ₃ [0] + δ ₄ [0] + δ ₅ [0] + δ ₆ [0] + δ ₇ [0] + δ ₈ [0]) / 8
= (0 + 0.629929 + 0.266447-0.48069-0.4426 + 0.237764 + 0.472454 + 0.008907) / 8
= 0.0865526375
D2 = (δ ₁ [1] + δ ₂ [1] + δ ₃ [1] + δ ₄ [1] + δ ₅ [1] + δ ₆ [1] + δ ₇ [1] + δ ₈ [1]) / 8
= (0.546489 + 0.846078 + 0.178698-0.40762 + 0.0173322 + 0.7555604 + 0.653113-0.05465) / 8)
= 0.316887925
・
・
・

  The average D1, D2, D3... Values are as shown in FIG. 6 and as waveforms, as shown in FIG. 7, and a sine wave waveform of a 2500 Hz component to be extracted can be extracted. The amplitude of the 2500 Hz component to be extracted can also be reproduced as 0.4.

  As described above, according to the present embodiment, the signal component of the target frequency ft can be extracted from the input signal with a simple configuration and control.

In the above embodiment, the example of extracting the frequency component of 2500 Hz has been shown, but the frequency to be extracted is arbitrary.
However, it is desirable that the frequency ft to be extracted, the sampling frequency fs, and the number of data m satisfy 1 = m · ft / fs, and m is a natural number of 2 or more.

The frequency analysis apparatus 100 of this embodiment has the following advantages.
(1) Since it can be realized only by storing an input signal, addition processing, division processing, or bit shift processing, the entire processing is simple and easy to realize.

  (2) Frequency analysis is possible without performing FFT analysis with a large amount of calculation.

  (3) Since a filter such as a bandpass filter is not used, calculation can be easily performed without worrying about calculation accuracy.

  (4) A desired frequency component can be extracted with higher accuracy than using a filter such as a bandpass filter.

(Modification)
In the above embodiment, the peak value (amplitude) is output as a level, but the peak value / 1.4 (effective value) may be output as a level.

[Second Embodiment]
FIG. 8 is a configuration diagram showing a frequency analysis apparatus 100 according to the second embodiment of the present invention.
The frequency analyzing apparatus 100 includes a plurality of, for example, four input buffers 31a, 31b, 31c, and 31d commonly connected to an input terminal In, and arithmetic operations connected to the input buffers 31a, 31b, 31c, and 31d, respectively. The units 32a, 32b, 32c, and 32d and the control unit 33 that controls the entire apparatus are provided to extract the levels of the four extraction target frequencies.

  Assuming that one period of the four extraction target frequencies is Ta, Tb, Tc, and Td, the input buffer 31a stores the Ta time of the input signal. The input buffer 31b stores the Tb time of the input signal. The input buffer 31c stores the Tc time of the input signal. The input buffer 31d stores the Td time of the input signal.

  The calculation units 32a, 32b, 32c, and 32d connected to the input buffers 31a, 31b, 31c, and 31d are controlled by the control unit 33, and the input signals stored in the input buffers 31a to 31d It operates in the same manner as the calculation unit 32 of the first embodiment, and can extract four frequency levels and waveforms to be extracted.

  Therefore, the frequency analysis apparatus 100 according to the present embodiment has the same advantages as the first embodiment, and has the advantage that four extraction target frequency levels and waveforms can be extracted.

[Third Embodiment]
FIG. 9 is a configuration diagram showing a frequency analysis device 100 according to the third embodiment of the present invention.
The frequency analysis apparatus 100 includes an input buffer 41 connected to an input terminal In, four arithmetic units 42a, 42b, 42c, and 42d connected to the input buffer 41, and a control unit 33 that controls the entire apparatus. Provided, and extracts the levels of the four extraction target frequencies.

  The size of the input buffer 41 is set to a size that can store one cycle of the lowest frequency among the frequencies to be extracted, and the length for storing the input signal is selectively set by a control signal from the control unit 33 or the like. It can be changed in 4 stages. The calculation units 42a, 42b, 42c, and 42d connected to the input buffer 41 are the same as the calculation units 32a, 32b, 32c, and 32d of the second embodiment.

  Assuming that one cycle of the four frequencies to be extracted is Ta, Tb, Tc, and Td, the input signal stored in the input buffer 41 is set in a period in which the input buffer 41 is set to store an input signal for Ta time. On the other hand, the calculation unit 42a operates in the same manner as the calculation unit 32 of the first embodiment, and extracts the level and waveform of the extraction target frequency in which one period is Ta.

  During a period in which the input buffer 41 is set to store the input signal for Tb time, the calculation unit 42b performs the same operation as the calculation unit 32 of the first embodiment on the input signal stored in the input buffer 41. Operates and extracts the level and waveform of the frequency to be extracted for which one period is Tb.

  During a period in which the input buffer 41 is set to store the input signal of Tc time, the calculation unit 42c operates on the input signal stored in the input buffer 41 in the same manner as the calculation unit 32 of the first embodiment. Operates and extracts the level and waveform of the extraction target frequency for which one period is Tc.

  During a period in which the input buffer 41 is set to store an input signal of Td time, the calculation unit 42d performs the same operation as the calculation unit 32 of the first embodiment on the input signal stored in the input buffer 41. Operates and extracts the level and waveform of the frequency to be extracted for which one period is Td.

  In other words, the frequency analysis device 100 according to the present embodiment is obtained by replacing the four input buffers 31a, 31b, 31c, and 31d of the frequency analysis device 100 according to the second embodiment with one input buffer 41. And has an advantage that the configuration is simpler than that of the second embodiment.

In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. Examples of such modifications include the following.
(I) In the first to third embodiments, the level of the frequency component to be extracted is obtained by adding the input signals stored in the input buffers 31, 31 a to 31 d, 41 a plurality of times and obtaining an average thereof. However, when analyzing whether or not the frequency to be extracted is included in the input signal, it is not necessary to obtain the average. In this case, since the frequency components other than the extraction target are removed only by adding the input signals stored in the input buffers 31, 31a to 31d, 41 a plurality of times, whether or not the frequency to be extracted is included in the input signal. Can be analyzed.

  (Ii) In the second embodiment, the four input buffers 31a to 31d and the calculation units 32a to 32d are provided in the same number as the number of frequencies to be extracted. However, the input buffers 31a to 31d and the calculation units 32a to 32d are provided. The number of frequencies to be extracted can be increased or decreased by increasing or decreasing the number of.

  (Iii) In the third embodiment, the length of storing the input signal of the input buffer 41 is changed in four stages. However, the length of storing the input signal of the input buffer 41 is set to other than four stages. Also good. In this case, the number of frequencies to be extracted can be increased or decreased by changing the number of calculation units 42a to 42d accordingly.

  (Iv) The input signal may be a signal representing sound, a signal representing an image, or a signal output from various sensors.

  (V) In the first to third embodiments, the presence / absence and level of the signal component of the target frequency are obtained every 8 frames, but the presence / absence / level may be obtained in units of frames.

Hereinafter, a frequency analyzing apparatus capable of this kind of processing will be described as a fourth embodiment.
[Fourth Embodiment]
FIG. 10 is a configuration diagram showing a frequency analysis device 200 according to the fourth embodiment of the present invention.
In the frequency analysis device 200, the arithmetic unit 32 includes an addition result register 321, an arithmetic circuit 329, n registers 341 to 34n, and a control unit 33 that controls the entire apparatus.

  The registers 341 to 34n are connected in cascade, and transfer m data stored therein to a subsequent register according to the control of the control unit 33, and receive m data supplied from the previous register. Newly memorize.

  The arithmetic circuit 329 adds the data of nFrame stored in the registers 341 to 34n with the same relative position in the Frame, and stores the value obtained by dividing the added value by n in the addition result register 321. This is the output of the calculation unit 32.

  Each time m pieces of data for one frame are stored in the input buffer 31, the data is stored in the register 341. Further, the data stored in the registers 341 to 34 (n-1) is stored in the subsequent registers 342 to 342. 34n.

  The arithmetic circuit 329 averages the input signals for the past n frames in units of Frame and stores them in the addition result register 321.

  Therefore, whether or not a signal of the target frequency is included in the frame unit, and if it is included, the level can be obtained.

  The present invention includes a program for causing a computer to realize the functions of the apparatus described above. These programs may be read from a recording medium and loaded into a computer, or may be transmitted via a communication network and loaded into a computer.

31, 31a to 31d, 41 input buffer 32, 32a to 32d, 42a to 42d arithmetic unit 33 control unit

Claims (9)

An input buffer for storing, as a signal segment, an input signal input at the predetermined time every predetermined time corresponding to one period of the extraction target frequency;
A register for holding a cumulative addition result obtained by cumulatively adding the signal values of the signal segments supplied from the input buffer at the predetermined time at the respective time points within the predetermined time; Each time, the cumulative addition result held in the register and the signal segment newly supplied from the input buffer are added together at the same time point within the predetermined time, and a new value is added. An operation unit for obtaining a cumulative addition result and holding the new cumulative addition result in the register;
A frequency analysis apparatus comprising:   The frequency analysis apparatus according to claim 1, wherein the arithmetic unit divides the cumulative addition result by the number of times of cumulative addition. A plurality of the input buffers and the arithmetic units are installed corresponding to a plurality of extraction target frequencies,
The frequency analysis apparatus according to claim 1 or 2, characterized by the above. An input process for holding an input signal input at the predetermined time as a signal segment for each predetermined time corresponding to one period of the extraction target frequency;
The signal unit held at every predetermined time is held in a cumulative addition result obtained by cumulatively adding the signal values at each time point within the predetermined time, and the held time is held each time the predetermined time elapses. A signal value at the same time point within the predetermined time is added to each of the cumulative addition result and the newly input signal fragment to obtain a new cumulative addition result, and the new cumulative addition result is retained. An arithmetic processing to be held instead of the cumulative addition result,
The frequency analysis method characterized by performing.   The frequency analysis method according to claim 4, wherein in the calculation process, the cumulative addition result is divided by the number of times of cumulative addition. The input process and the arithmetic process are respectively performed corresponding to a plurality of extraction target frequencies.
The frequency analysis method according to claim 4 or 5, wherein An input procedure for holding, as a signal segment, an input signal input at a predetermined time every predetermined time corresponding to one cycle of the extraction target frequency in the computer;
The signal unit held at every predetermined time is held in a cumulative addition result obtained by cumulatively adding the signal values at each time point within the predetermined time, and the held time is held each time the predetermined time elapses. A signal value at the same time point within the predetermined time is added to each of the cumulative addition result and the newly input signal fragment to obtain a new cumulative addition result, and the new cumulative addition result is retained. Calculation procedure to be held instead of the cumulative addition result,
A program characterized by having executed.   The program according to claim 7, wherein in the calculation procedure, the cumulative addition result is divided by the number of times of cumulative addition. The input procedure and the calculation procedure are executed corresponding to a plurality of extraction target frequencies,
The program according to claim 7 or 8, characterized in that.

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