JPS6017260B2 - Digital to analog converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital-to-analog converter that converts a digital signal into an analog signal, and in particular, it is capable of processing a multi-bit digital signal and is capable of disposing a large number of resistors on a single chip semiconductor substrate. It relates to a potentiometer-type digital-to-analog converter.

Digital to analog converter (hereinafter referred to as TDA converter)
There are three widely known types: '11 integral type, '21 binary weighted addition type, and '31 potentiometer type. Here, the integral type '1} obtains an analog signal by integrating the number of pulses corresponding to the digital value, and although it is simple, it can handle only a few numbers, cannot achieve high precision, and is slow. . Next, the '2-binary weighted addition type converts the digital value represented by the binary code into electrical analog quantities (current, charge, voltage, etc.) for each digit. By adding, an analog value corresponding to the digital value is obtained, and the analog amount for each digit is weighted according to the binary number.

Also, the response speed during conversion is long. FIG. 1 shows such a binary weighted addition type DA converter 51.
Input terminal 52. m resistors 53 corresponding to m-bit digital inputs Do~Dm-, supplied to ~52m-,
. ~53m-, is provided. Each resistor 53 is connected by a constant voltage source 58. ~53m-, since a constant voltage Er is applied to these resistors 53. ~53m-, the current that can flow through them is determined only by their respective resistance values. Here, these resistance values are resistor 53. R, R/2 sequentially from
, R/4... and multiplying by 1/2, the resistance becomes 53m-,
becomes 2-elbow IR, and these resistances are 53. ~53m-
, are sequentially doubled and weighted according to the binary number. Each of these resistors 53o to 53m is a switch 54. .about.54m-, and are connected to the negative side input terminal of the oven amplifier 55. The switches 54o to 54m-, respectively correspond to the values Do to Dm- of each digit of the m-bit digital signal, respectively.
The current i supplied to the negative side input terminal of the obeamp 55 is as follows. Therefore, a current i is obtained as an analog quantity corresponding to a digital value. The obeamp 55 converts this current i into a voltage V. This obeamp 55
When the resistance value of the negative feedback resistor 66 connected to is r,
The voltage V obtained at the output terminal 57 is V=-lr
......■, and there is a near relationship with the current i.

Next, FIG. 2 shows a binary weighted addition type DA converter 61 called an R-group ladder type, and has an input terminal 62.

m-bit digital input Do supplied to ~62m-,
.about.Dm-,, m-1 resistors 63 having a resistance value R and m11 resistors 64 having a resistance value R are used. This is done by connecting two resistors 64 in parallel to obtain a resistance value of R, then connecting a resistor 63 in series to this to set the resistance value, and then sequentially connecting fox resistors 64 in parallel to obtain R. The resistors 63 of the stations are connected in series, and the resistors 64 of the stations are connected in parallel to form a ladder resistance matrix. The resistance value of the entire resistance matrix is R, and if a constant voltage source 68 of voltage Er is connected to this, the current flowing through the m next resistors 64m-, ~640, is 2-2-drops, 2-2-drops, 2-2 - Heavy R, ---, 2-m-The remaining fox resistance value is 64'' or 64.

This is equal to 2-m. In addition, the above m love resistances 6
4o~64m-, selector switch 65o~ between and ground
65m-, and connect each ground side switching terminal a.
The other switching terminal b is commonly connected to the switch 65. ~65m-, corresponds to the value of each digit of the digital signal ■o~Dm-, and the value is "0"
If the switch is made to switch to the terminal a side when the signal is "1" and to the terminal b side when the signal is "1", the current i obtained from the terminals to which the terminals b are commonly connected is as follows.

This fin flow i is converted into a voltage V by an oven amplifier 66 and sent to an output terminal 67. However, these binary weighted addition type DA converters obtain monotonicity, that is,
In order to ensure that the relationship between any two digital values is always the same for the corresponding analog values, the precision of the resistance value is as follows for an m-bit digital value:
A relatively high height of 2-m is required. Also,
Even if the error in the resistance value is relatively 2-m, the peak B (Lea
The error of stSi Yanagi finiteBit (the least significant bit) is close to ±100%, and the differential linearity and Kobashi characteristic become very poor. For this reason, a monolithic type DA converter without resistance trimming has a limit of 8 bits, and with resistance trimming, the fuse R
Even a monolithic type used in combination with OM etc. has a limit of 12 bits. Furthermore, when it comes to 12 bits or more, it is limited to hybrid types with highly accurate resistance trimming.
Prices soar. Next, the potentiometer type {3} is the simplest in principle and has the advantage of providing reliable monotonicity and excellent differential linearity.

FIG. 3 shows the basic circuit of this potentiometer-type DA converter 71. In order to convert m-bit digital inputs Do to Dm-, to the input terminals 72o to 72m-, 2m-1 resistance 73.・7321...... are connected in series and inserted between the constant voltage source 74 and the ground, and 2m voltages from each connection point of these resistors (including the constant power source and the ground) The output is connected to 2m switches 75.・
752. Only one of these switches 751, 752, . . . is turned on depending on the m-bit digital value. Here, since the input digital signal is binary encoded,
An address decoder 76 is required that selects one of the 2m outputs in response to each m digit input,
2m switches 75 according to the power of this world.・752
One of them turns on. These switches 7
5. The voltage as an analog quantity obtained through 752, . . . is amplified by an oven amplifier 77 and sent to an output terminal 78. Note that the address decoder 76
In place of the switches 751, 752, . . . , a tree-shaped switch matrix 82 like the potentiometer-type DA converter 81 shown in FIG. 4 may be used.
This switch matrix 82 has digital inputs Do to D.
By appropriately wiring a group of changeover switches that operate in accordance with m-, one of the 2m connection points is selected. Changeover switches 83...832...
... switches two non-overlapping connections among the 2m connection points, and operates in accordance with the next digit input D, 2.
m-2 changeover switches 84.・...is to switch each of the 2m-1 changeover switches that do not overlap, and then reduce the number of changeover switches that are sequentially interlocked by 1/2.
By wiring to switch each of the two non-overlapping switches in the previous stage (one level lower), digital communication can be achieved by simply using 2m-1 switch (without the need for an address decoder). Input Do~Dm-
, one connection point corresponding to , can be selected. The other configurations are the same as in FIG. 3, and the same parts are given the same reference numerals. However, in potentiometer-type DA converters such as those shown in Figures 3 and 4, the configuration becomes complicated as the number of input bits increases, and in particular, the entire circuit of the DA converter is patterned on a single semiconductor substrate. In this case, it is difficult to increase the number of bits because a large area is required.

This means that for one series of series resistors, a switch 75 and an address decoder 76 are connected in parallel with this series resistor.
(or a tree-type switch matrix 82 as shown in FIG. 4).If the number of input bits increases, multiple DA converters 86 as shown in FIG. Switch 75 and address decoder 76
, or a control unit 8 equipped with a switch matrix 82, etc.
There is a limit to the extent to which the series resistors 73 can be arranged around the resistors 7, and it is impossible to significantly increase the number of resistors. Further, in the potentiometer type, since the resistors are connected in series, the output impedance becomes considerably high as the number of bits increases (approximately 100 k○ for 10 bits), which is a drawback. Furthermore, as the number of bits increases and the number of series resistors increases, the size of the resistor element pattern on the semiconductor substrate must be reduced, and the variation in each resistance value increases, making the output analog voltage unstable. There are many people who are obsessed with low accuracy. The present invention has been made in view of the above-mentioned conventional circumstances, and its purpose is to not only have the features of a potentiometer type that is high speed, high precision, and good linearity, but also to have a simple circuit configuration. Moreover, even when the number of digital input bits increases and the total number of resistors increases, the maximum output impedance can be lowered and the DA
It is an object of the present invention to provide a digital-to-analog converter that can speed up the conversion operation and obtain an analog output voltage stably and with high precision. Before explaining the embodiments of the present invention, a DA converter as a prior art of the present invention will be explained with reference to FIGS. 6 to 8. That is, FIG. 6 shows a DA converter 1 according to the prior art of the present invention, which operates as a potentiometer type DA converter.

m input terminals 2 of this DA converter 1;・22・…・2
m- is an m-bit digital input D.・D.・・・．
...Dm-, is supplied. These digital inputs Do/D. ...Dm-, of which there are so many digital inputs Do and D. ...D So-. is sent to the address decoder 4 via the input inverting circuit 3, and one of the 2 Y addresses corresponding to the digital inputs Do to D-1 is selected. Also, m-digital inputs D, D,+. . . . Dm-, is sent to the X address decoder 5, and one address out of the 2m- pieces of X addresses is selected in accordance with the digital input Dm-, Dm-,. Here, the digital input D is the input inverting circuit 3
It is also sent to Next, a plurality of pieces (in the example, 2 m - 1
) resistors 6 are connected to the power terminal 7E and the ground terminal 7. By inserting and connecting them in series, 2m connection points of mutually different potentials (including the connection point between the power supply and the resistor, and the connection point between the ground and the resistor) are obtained. These 2m connection points are arranged two-dimensionally so that there are 2m-k connection points for x and 2〆 connection points for Y. This can be done by arranging series-connected series resistors 2m apart in the X direction. These series resistors are turned back and connected in series each time the x address advances by 1, and are formed in a meandering shape as a whole. However, the series resistance at the highest address (or lowest address) of X is 2-1. In this way, 2m-1 resistors connected in series are arranged in the two dimensions of x and Y, so that the 2m connection points are arranged at two
m-so x 2 pieces are arranged, and 2 pieces are arranged corresponding to these connection points.
m switches are connected to each other. That is,
2m - any one of its X addresses has
Two connection points arranged in the Y direction correspond to each other, and the two switches 8 connected to these connection points are connected to a switch 9 with their other ends commonly connected. These 2m switches 9 are provided in correspondence with the X address, and the ends of these 2m switches 9 are connected in common, and one output terminal is connected. Of these 2m switches 9, only those selected by the address selection signal from the X address decoder 5 are turned on. Next, any one of the 2 Y addresses corresponds to 2m-〆 connection points arranged in the x direction, and the 2m-〆 switches connected to these connection points are: It is turned ON by the selection signal of the address. Therefore, one of the 2m connection points is selected by the X address decoder selecting one address among 2m and the Y address decoder 2 selecting one address among them. By the way, since the series-connected resistors are arranged in a meandering manner by folding back every x address, the order of the Y addresses is reversed when the number of x addresses is an odd number and when it is an even number. The odd number or even number of this X address is determined by the least significant bit input D of the m-bit digital input D so ~ Dm- supplied to the x address decoder 5, so this digital input D It is necessary to invert the digital inputs Do to D so-, to the Y address decoder 4, in accordance with the above. An input inverting circuit 3 is provided to perform this inversion, and an example of the internal circuit configuration will be described with reference to FIG. The input inverting circuit 3 shown in FIG. 7 includes an inverter 1 and a NOR gate 1.
2, and the digital inputs Do~D so-
When the inverting circuit output corresponding to
・As is clear from FIG. 7, the output Ai corresponding to 1) is AF(D'+D〆)10(D,10Dso) .・・・．・・・． ...■ (However, Di indicates the negation (inversion) value of Di, and 10 indicates the logical sum (OR).

) can be expressed as Calculate this ■ formula, AFD, 〇 evening +
D.・〇Evening …………■(However, ・ is a logical product (AN
D) is shown.

), and for the value of D 0 or 1, when ○ evening = 0, Ai = Di ......■○ when so = 1, Ai =
Di …………■ becomes.

As a specific example of the above general configuration, m=4, so=
2 and the power supply voltage is 1.5V, the DA converter 1 will be described with reference to FIG.

In this FIG. 8, there are four input terminals 2.・2.・22・2
3. Digital input Do/D.・D2 and D3 are supplied, and the lower bit digital input Do, D, becomes a digital signal via the input inverting circuit 3 ・A, becomes the Y address decoder 4, and the upper 2 bits digital input D2 and D3 are sent to the x address decoder 5, respectively. Furthermore, the least significant bit digital input D2 of the digital inputs for the X address is also sent to the input inverting circuit 3. Next, in order to obtain 24 = 1 stitch resistor connection points, 13 resistors 6, to 6, 5 are connected to the ground terminal 7o, . 5V power supply terminal 78, and as shown in FIG. ) are folded back to form a meandering pattern. These 19 series connected
16 different voltages (OV
and 1.5V) and connect one of these to the digital input D. ~X address and Y according to D3
By selecting based on the address, an analog quantity output (voltage output) corresponding to the input digital value can be obtained. This is a one-needle box of MOSFET 8 at the 16 connection points above.
The sources (or drains) of the ×
Every four MOSFETs 8 arranged in the direction are turned on. In addition, four MOSFETs 8 arranged in the Y direction
The drains (or sources) of each are commonly connected as output lines, and these four output lines are connected to four MOSFETs 9.
~93 sources (or drains), and the drains (or drains) of these four MOSFETs9.
(or source) are connected in common, and one analog output terminal is connected. One of the four MOSFETs 9 on the output side is set to N according to the address selection signal from the X address decoder 5. MOSF used here
As ET8 and 9, N-channel MOS, P-channel M○S, CMOS, etc. can be used. The resistor 6 may be made of polycrystalline Si doped with impurities or single crystal Si.
You can use the inside diffusion area etc. Table 1 shows the relationship between the digital input and analog input of the circuit shown in FIG.

Table 1 According to the prior art of the present invention as described above, since the resistor 6 and switch 8 are arranged two-dimensionally in the X and Y directions,
To obtain a DA converter that has the advantages of a potentiometer such as high speed, high precision, and good linearity, can further reduce the pattern area when integrated into an IC, and can be easily mass-produced and supplied at low cost. I can do it.

By the way, generally speaking, the output terminal 101 often has a capacitance 10c of about lopF, but if each of the resistors 6 is about 10 resistors, in the case of 12 bits, 4099 resistors will be connected in series, and the total Resistance is approximately 40 arc○
The maximum output impedance when taking out the voltage from the approximately central connection point of the series resistor is approximately 100k○, so even with a small capacitance of about F in 1 above, the time constant is 1〆sec.
As a result, the response speed of the conversion operation decreases.

Even in the case of 10 bits, the total resistance is about 100kQ,
The maximum output impedance is approximately 2 balls, which is not desirable. Furthermore, as mentioned above, as the number of digital input bits m increases, the number of series resistors increases exponentially (at least 2m).
each resistor pattern on the semiconductor substrate.
It is not possible to increase the size of the resistor, and a 4-size resistor must be used. However, when an IC is constructed using resistive elements with such a small pattern size, the variation in the resistance value of each resistor becomes considerably large, resulting in a decrease in the accuracy of the output analog voltage. In consideration of these points, in the present invention, the maximum output is achieved by connecting an additional resistor in parallel to every predetermined number of resistors 6 to the plurality of series resistors 6 formed in the meandering shape. It is intended to lower the impedance.

That is, FIG. 9 shows a DA according to the first embodiment of the present invention.
The main parts of the converter are shown, and one folded part of the meandering series resistor 6 shown in FIG. 6 is shown.

In FIG. 9, adjacent folding points on one side of a meandering pattern in which a plurality of resistors 6 are connected in series are successively connected by additional resistors 13. One additional resistor 13 is connected in parallel to two rows of 2Z resistors 6 connected in series in the direction, that is, 2.2〆 series resistors 6.
The output impedance of a resistor with this configuration is
When calculating for 10 bits assuming that each resistor 6 and 13 are all 1000, the center connection point of all the resistors is approximately 40
Below the plate, the point from this central connection point through two resistors has the maximum output impedance, which is approximately 1. It can be seen that this is an extremely low value compared to the above-mentioned approximately 2 balls and 0. Other configurations and operations are shown in FIGS. 6 to 8 described above.
Since this is the same as the prior art described with the figures, the description will be omitted. Next, FIGS. 10 to 13 show specific examples in which a DA converter circuit like the above-mentioned second embodiment is configured on a single semiconductor (for example, Si) substrate. Fig. 10 is a block diagram showing the overall arrangement, Fig. 11 is a schematic plan view showing the wiring pattern of the resistor/switch matrix circuit on the Si substrate, and Fig. 12 is a plan view showing the basic pattern of Fig. 11. , FIG. 13 is a sectional view taken along line 1-1 in FIG. 12.

In these figures, the same reference numerals are given to the parts that perform the same functions as in FIG. 6, and the explanation will be simplified. In this specific example, a DA converter 1 is shown which converts a 10-bit digital input Do to D9 into an analog output, and has one fixed input terminal 2.

~29 The digital input Do~○9 supplied with V is
First, it is sent to a 10-bit latch circuit 14, and from this latch circuit 14, D is sent. ~D4 is input to Y via input inverting circuit 3
Address decoder 4 and D5 to D9 are sent to X address decoder 5, respectively. As described above, the input inverting circuit 3 outputs D according to the value of the digital input D5. ~D
Flip 4. Each of these X/Y address decoders 4.5 selects one address out of 32 addresses in response to a 5-bit input. A matrix circuit 15 including a resistor 6 and switches 8 and 9 outputs an analog output voltage from one connection point selected by the X address and Y address among the connection points corresponding to 32×32=1024 addresses. Send terminal 1 river. These circuits are formed on one SJ substrate 20 using IC technology, but the latch circuit 14, the X/Y address decoders 4 and 5, and the input inverting circuit 3 are formed using conventionally known circuits. The explanation will be omitted because it can be easily constructed using conventional technology.

Next, although various configurations are possible for the resistor and switch matrix circuit 15, in order to simplify the wiring, an A (aluminum) wiring pattern is mainly used in the x direction, and an impurity-doped wiring pattern is used in the y direction. polycrystalline S; (
Polysilicon) wiring patterns and resistance patterns are used. Furthermore, a MOSFET formed on the Si substrate 20 is used as a switch. That is, the 11th
In the figures to FIG. 13, a polycrystalline Si layer resistance pattern 21 arranged linearly in the Y direction consists of two (32) resistors 6 each connected in series in the Y direction in the circuit. The resistance patterns 21 are arranged in 2m lengths (32 patterns) in the x direction. For one low resistance pattern 21, two connection points 22 are set at equal intervals in the Y direction, and these connection points 22 are electrically connected to the source (or drain) region 24 of the MOSFET 23.

Here, the A layer 28 formed at the connection point 22 of the resistor pattern 21 is made to have the same shape and current flow at the turn-around point of the resistor and the same conditions as each connection point 22, and each resistance value is This is to improve the accuracy of Next, the MOSFET 23 faces, for example, the surface of the P-type Sj substrate 20 and has N+ type source and drain regions 24 and 2.
A polycrystalline Si gate 5 is formed by diffusion, ion implantation, etc., and doped with impurities on the Si substrate surface between these source and drain regions 24 and 25 via an insulating layer (for example, a SiQ layer) 26. 27 is formed. This gate 27 is electrically connected to a wiring pattern 29 of the A-layer layer arranged linearly in the x direction. Thirty-two wiring patterns 29 are arranged in parallel, and each address selection signal of the Y address decoder 4 is connected to the gate 27 of the MOSFET 23. Next, the drain (or source) regions 25 of the MOSFETs 23 are commonly connected through the three wire patterns of the impurity-doped polycrystalline Sj every two (32) arranged in the Y direction, and each MOS
It is electrically connected to the source (or drain) region 32 of the FET 31.These MOSFETs 3 1
An address selection signal from the X address decoder 5 is supplied to the gate 33 of the gate 33 . In addition, these MOSFE
The drain (or source) region 33 of T31 is commonly connected by the wiring pattern 34 of the layer A, and is electrically connected to the output terminal 10. (See Figure 10) Here, MOSFET 23 is connected to switch 8 in Figure 6.
The FETs 31 correspond to the switches 9 in FIG. 6, respectively. In addition, regarding the folded portion of the resistor 6 in FIG. 6, the two ends of the resistor pattern 21 are electrically connected alternately by the wiring pattern 35 of the layer A, so that the whole is connected in series. There is. Moreover, the wiring pattern 35 on one end side of these resistance patterns 21 is as follows.
They are connected at equal intervals to a resistance pattern 36 of polycrystalline Si doped with impurities, which corresponds to the additional resistance shown in FIG. According to the first embodiment of the present invention as described above, the resistor 6 and the switch 8 such as the MOSFET 23 are
Since the number of digital input bits is large, it is possible to form a pattern in a relatively large area on a semiconductor substrate.
Even with a 10-bit input DA converter as shown in Figure 3,
It can be constructed using an extremely small Si chip of approximately 2.6 x 2.9 sides.

Furthermore, the additional resistor 13 allows the output impedance to be kept extremely low, thereby increasing the operating speed of the DA converter. Furthermore, when the number of digital input bits is large (m) and the number of series resistors 6 increases exponentially (to at least 2m pieces), the pattern size of each resistive element on the semiconductor substrate must be reduced. too,
The number of the additional resistors 13 is about 2m-Z-1, which is smaller than the series resistor 6, and the pattern size of these additional resistors 13 can be made relatively large, and variations in resistance values can be reduced. Therefore, the potential at each connection point of the additional resistor 13 becomes highly accurate and stable, and the analog output voltage obtained by further dividing this by the series resistor 6 also becomes highly accurate and stable.
The accuracy of conversion can be significantly improved. By the way, in actual usage of a DA converter, non-linear conversion is often performed during DA conversion from the viewpoint of reducing quantization noise.

If this non-linear conversion is performed before or after the DA converter, an extra circuit will be required, so it is preferable to provide the DA converter itself with a desired non-linear transfer characteristic. To perform this with a general potentiometer-type DA converter, the resistance values of the series-connected resistors 6 are sequentially changed according to a desired nonlinear function (often exp, sinh, cosh, etc.). However, when integrated into an IC, the regularity of the resistance pattern will be disrupted, which is not preferable. FIG. 14 shows the main parts of a second embodiment of the present invention that improves these points, and the same references are used for parts corresponding to the prior art and the first embodiment described above. Numbered.

In FIG. 14, one folding point 7 (including the power supply terminal 78) of the pattern formed by folding and arranging the resistors 6 connected in series in a meandering manner as described above.

) are connected by first additional resistors 13 each having a resistance value Ro. This is equivalent to 1 first resistor for 2.2 series resistors.
This is equivalent to additional resistors 13 connected in parallel. next,
connection point 7 of these first additional resistors 13; 7n (however, power supply terminal 7E is not included) and ground, second additional resistors 16 each having a resistance value r. Insert and connect ~16n. Further, the grounding terminal 7o in the first embodiment described above is grounded via a resistor 17 having a resistance value Rt. In such a configuration, when the number of series resistors in the Y direction is sufficiently large, the voltage of the power supply is Er, and each point 7.

・7.・...・The potential of 7n is sequentially eo, e.・
...en (however, n=1/2・2m-t+1), then the electric potential ek at any point (however, k=0・1...
・n) is Rt depending on the condition of the resistance value Rt of the resistor 17.
=Nor・R:ek =Erepx(1(n-k)ノRearfu7)・….・■ Rt2: ek; Bag washing hand that washes away the yellowtail potatoes -. -. ---
‐‐■Wanibi plan section side…■Rtni0: eknishi skin (n
It becomes or.

The relationships between ek and k in these equations 2, 2, and 2 are shown in curves 2, 2, and 2 in FIG. 15, respectively. Therefore, a D~ converter that can be converted into a non-linear doji with a simple configuration can be obtained. next,
FIG. 16 shows a DN converter 40 according to a third embodiment of the present invention.
, and the lower bits of the least significant bit of the m-bit input main DN converter 41 are taken over by the i-bit input rich plate A converter 42 to significantly increase the number of input bits. It is.

Here, the internal configuration of the main DA converter 41 is the same as that of the first embodiment described above, so it is not shown and the explanation will be omitted. The sub-DA converter 42 may have the same configuration as the first embodiment, but if the number of input bits is small, a binary weighted addition type or a conventional potentiometer type DA converter may be used. A container may also be used. In FIG. 16, digital inputs Do to DH from the least significant digit to the i-th digit of all digital inputs are sub-D to j input terminals 2 of the converter 42.

~2i-. and digital inputs Dj to Dm+j- from the 11th digit to the most significant digit (m+j digit).
, are supplied to m input terminals 2i to 2mj-, of the main DA converter 41. The output terminal 43 of this main DA converter 41 is connected to the positive input terminal of the obeamp 44,
The output terminal of this obeamp 44 is the analog output terminal 4.
5 and is also connected to the negative input terminal via a feedback resistor 46. Output terminal 47 of sub-DA converter 42
is connected to the positive input terminal of the OBE amplifier 48, and the output terminal of the OBE amplifier 48 is connected to the negative input terminal to form a negative feedback loop, and is also connected to the negative input terminal of the OBE amplifier 44 via a resistor 49. . Figure 17 A-C
shows the input/output characteristics of such a DA converter 40, and the horizontal axis shows the digital input in BB units.
The vertical axis shows the analog output potential.

First, FIG. 17A shows the input/output characteristics of the main DA converter 41, and the LSB corresponds to the i+1st digit input Di of the entire digital input. If the potential difference (voltage) of the analog output of 1 with respect to B is Eo, the power supply voltage Er is approximately 2 m·Eo. The accuracy of this voltage is based on the first
It is equal to the accuracy of one resistor 6 connected in series in the embodiment, and is, for example, within several percent of the error rate. Next, FIG. 17B shows the input/output characteristics of the rich plate N converter 42, where the LSB corresponds to the first digit digital input Do, and the MSB corresponds to the i-th digit input Dj-, . Here, the potential difference (voltage) of the analog output for the 2MSB is converted to the main DA converter 4.
By making it approximately equal to the voltage Eo of ILSB of 1,
Voltage Eo is approximately 1/a according to digital input Do to DH
The voltage corresponding to 1 and B of the sub DA converter 42 is Eo/2j. Therefore, by adding (or subtracting) the analog outputs of the main DA converter 41 and the sub DA converter 42, as shown in FIG.
/2j as a unit, an analog output that can change in 2-j steps from 0 to Er (=-m・Eo) can be obtained, and an extremely large number of bits can be converted to m + i bits at once. become. For example, in conventional binary weighted addition type DA converters (see Figures 1 and 2), an error of about 50% still occurs even though extremely high-precision resistors are used. Adding bits is almost impossible, but in this embodiment, the main DA converter 41 performs high-precision DA conversion using the configuration of the present invention. Addition of the lower bits of the BB can be easily performed with relatively high accuracy. As is clear from the above description, the digital-to-analog converter of the present invention has the features of a conventional potentiometer-type DA converter, while simplifying the circuit configuration and reducing the pattern area when integrated into an IC. By connecting additional resistors in parallel to each predetermined number of series resistors formed in a meandering pattern, the maximum output impedance can be kept small even when the number of bits increases.
The operation speed during conversion can be further increased.

Furthermore, since the number of additional resistors is extremely small compared to the number of series resistors, it is possible to make the element pattern size of each additional resistor relatively large to reduce variation in resistance values, thereby improving the accuracy of analog output voltage. It becomes possible to increase and stabilize the temperature. Note that the present invention is not limited to the DA converter, but also compares the analog input with the output from the DA converter,
A comparison type AD converter that obtains a digital output corresponding to this analog input (for example, a successive approximation type or a counting type A
D converters and the like are known.

) may be used to perform rainbow transformation.

[Brief explanation of drawings]

1 and 2 are schematic diagrams showing different conventional examples of the binary weighted addition type, and FIGS. 3 to 5 are circuit diagrams showing different examples of the potentiometer type. 6 to 8 show the prior art of the present invention, FIG. 6 is a basic circuit diagram, FIG. 7 is a circuit diagram showing an example of the input inverting circuit 3 of FIG. 6, and FIG. It is a schematic diagram showing a specific example. 9 to 13 show a first embodiment of the present invention, FIG. 9 is a circuit diagram showing main parts of the first embodiment, and FIG.
Figure 0 is a block diagram showing the overall arrangement, Figure 11 is the Si
A schematic plan view showing the wiring pattern of a matrix circuit of resistors and switches on the board, Fig. 12 is a plan view showing the basic pattern of Fig. 11, and Fig. 13 is a sectional view taken along line 1-1 of Fig. 12. be. 14 and 15 show a second embodiment of the present invention, FIG. 14 is a circuit diagram showing the main part, and FIG. 15 shows each connection point 7 in FIG. 14. It is a graph showing the output voltage of ~7n. 16 and 17 show a third embodiment of the present invention, FIG. 16 is a block diagram showing the whole, and FIGS. 17A, B, and C show the main DA converter 41, sub-DA converter 42 and the entire DA converter 40
3 is a graph showing the input and output characteristics of each. 2...
...Input terminal, 3...Input inversion circuit, 4...
・Y address decoder, 5...×address decoder, 6
...Resistance, 8...Switch, 14...
...(first) additional resistance, 16...(second)
) additional resistance. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 15 Figure 14 Figure 16 Figure 17 figure

Claims (1)

[Claims] 1 In a potentiometer-type digital-to-analog converter, the m-bit digital input is converted into upper m-l bits (l<
m), and lower l bits, connect multiple resistors in series between the power supply terminal and ground to obtain 2^m different connection points, and connect these connection points to 2^ with respect to X. The plurality of resistors are two-dimensionally arranged in a meandering manner so that there are m^-l pieces and 2l pieces for Y, and the above-mentioned m-
In response to the l-bit digital input, the X address decoder selects one address out of 2^m^-l addresses, and in response to the l-bit digital input, the Y address decoder selects one of the 2l addresses. 1 address is selected, and the output from the connection point determined by these selected X and Y addresses is made into an analog output, and every predetermined number of series resistors is A digital-to-analog converter characterized in that the output impedance is lowered by connecting an additional resistor in parallel to the converter.