JP3461339B2 - Resistor ladder type digital / analog converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistance ladder type digital / analog converter, and more particularly to an MO as a switch element.
The present invention relates to a layout structure of a resistance ladder type digital / analog converter using an S (Metal Oxide Silicon) transistor.

[0002]

2. Description of the Related Art As is well known, a resistance ladder type digital / analog converter (hereinafter referred to as "D / A converter") has 2 ⁿ resistors (referred to as unit resistance) between two reference voltages. the pressure in series connection min, switching the 2 ⁿ pieces of resistive partial pressure in the 2 ⁿ switch, refers to a signal converter which they were taken out as an analog output voltage. Here, n is the number of bits of the digital input signal that is an input to the switch. Such D / A converters have been known for a long time, but in recent years, the demand for integrated circuits in which analog signals are mixed has become strong. Also, video and CCD (Charge Coupl
In applications related to ed devices), the increase in the number of bits n of digital input signals is remarkable.

Since the analog output voltage corresponding to the digital input signal is created by the resistance voltage division of the voltage applied to the resistance ladder, the relative error of each unit resistance is kept low in order to improve the accuracy of the D / A converter. There is a need. Therefore, in the case where the D / A converter is realized by a semiconductor integrated circuit, when the unit resistors are arranged on the integrated circuit chip, the shape and arrangement interval of the unit resistors are made the same. However, when the number of bits n of the digital input signal increases, it is difficult to arrange the unit resistors in one column due to the layout, and the efficiency also deteriorates.

Therefore, conventionally, the unit resistors 40 are arranged in a two-dimensional array by being folded back in the middle of the resistor ladder as shown in the schematic arrangement of elements shown in FIG. Since the resistor ladder and the row of switches 44 are formed on different lines, the same contact 42 is provided between the adjacent unit resistors 40.
The metal wiring 43 is used for folding back. A resistor 41 having a resistance value R / 2 that is half that of the unit resistor 40 is arranged at both ends of the metal wiring 43 to make the resistance ladder uniform.

As described above, since the metal distribution wiring 43 made of a material different from that of the unit resistor 40 is used for folding the resistance ladder,
The resistance arrangement of the resistance ladder is as shown in FIG. In FIG. 9, R is the resistance value of the unit resistance 40, and R / 2 is the resistance 41.
, R is a wiring resistance value of the metal wiring 43, r ′ is a wiring resistance value of another folded portion (not shown), and SW is a switch 44. The wiring resistances r and r ′ are parasitic resistances that are not considered in the circuit design, and the resistance value of the folded portion is obtained by adding the wiring resistance r or r ′ to the resistance value R of the unit resistance 40. Further, in the simple folding method, as shown in FIG.
The wiring resistance is r at the position where the switch SW is folded back, and is r ′ at the position where it is simply folded back.

As a result, the expected resistance value R cannot be obtained at the folded portion. As a countermeasure, even if the resistance values of the wiring resistances r and r ′ are estimated and the resistance value of the folded portion is matched with the resistance value of the other portion, the unit resistance 40 and the metal wiring 43 have different constituent materials. The manufacturing variations do not match. After all, it is not possible to make all the resistance values the same, so that the unevenness of the resistance values is D /
It is output as an error of the analog output voltage of the A converter.

[0007] When searching for prior arts of this kind in the patent publications, Japanese Unexamined Patent Publication No. 7-86949 could be detected. The "digital-analog converter" described in this publication includes any one of a switch for selecting any connection point of the resistor strings by a digital input signal, a correction resistor network connected in series with the resistor strings, and this correction resistor network. A correction switch that selects one of the connection points, and an adder that adds the common output of the switch connected to the resistor string and the common output of the correction switch. This is because the correction resistor network eliminates the error due to the parasitic resistance generated at the folded portion of the resistor string, substantially eliminates the digital-analog conversion error voltage, improves its linearity, and achieves high precision D / A conversion. It is about to be transformed.

Another search result is Japanese Patent Laid-Open No. 3-23.
The "D / A conversion device" (prior art 2) described in Japanese Patent No. 5423 has all switches connected to unit resistances configured by a parallel connection body of a P-channel MOSFET and an N-channel MOSFET, and has no switch element. The unevenness of the stress with respect to the diffusion resistance, which occurs when the IC chip of the D / A conversion device is incorporated in a mold package which is strongly stressed due to the uniform arrangement, is prevented.
The primary purpose is to prevent the deterioration of the relative accuracy of the unit resistance due to the ezoelectric effect.

FIG. 10 is a layout pattern diagram on a semiconductor integrated circuit for a 6-bit resolution D / A conversion device disclosed in Japanese Patent Laid-Open No. 3-235423. 6
Three bits of the bit digital input signal are decoded into digital input signals X1-X8, which are used to select one of the 2 ³ switches. The remaining 3 bits of the digital input signal are then used to select one of the 2 ³ analog output voltages 01-08 connected to the selected switch. Also in FIG.
Similar to that shown in FIGS. 8 and 9, metal wiring is recognized in the folded portion. Further, it can be seen that the unit resistor strings and the switch row are arranged on different lines as shown in FIG. Unlike the case shown in FIG. 9, the resistor strings reciprocate so that the VDD terminal and the ground terminal at both ends thereof are adjacent to each other, so that the wiring resistances r and r ′ are irrespective of the parallel arrangement with the resistor strings of the switch row. The idea is to make them the same.

[0010]

However, in the above-mentioned prior art 1, since the error due to the parasitic resistance generated at the folded portion is eliminated by installing the correction resistor network,
The first problem is that the correction resistor network and the correction switch, which are elements that are not originally required, are required, which is a negative factor in cost and mounting.

Further, the time constant of the switch relating to the D / A conversion speed is determined by the combined resistance of the resistor strings and the resistance of the switch, and the input capacitance of the switch and the adder, but since the correction resistance is added, There is a second problem that it becomes large.

Further, in the above-mentioned prior art 2, regarding the folded-back portion, the folded-back portion is merely equalized, and the error due to the parasitic resistance generated in the folded-back portion is eliminated to make the resistance value uniform over the entire length of the resistor string. Since it does not extend to this, the error output of the analog output voltage of the D / A converter is accepted.

A first object of the present invention is to provide a highly accurate resistance ladder type D / A converter with a simple structure.

A second object of the present invention is to provide a resistance ladder type D / A converter which lowers the wiring resistance corresponding to the unit resistance which is required to have a low resistance as the number of bits of the D / A converter increases. To do.

[0015]

A resistance ladder type D / A converter according to the first aspect of the present invention is a resistance ladder in which unit resistances (10 in FIG. 1) are connected in series, and a reference voltage is divided by the resistance ladder. And a switch (14 in FIG. 1) corresponding to the unit resistance for selecting the resistance voltage division, and one of the resistance voltage divisions is taken out as an analog output voltage by a digital input signal. When laying out the ladder type digital / analog converter on a semiconductor integrated circuit chip, unit resistors and switches are alternately arranged on the same line, and the unit resistors are connected by metal wiring (13 in FIG. 1). The resistance ladder is configured, and the total resistance value of the unit resistance and the metal wiring is made uniform over the entire length of the resistance ladder.

According to the present invention, the unit resistances and the switches are alternately arranged on the same line, and the unit resistances are connected by the metal wiring as described above. It is possible to easily realize the same total resistance value of the resistance and the metal wiring over the entire length of the resistance ladder including the folded portion.

The resistance ladder type D / A converter of the second aspect of the present invention comprises a resistance ladder in which unit resistances (R11 etc. in FIG. 6) are connected in series, and a reference voltage (REF in FIG. 6) generated by the resistance ladder.
1, REF2) are provided with a switch (SW11, etc. in FIG. 6) corresponding to a unit resistance of a plurality of channels (two channels in FIG. 6) for independently selecting divided resistance voltage divisions, and one switch for each channel. A resistance ladder type digital / analog converter for extracting one of the resistance voltage divisions as an analog output voltage (01-1 etc. in FIG. 6) by a digital input signal (X1-1 etc. in FIG. 6) from the resistance ladder When laying out the digital-to-analog converter on a semiconductor integrated circuit chip, the unit resistors and the switches are alternately arranged on the same line with the unit resistors shared by the switches of each channel sandwiched between the unit resistors. In addition to configuring the resistance ladder by connecting with metal wiring, the total resistance value of the unit resistance and the metal wiring was made uniform throughout the length of the resistance ladder. To.

In this configuration, since one resistance ladder is shared by a plurality of channels, the chip area of the integrated circuit can be reduced as compared with the case where a plurality of layout patterns for one channel are arranged without sharing. Further, since the unit resistance and the switch are alternately arranged on the same line so as to sandwich the unit resistance shared by the switches of each channel, the switch and the unit resistance of each channel are not arranged as in the circuit diagram. It becomes possible to make the wiring connecting between and the shortest and to have the same length.

Further, the metal wiring is a layer different from the switch,
For example, if it is formed on the upper layer of the switch layer, the space for the metal wiring can be widened, so that the wiring resistance of the metal wiring can be reduced. Specifically, the N-type well layer (3 in FIG.
The P-type diffusion layer (31 and 32 in FIG. 4) formed in 9) is used as a source electrode and a drain electrode, and the gate electrode (30 in FIG. 4) is formed on the upper layer of the N-type well layer to function as a switch. P-channel MOSFET and a unit resistance region formed in the same layer as the gate electrode layer (38 in FIG. 4)
And a first-layer metal wiring (35 in FIG. 4) formed in the upper layer of the unit resistance region, connecting the source electrode and the first terminal of the unit resistance region, and the drain electrode to the analog output signal,
A second layer metal formed on the upper layer of the first layer metal wiring by connecting the first terminal and the second terminal of the unit resistance region to the second terminal, the first terminal and the gate electrode of the adjacent unit resistance with the digital input signal. Wiring (36 in FIG. 4).

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION The resistance ladder type D / of the first present invention
The A converter includes a resistance ladder in which unit resistances are connected in series, and a switch corresponding to the unit resistance that selects a resistance voltage division obtained by dividing the reference voltage by the resistance ladder. One of the resistance voltage divisions is performed by a digital input signal. In the resistance ladder type digital / analog converter for taking out as an analog output voltage, when laying out the resistance ladder type digital / analog converter on a semiconductor integrated circuit chip, unit resistors and switches are alternately arranged on the same line. The resistance ladder is configured by connecting the unit resistances with metal wiring, and the total resistance value of the unit resistance and the metal wiring is made uniform over the entire length of the resistance ladder.

The resistance ladder type D / A converter of the second aspect of the present invention comprises a resistance ladder in which unit resistances are connected in series, and a plurality of channels for independently selecting a resistance voltage division in which a reference voltage is divided by the resistance ladder. Equipped with a switch for unit resistance,
A resistance ladder type digital / analog converter for taking out one of resistance division voltages as an analog output voltage from one switch of each channel by a digital input signal,
When laying out the resistance ladder type digital / analog converter on a semiconductor integrated circuit chip, the unit resistors and the switches are alternately arranged on the same line so as to sandwich the unit resistors shared by the switches of the respective channels, and the unit resistors are arranged. The resistance ladder is formed by connecting the two to each other with a metal wiring, and the total resistance value of the unit resistance and the metal wiring is made uniform over the entire length of the resistance ladder.

[0022]

Embodiments of the present invention will now be described with reference to the drawings.

Before going into a specific content, the basic idea of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a schematic view of the element arrangement of the present invention, and is shown in a form that can be compared with FIG. 8 showing the prior art. In the present invention, as shown in FIG. 1, the unit resistors 10 and the switches 14 are alternately arranged on the same line. Between the adjacent unit resistors 10,
The metal wiring 13 that straddles the switch 14 is connected to the contact 12. The metal wiring 13 can easily have the same resistance value as the metal wiring 15 in the folded portion. Further, since the metal wiring 13 and the metal wiring 15 are arranged in the upper wiring layer, their area can be increased, and therefore the resistance value can be reduced.

FIG. 2 shows the arrangement of resistors with respect to the element arrangement of FIG. 1 and is shown in a form that can be compared with FIG. As described above, since the unit resistance 10 and the switch 14 are alternately arranged on the same line, the total resistance value of the resistance value of the unit resistance 10 and the wiring resistance value of the metal wiring 13 is “new”. It can be regarded as the resistance value R of the unit resistance RXX (XX is 11, 12, etc.). In addition, for the same reason, it is possible to minimize the difference between the wiring resistances r and r ′ shown in FIG. 9 without having to go back and forth between the folded portions as in FIG. 10 for the same reason.

FIG. 3 shows a resolution 4 which is an embodiment of the present invention.
3 shows a circuit diagram of a bit D / A converter. In FIG.
Sixteen unit resistors R11 to R14 and R21 to R that are connected in series between the reference voltage REF1 and the reference voltage REF2 and divide the potential difference between the reference voltage REF1 and the reference voltage REF2.
24, R31 to R34 and R41 to R44 are arranged in a matrix configuration of 4 rows and 4 columns. The horizontal axis of the matrix is the decoded digital input signals X1 to X4,
The vertical axis represents the analog output voltages 01 to 04. Switches SW11 to SW14, SE21 to SW24, SW31, which are P-channel MOSFETs, have a one-to-one correspondence with each unit resistance.
SW34 and SW41 to SW44 are provided. P-channel MOSFET forming each switch SW
The source terminal S is connected to the resistance ladder, the drain terminal D is connected to the analog output voltage 01 to 04 on the vertical axis, and the gate terminal G is connected to the digital input signal X on the horizontal axis.

The features of the present invention are represented in the circuit diagram by the unit resistors R24, R31 and R44 arranged at the folded portion of the resistor ladder. The resistance at this position is
As shown in FIG. 8 and FIG. 8, the unit resistance is conventionally divided into two parts. In the present invention, the accuracy of the D / A converter is improved by setting the total resistance on the resistance ladder to the unit resistance Rxx having the same resistance value. Details of this will be described later with reference to the layout pattern diagram shown in FIG.

Two bits of the 4-bit digital input signal are decoded by a decoder (not shown) to become digital input signals X1 to X4, and the remaining 2 bits of the digital input signal are decoded by a decoder and converted into analog signals. It is used to select any one of the output voltages 01 to 04. That is, the four switches SW derive the voltage division on the resistance ladder from the source terminal S to the drain terminal D by the digital input signal X, one of which is activated, and the four analog outputs to which these drain terminals D are connected. One of the voltages 01 to 04 is selected by the switch SW. Although a D / A converter having a resolution of 4 bits is shown in FIG. 3 in order to avoid complication of the drawing, the present invention assumes a D / A converter having a resolution of more bits. The switch is an n-channel MOSFET, or a C in which n-channel and p-channel MOSFETs are connected in parallel.
It may have a MOS structure.

FIG. 4 is a layout pattern diagram corresponding to the circuit diagram of FIG. In this layout pattern diagram, a multilayer structure is formed from bottom to top in the order of a white background, a dotted portion, a horizontal line portion, and a diagonal line portion. 4, 30 is a gate electrode of the switch SW to which the digital input signals X1 to X4 are supplied, 31 is a P-type diffusion electrode corresponding to the drain terminal D of the switch SW, and 32 is P corresponding to the source terminal S of the switch SW. A type diffusion electrode 33 is an N type diffusion electrode for the back gate of the P-channel MOSFET that constitutes the switch SW. The portion 35 with horizontal lines is the first-layer metal wiring, the portion 36 with diagonal lines is the second-layer metal wiring, and a small square 37 filled with black.
Is a via hole connecting the first layer metal wiring and the second layer metal wiring, and 34 is a contact connecting the diffusion layer and the electrode or the first layer metal wiring. A region 39 surrounded by a dotted line including 30 to 34 is an N-type well layer.

The dotted area 38 is a unit resistance area, and is composed of a P-type high-concentration diffusion layer formed at the same time when the source / drain areas of the P-channel MOSFET forming the switch SW are formed. Regarding the unit resistance, it is general to use N-type and P-type diffusion resistors having a high layer resistance to obtain a high resistance value, and use polysilicon resistors having a low layer resistance to obtain a low resistance value. .

Next, a method of placing and wiring each element will be described. The switch SW and the unit resistance region 38 are arranged vertically, and four sets are arranged vertically and four pieces are arranged horizontally as one set. The unit resistor 38 on the upper right is a unit resistor R11 connected to the reference voltage REF1, and the unit resistor 38 on the upper left is a unit resistor R41 connected to the reference voltage REF2. These connections are made via the contact 34 and the via hole 37. The side opposite to the side connected to the reference voltage REF1 of the unit resistor R11 is
The source electrode S of the switch SW11 arranged thereon,
That is, it is connected to the P-type diffusion electrode 32 via the first-layer metal wiring 35. Further, it is taken out to the second layer metal wiring 36 through the via hole 37 and connected to the next unit resistor R12.

The gate electrodes G of the four vertical switches SW, that is, the gate electrodes 30 are led to the second-layer metal wiring 36 through the via holes 37, and the digital input signal X is supplied thereto. Vertical four back gates B
The N-type diffusion layer 33 for G is similarly guided to the second layer metal wiring 36 through the via hole 37. The drain electrodes D of the four lateral switches SW, that is, the P-type diffusion electrodes 3
1 is led to the first-layer metal wiring 35, from which the analog output voltages 01 to 04 are taken out. In FIG. 4, the portions where the digital input signal X and the analog output voltages 01 to 04 are actually conductors, but for convenience, the names of signals and voltages on the conductors are used as they are.

Even when wiring is performed by this layout method,
As shown in FIG. 4, the folded portion 1 and the folded portion 2 are present. The folded portion 1 includes a unit resistance R14 and a unit resistance R.
24, or the unit resistance R34 and the unit resistance R44 are connected, the first via between the via holes 37 on the lower side of the unit resistance.
The second layer metal wiring 36 connects the layer metal wiring 35. On the other hand, when connecting the unit resistors R34 and R44, the folding unit 2 connects the switch SW2 between the via holes 37 above the unit resistors R21 and R31.
1 and the switch SW31 are connected by the second layer metal wiring 36. However, although the folded portions 1 and 2 have different wiring lengths, this difference can be eliminated by changing the wiring width.
Since the folded portion also uses the second-layer metal wiring 36 made of the same material as the connection between the unit resistors, the resistance value of the total resistance including the wiring resistance of the folded portion can be designed as required. It is possible. As a result, an analog output voltage with desired accuracy can be obtained.

FIG. 5 is a layout pattern diagram for clarifying the arrangement and wiring method of each element described above. Figure 5
FIG. 5A is an extracted layout pattern diagram of one block which is repeated four times in FIG.
FIG. 5B is a layout pattern diagram when the second metal wiring 36 is removed from FIG. 5A, and FIG.
Layout pattern diagrams when the first metal wiring 35 and the via hole 37 are removed from FIG.

Referring to FIG. 5C, the N-type well layer 3
P-type diffusion electrodes 31, 32 having contacts 34 at 9 and N-type diffusion electrodes 33 are formed, and P-type diffusion electrodes 31, 3 are formed.
The gate electrode 30 is disposed on the upper layer of the second layer. Further, a unit resistance region 38 is formed in the same layer as the gate electrode 30.

In FIG. 5B, the gate electrode 30, the P-type diffusion electrodes 31 and 32, the N-type diffusion electrode 33, and the contact 34.
The first-layer metal wiring 35 is applied to and. As a result, the P-type diffusion electrode 31 (drain terminal D of the switch SW), the analog output voltage 01, and the P-type diffusion electrode 32 are provided.
(The source terminal S of the switch SW) and the contact 34 below the unit resistance region 38 are connected to each other.

In FIG. 5A, the digital input signals X0 to X4 are connected to the gate electrode 30 by the second layer metal wiring 36. In addition, the first for the unit resistance region 38
The connection of the reference voltage REF1 and the second reference voltage REF2, the connection to the next unit resistance region 38, the connection of the folded portion of the resistance ladder, and the connection between the N-type diffusion electrode 33 and the back gate BG are performed by the second layer metal wiring 36. Has been done.

FIG. 6 shows a resolution 4 according to another embodiment of the present invention.
FIG. 7 is a circuit diagram of the D / A converter of bits, and FIG. 7 is a layout pattern diagram thereof. This embodiment provides two D / A converters with the same 4-bit resolution as the above-mentioned embodiments, but is characterized in that the resistance ladder is shared. 6 and 7, parts common to those in FIGS. 3 and 4 are given the same reference numerals. This D / A converter operates in two independent manners, that is, operates in two channels. In the digital input signal X and the analog output voltages 01 to 04, -1 and -2 are added after each symbol to distinguish the channels.

In FIG. 7, the switch SW of the channel 1 and the switch SW of the channel 2 are arranged so as to sandwich one unit resistor,
This is set as one set and is repeatedly connected in the same manner as in FIG. As a result, the wiring connecting the switch SW of each channel and the unit resistance can be made the shortest and have the same length, rather than arranging each element as in the circuit diagram of FIG. When arranged according to the circuit diagram of FIG. 6, for example, there is a clear difference between the wiring length from the switch SW14 of the channel 1 to the unit resistance R14 and the wiring length from the switch SW14 of the channel 2 to the unit resistance R14. In addition, the wiring length from the switch SW11 of the channel 1 to the unit resistance R11 and the switch SW14 of the channel 1 to the unit resistance R1
The same applies to the wiring length to 4. With reference to FIG. 7, it can be seen that such a difference disappears.

However, the length of the second-layer metal wiring 36 connecting the unit resistors is 4 for the switch SW for one channel.
The more you add, the longer it becomes. Therefore, in order to reduce the wiring resistance of this portion, the wiring width is made thick and the wiring width of the folded portion 1 is made thin to make the wiring resistance the same. As a result, the analog output voltages of channel 1 and channel 2 become exactly the same, and the variation between channels can be minimized.

[0040]

The first effect of the present invention is that the unit resistors and the switches are alternately arranged on the same line, and the unit resistors are connected by metal wiring. Therefore, when the resistance ladder is folded back, Since the total resistance value of the unit resistance and metal wiring can be easily equalized over the entire length of the resistance ladder including the folded portion, the resistance ladder type D / A converter with a simple structure and high accuracy can be realized. It can be provided.

The second effect of the present invention is that the metal wiring connecting the unit resistance and the switch is formed in a layer different from that of the switch,
For example, since it can be formed in the upper layer of the switch layer, the space for the metal wiring can be widened, and the wiring resistance of the metal wiring can be reduced. Therefore, the resistance reduction is required as the number of bits of the D / A converter increases. An object of the present invention is to provide a resistance ladder type D / A converter that lowers wiring resistance corresponding to unit resistance.

Furthermore, a third effect of the present invention is a resistance ladder type D / A in which one resistance ladder is shared by a plurality of channels.
In the converter, the unit resistance and the switch can be arranged alternately on the same line with the unit resistance shared by the switches of each channel sandwiched between them.Therefore, rather than arranging each element according to the circuit diagram, This means that the wiring connecting the unit resistors can be made the shortest and have the same length.

[Brief description of drawings]

FIG. 1 is a schematic diagram of element arrangement in a D / A converter for explaining the basic configuration of the present invention.

FIG. 2 is a layout view of resistors for the device layout of FIG.

FIG. 3 is a diagram showing a 4-bit resolution D / which is an embodiment of the present invention.
Circuit diagram of A converter

FIG. 4 is a layout pattern diagram corresponding to the circuit diagram of FIG.

FIG. 5 is a detailed view of the layout pattern diagram of FIG.

FIG. 6 is another embodiment of the present invention, 2 with 4-bit resolution.
Circuit diagram of channel D / A converter

7 is a layout pattern diagram corresponding to the circuit diagram of FIG.

FIG. 8 is a schematic diagram of device arrangement in a D / A converter of the related art.

9 is a layout diagram of resistors for the device layout of FIG.

FIG. 10 is a layout pattern diagram of a conventional D / A converter.

[Explanation of symbols]

01 to 04 analog output voltage 10 unit resistance 11,13 Metal wiring 12,34 contacts 14 switch 30 gate electrode 31, 32 P-type diffusion electrode 33 N-type diffusion layer 35 First layer metal wiring 36 Second layer metal wiring 37 Beer Hall 38 Unit resistance area 39 N-type well layer 01-1 to 04-1 Analog output voltage 01-2 to 04-2 Analog output voltage R unit resistance REF1, REF2 reference voltage SW switch X1 to X4 Digital input signal X1-1 to X4-1 Digital input signal X1-2 to X4-2 Digital input signal

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Claims (6)

(57) [Claims] 1. A resistor ladder in which unit resistors are connected in series,
A resistor ladder type digital / analog converter for selecting a resistance voltage division obtained by dividing the reference voltage by the resistance ladder, corresponding to the unit resistance, and taking out one of the resistance voltage divisions as an analog output voltage by a digital input signal. In arranging the resistance ladder type digital / analog converter on a semiconductor integrated circuit chip, the unit resistors and the switches are alternately arranged on the same line, and the unit resistors are connected by metal wiring. The resistance ladder type digital / analog converter is characterized in that the resistance ladder is configured so that the total resistance value of the unit resistance and the metal wiring is made uniform over the entire length of the resistance ladder. 2. A resistor ladder in which unit resistors are connected in series,
And a switch corresponding to the unit resistance of a plurality of channels for independently selecting a resistance voltage division in which the reference voltage is divided by the resistance ladder, and one of the resistance voltage divisions is selected by a digital input signal from one switch of each channel. A resistance ladder type digital / analog converter that is taken out as an analog output voltage, wherein a unit resistance shared by the switches of the respective channels is sandwiched when the resistance ladder type digital / analog converter is laid out on a semiconductor integrated circuit chip. The unit resistance and the switch are alternately arranged on the same line, and the resistance ladder is configured by connecting the unit resistances by metal wiring, and the total resistance of the unit resistance and the metal wiring is The resistance ladder type digital / analog is characterized in that the values are made uniform over the entire length of the resistance ladder. Log converter. 3. When the resistance ladder is folded back,
The resistance ladder type digital / analog converter according to claim 1 or 2, wherein the total resistance value of the unit resistance and the metal wiring is made uniform in the entire length of the resistance ladder including the folded portion. 4. The resistance ladder type digital / analog converter according to claim 1, wherein the metal wiring is formed in a layer different from that of the switch. 5. The resistance ladder type digital / analog converter according to claim 4, wherein the metal wiring is formed on an upper layer of the switch. 6. A switch having the second polarity diffusion layer formed in the first polarity well layer as a source electrode and a drain electrode formed on the upper layer of the first polarity well layer, and the switch serving as the switch. Functional second polarity MOSFE
T, a unit resistance region formed in the same layer as the gate electrode layer, the source electrode and the first terminal of the unit resistance region, and the drain electrode and the analog output signal are connected,
The first layer metal wiring formed in the upper layer of the unit resistance region, the first terminal and the second terminal of the unit resistance region adjacent to the second terminal, the first terminal, and the gate electrode of the unit resistance are digitally input. 6. The resistance ladder type digital / analog converter according to claim 5, wherein the resistance ladder type digital / analog converter includes a second layer metal wiring connected to a signal and formed on an upper layer of the first layer metal wiring.