JPH0786949A - Digital/analog converter - Google Patents

Abstract

PURPOSE:To eliminate a digital/analog(D/A) conversion error voltage, which is generated at the return part electrode of resistor strings, by providing a resistor network for correction, selection switch and adder to be serially con nected to a resistor string. CONSTITUTION:Since parasitic resistance (r) to be generated at the return part electrode of the resistor strings can not be ignored and an error is generated at the D/A converter, as a correcting voltage, the error is corrected by a correcting resistor Vk. As a concrete example, at the time of Rf/Ri=1, correcting resistance rk is turned to the double value of the parasitic resistance (r) at every time of a return part so as to correct the error. The selected correcting resistance rk is guided to an adder 4 by a switch Sk for correction, respectively outputted as the correcting voltage and becomes a value from which the linearlity distortion of removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog converter, and more particularly to a resistor string type digital / analog converter.

[0002]

2. Description of the Related Art Referring to FIG. 6 showing the structure of a conventional resistor string type digital-analog converter, a conventional resistor string type digital-analog converter is connected in series between a reference power supply VREF and ground. 2 ⁿ resistors R and one terminal of one of these resistors R is connected to 2
ⁿ switches S (1) to S (2 ⁿ ) and a decoder 60 for conducting one of the switches S (1) to S (2 ⁿ ) by the digital input signal VIN, and the switch S (1 ) To S (2 ⁿ ) have a common terminal and have a non-inverting input as a buffer amplifier 64. The resistors R1 and R2 are resistors for adjusting the minimum value and the maximum value of the analog output V0 level, and may be omitted. Also, the switches S (1) to S (2 ⁿ )
Is usually composed of a MOS transistor, and the output of the decoder 60 is connected to the gate of each switch. Further, the number of components of the resistor R and the switch is determined according to the digital input bit number n. For example, the digital input bit number is 1
In the case of 0 bit, 2 ¹⁰ = 1024 resistors R and switches are required respectively.

[0003]

In the conventional resistor string type digital-analog converter, the number of resistors R and stitches increases due to an increase in the number of digital input bats. Therefore, as shown in FIG. It is generally arranged.

That is, as shown in FIG. 7, a resistor string 1 (32 in FIG. 7) in which several tens of resistors are arranged in series and a switch having the same number as the number of resistors constituting the resistor string (32 in FIG. 7).
(Units) as units, which are repeatedly arranged in the column direction to obtain resistors and switches of a desired scale.

As a result, the resistance rope is connected by the end portion of the resistance rope 1, that is, the bent-back electrode 3A, so that parasitic resistance is added in series. The conversion speed of this type of digital-analog converter is determined by the time constant of the combined resistance of the resistor strings, the resistance of the switch, and the input capacitance of the switch and buffer amplifier.
In a digital-analog converter with a conversion speed of 00KHZ, the unit resistance that constitutes the resistance string must be several tens Ω. Further, if the number of digital input bits is increased by 1 bit, the number of resistors and switches will be doubled, so that the unit resistance also needs to be (1/2).

On the other hand, since the parasitic resistance value r cannot be reduced unless the interval between the resistance ropes 1 is narrowed in the barb return electrode 3A shown in FIG. 7, in the conventional example, the parasitic resistance due to the barb return electrode 3A increases as the number of bits increases. There is a drawback that the influence of r is remarkably exhibited. As a means for solving such a drawback, a method of designing the value of the unit resistance connected to the tilt-back electrode 3A to be smaller by the value of the parasitic resistance r,
Alternatively, as shown in FIG. 8, there is a method in which the unit resistances 1A are respectively connected by wirings 3B and the wirings 3B have the same parasitic resistance value as that of the return electrode 3A.

The former has the drawback that the resistance cannot be matched between the impurity diffusion layer or each crystalline silicon film in the semiconductor substrate constituting the unit resistance and the electrode, and the latter has the drawback that the resistance region is significantly increased. It was

[0008]

A digital-to-analog converter according to the present invention includes a decoder for decoding digital input data, a resistor string consisting of a series circuit of a plurality of unit resistors, and a connection of any of the resistor strings. A switch for selecting a point by the output of the decoder, and a digital-analog converter for generating an analog voltage according to the data decoded by the decoder, wherein a digital-analog generated at the turning-back electrode of the resistor string. A correction resistance line connected in series to the resistance string so as to substantially eliminate the conversion error voltage, a correction switch selecting one of connection points of the correction resistance line, and a common output of the correction switch. , An adder that adds the common output of the switch connected to the resistor string Obtain.

Further, the digital-analog converter of the present invention comprises a first buffer circuit which uses the common output of the correction switch as a non-inverting input, and adds the common output of the switch connected to the resistor string to the addition circuit. A non-inverting input of the adder and an output of the first buffer circuit may be an inverting input of the adder.

Further, in the digital-analog converter of the present invention, a first buffer circuit having a common output of the correction switch as a non-inverting input and a common output of the switch connected to the resistor strings are non-inverting input. And a second buffer circuit that makes the output of the second buffer circuit the non-inverting input of the adder and the output of the first buffer circuit the inverting input of the adder. You can also Furthermore, the digital-analog converter of the present invention can be configured by replacing the adder with a differential amplifier.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a resistance string type digital-analog converter according to a first embodiment of the present invention.

2 ⁿ resistors R connected in series between the reference power source VREF and ground, and 2 ⁿ switches S (1) to S (S) connected to one terminal of one end of these resistors R.
(2 ⁿ ), correction resistors rk connected in series to the 2 ⁿ resistors R connected in series, and i correction switches SK having one terminal connected to one end of these correction resistors rk.
(1) to SK (i) and one of the switches S (1) to S (2 ⁿ ) are made conductive by the digital input signal VIN to select an analog output corresponding to the digital input signal VIN, and at the same time, Switch S selected by
Correction switches SK (1) to SK that output the same correction voltage as the error voltage included in the outputs of (1) to S (2 ⁿ ).
The decoder circuit 10 for selecting (i), the buffer circuit 4 for commonizing the other terminals of the correction switches SK (1) to SK (i) for non-inverting input, and the switches S (1) to
The other terminal of S (2n) is commonly used for non-inverting input.
It is composed of an adder 5 and a resistor Rf provided between the inverting input of the adder 5 and the output of the buffer circuit 4.

Further, the resistor R and the switches S (1) to S (S).
(2 ⁿ ) is arranged as shown in FIG. 7 similarly to the conventional example, and similarly to the conventional example, the bent portion (S in FIG.
The parasitic resistance r due to the electrode 3A between (32) and S (33) is included in the circuit diagram in FIG. The output voltage V0 of the digital-analog converter according to the present invention can be expressed by the following equation.

[0015]

However, S: number of switch selected by digital input signal m: number of cage flaps included in resistor string when S-th switch is turned on r: parasitic resistance of cage flap rk: correction resistor Value K: Number of the correction switch that is turned on at the same time when the Sth switch is turned on A: Number of rk r: Current flowing through the resistor string (m) The term of (mr) i in the formula is parasitic on the return section Since this value changes depending on the ON state of the switches S (1) to S (2n), which is the error voltage due to the resistance, it appears as linear distortion in the output. In the present invention, (k · r in the second term
The error voltage can be eliminated by designing k) i to be the same as the term of (m · r) i. I.e.

[0017]

As a result, (m · r) in the equation (1)
The term of i is deleted and the following equation is obtained.

[0019]

Next, a specific example will be described (Rf / R
When i) = 1, from the equation (2), K = 2m, that is, the equation (3) is established by setting the correction resistance rk to be twice the parasitic resistance r per tilting section. This is designed by designing the correction resistance rk as a pattern having a value twice the parasitic resistance r as shown in FIG. 2, or by setting the correction resistance rk to be the same as the parasitic resistance r and by setting every other correction switch SK (1) to SK. This can be easily realized by selecting (i).

If the correction resistor rk shown in FIG. 2 is formed to have the same structure (for example, an aluminum electrode) as the deflection electrode 3A shown in FIG. 7, both of them can be matched, and the equation (3) is established. The effect can be obtained by changing.

Similarly, when (Rf / Ri) = 0.5, k = 3 m from the equation (2), that is, the correction resistance rk is set to a value three times the parasitic resistance r per tilting section. It should be designed to. Further, when K is not a positive multiple of m (Rf / Ri), the value of the correction resistor rk may be designed to be a required magnification.

Next, a second embodiment resistor string type digital-analog converter of the present invention will be described with reference to the drawings.

Referring to FIG. 5 which is a circuit diagram of a resistor string type digital-analog converter of a second embodiment according to the present invention, the digital-analog converter of this embodiment is the adder of the first embodiment. Replace 5 with differential amplifier 6,
The buffer circuit 4A having the other terminals of the correction switches SK (1) to SK (i) in common and having a non-inverting input, and the other terminals of the switches S (1) to S (2 ⁿ ) having a common non-inverting input. And a resistor Ri provided between the output of the buffer circuit 4B and the non-inverting input of the differential amplifier 6.
And a resistor Ri provided between the output of the buffer circuit 4A and the inverting input of the differential amplifier 6, a resistor Rf provided between the non-inverting input of the differential amplifier 6 and ground, and the resistor Ri of the differential amplifier 6. It is composed of a resistor Rf provided between the input and the inverting input.

The analog output voltage V0 of the digital-analog converter according to this embodiment is given by the following equation.

[0026]

However, S, m, r, rk, K, A and i are the same as in the equation (1). In this embodiment, if rk = r, K = m (5), they are included in the output voltage V0. Error voltage can be deleted, and

[0028]

From the condition of equation (5), K = m,
That is, the equation (6) is established by setting the correction resistance rk to the same value as the parasitic resistance r for each one return, and is not affected by the ratio of the resistance Ri and the resistance Rf. Therefore, the correction resistor r
There is an effect that it is sufficient to prepare as many k as the number of the bent portions of the resistor strings.

Next, a resistance string type digital-analog converter according to a third embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a plan view showing a part of the resistor string, which is obtained by further reducing and improving the resistor string shown in FIG. 7 described in the above-mentioned conventional example. That is, the contacts 2A and the electrodes 3 are evenly spaced (l1 in the figure) on the side surface of the resistance rope 1.
Is provided and the potential is divided, so that the contact on the resistance ladder is deleted and the area is reduced by that amount. In addition, the connection with the resistance line next to the barbed portion of the resistance rope 1 is connected via the contact through the barbed portion electrode 3A, as in the case shown in FIG.

In the case where such a pattern is adopted, in the conventional example, not only the parasitic resistance of the cage return electrode 3A but also the resistance of the contact 2 of the cage return portion is added as a parasitic resistance, so that the error voltage is further increased as compared with the pattern shown in FIG. Results in an increase in the linearity of the digital-analog converter.

In this embodiment, the effect described in each of the first and second embodiments can be easily obtained by forming the shape of the correction resistor shown in FIG. 3 in such a pattern. That is, the distance l between the contact 2 of the return portion and the center line of the contact 2A provided on the side portion of the resistance rope 1 as the wiring 3B having the same resistance as that of the flap portion electrode 3A in FIG.
The correction resistance rk may be formed by the unit resistance r ′ having a distance l obtained by subtracting the distance l1 between the center lines of the contacts 2A which are the sum of 2 and l3.

[0034]

As described above, according to the present invention, there are provided a correction resistance line connected in series with the resistance strings, a correction switch for selecting one of the correction resistance lines, an output of the resistance strings and a correction switch. By adding the outputs with an adder or a differential amplifier, it is possible to easily eliminate the error voltage due to the parasitic resistance generated in the tilting part when the resistance strings are placed back and placed. It has the effect of improving the linearity of the vessel and making the conversion highly accurate.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a digital-analog converter according to a first embodiment of the present invention.

FIG. 2 is a plan view of a correction resistor of the digital-analog converter shown in FIG.

FIG. 3 is a plan view of a correction resistor of a digital-analog converter according to a third exemplary embodiment of the present invention.

FIG. 4 is a plan view of resistor strings of a digital-analog converter according to a third exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram of a second embodiment digital-analog converter of the present invention.

FIG. 6 is a circuit diagram of a conventional digital-analog converter.

FIG. 7 is a plan view of resistor strings of the conventional digital-analog converter shown in FIG.

FIG. 8 is a plan view of another resistor string of the conventional digital-analog converter shown in FIG.

[Explanation of reference symbols] R resistor string unit resistance rk correction resistor S (1) to S (2 ⁿ ) resistor string switch SK (1) to SK (i) correction switch 4, 4A, 4B buffer circuit 5 adder 6 Differential amplifier 10 Decoder

Claims (4)

[Claims] 1. A decoder for decoding digital input data, a resistor string formed of a series circuit of a plurality of unit resistors, and a switch for selecting one of connection points of the resistor string by an output of the decoder, In a digital-analog converter that generates an analog voltage according to the data decoded by the decoder, the resistor strings are arranged so as to substantially eliminate the digital-analog conversion error voltage generated at the turning-back electrode of the resistor strings. A correction resistance line connected in series, a correction switch for selecting any connection point of the correction resistance line, a common output of the correction switch, and a common output of the switch connected to the resistance string. A digital-analog converter comprising: an adder for adding. 2. A first buffer circuit having a common output of the correction switch as a non-inverting input, wherein a common output of the switch connected to the resistor strings is a non-inverting input of the adder, 2. The digital-analog converter according to claim 1, wherein the output of the buffer circuit of is an inverting input of the adder. 3. A first buffer circuit having a common output of the correction switch as a non-inverting input, and a second buffer circuit having a common output of the switch connected to the resistor strings as a non-inverting input. 2. The digital-analog conversion according to claim 1, wherein the output of the second buffer circuit is a non-inverting input of the adder, and the output of the first buffer circuit is an inverting input of the adder. vessel. 4. The digital-analog converter according to claim 3, wherein the adder is replaced with a differential amplifier.